)]}'
{
  "log": [
    {
      "commit": "3f37cce66ef8b36932db08a1fb5e6486647da308",
      "tree": "b14750a924f1384018f2b56854bb82a0803441a4",
      "parents": [
        "7e08e5d2803914af4e46280b558ec1307ead9031"
      ],
      "author": {
        "name": "Arthur Heymans",
        "email": "arthur@aheymans.xyz",
        "time": "Tue Mar 03 18:52:12 2026 +0100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Jun 28 09:24:08 2026 +0000"
      },
      "message": "gma g45: Add support for Intel GM965 (Crestline)\n\nAdd GM965 as a new CPU type under the G45 generation. GM965 shares\nthe GMCH display architecture with G45/GM45 (no PCH, same connector\nregisters) but differs in PLL limits, VCO/CDClk tables, and register\nfield encoding.\n\nKey differences from G45/GM45:\n - PLL limits: Uses i9xx limits (VCO 1.4-2.8 GHz) instead of g4x\n   limits. Add I9XX_LVDS_Limits; refactor Calculate_Clock_Parameters\n   to take Limits as a parameter, with a new Select_Limits function.\n - VCO: Uses Crestline (CL) VCO tables with different frequencies\n   and divisors than GM45\u0027s Cantiga (CTG) tables.\n - CDClk: GCFGC register decoding uses bits 12:8 minus 1 (3 possible\n   divisor selections), unlike GM45\u0027s single bit 12.\n - No native DisplayPort (SDVO B/C only).\n - No HD Audio (G4X_AUD_VID_DID reads as 0).\n - Has integrated LVDS transmitter (mobile platform).\n - PCI IDs: 0x2a02 (I965_GM), 0x2a12 (I965_GME).\n\nAll implementation details cross-referenced against the Linux kernel\ni915 driver (intel_dpll.c, intel_cdclk.c, intel_display_device.c).\n\nChange-Id: I0d5d698cc1c2aa84778f0fc6c2752cb5ce4f1cb2\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/499\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n"
    },
    {
      "commit": "41e8674b7180778ed4beec9fc55c988aef330ebe",
      "tree": "839a4ffa6f5602f9b2f4a9487f0432cb86ad09c5",
      "parents": [
        "1b99185ac3275f8d231e734a92d4f1e25a2eb829"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.huber@secunet.com",
        "time": "Wed Jul 17 17:10:28 2024 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat Jun 06 10:28:13 2026 +0000"
      },
      "message": "gma power: Allow to explicitly enable DDI/Aux power\n\nWe used to enable power for DP-aux channels quite implicitly by faking\nconfigs that use a specific port.  As Tiger Lake requires us to enable\na DDI port\u0027s power late during the modesetting sequence,  we introduce\na new API for such cases, and also use it for the DP-aux case.\n\nTested on HSW, and BXT \u0026 CFL where we enable PW2 explicitly now.\n\nChange-Id: I1fd6348ff4855557166495613c6a181f85a818f4\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/461\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n"
    },
    {
      "commit": "b47a5c479358a4cecf2589295b37954edd1e36e5",
      "tree": "8a84cb4ae9f3f8384e233c61eeb1de6c32b3d423",
      "parents": [
        "07ff1b95bb1db12cc3d01e3f542338d25eb2dbf3"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Sep 29 00:07:21 2019 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Oct 18 12:19:16 2019 +0000"
      },
      "message": "gma g45: Read CDClk and calculate dot-clock limits\n\nNumbers are taken from `intel_cdclk.c` of Linux\u0027 i915 driver.\n\nWe introduce three new procedures to the `Power_And_Clocks` interface:\n\n  o Limit_Dotclocks() limits the dot clocks of all pipe configs\n    according to the maximum supported CDClk. It also reports if\n    CDClk has to be switched for these configs.\n\n  o Update_CDClk() performs the CDClk switch if necessary. It may\n    further limit the dot clocks if the switch didn\u0027t succeed.\n\n  o Enable_CDClk() ensures that the CDClk is running. This may be\n    necessary to probe for DP displays when no pipes are active.\n\nThe latter two are no-ops for G45, as the CDClk runs at a fixed rate.\nDot clocks are limited to 90% of CDClk.\n\nChange-Id: Ie50c0f8f51b3a0a6ed58c6461069c556cc92f51e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/libgfxinit/+/35715\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n"
    },
    {
      "commit": "73ea03245445527a80b70e41cf4a910371014ca0",
      "tree": "210fafb8ff5631b2946bdd4511271293b2f8a27c",
      "parents": [
        "d5198445517c361b30f4521e52b953d2a7928a70"
      ],
      "author": {
        "name": "Arthur Heymans",
        "email": "arthur@aheymans.xyz",
        "time": "Wed Mar 28 17:17:07 2018 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Jun 03 20:33:18 2018 +0000"
      },
      "message": "gma: Add G45 support\n\nThe following ports are implemented: HDMI/DVI, VGA, LVDS and DP.\n\nTested with gfx_test and coreboot on a Thinkpad X200 (GM45).\n\nChange-Id: Ifc05a1516329a61772af84558e5bfceb4d4ca277\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-on: https://review.coreboot.org/21295\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n"
    }
  ]
}