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Nico Huber83693c82016-10-08 22:17:55 +02001--
Nico Huberfdb0df12018-02-07 14:30:34 +01002-- Copyright (C) 2015-2018 secunet Security Networks AG
Nico Huber83693c82016-10-08 22:17:55 +02003--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +02006-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +02008--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with HW.Debug;
16with GNAT.Source_Info;
17
18with HW.GFX.GMA.Config;
Nico Huber7ad2d652016-12-07 15:19:32 +010019with HW.GFX.GMA.Transcoder;
Nico Huber83693c82016-10-08 22:17:55 +020020
21package body HW.GFX.GMA.Pipe_Setup is
22
Nico Huberfbb42202016-11-07 15:08:26 +010023 ILK_DISPLAY_CHICKEN1_VGA_MASK : constant := 7 * 2 ** 29;
24 ILK_DISPLAY_CHICKEN1_VGA_ENABLE : constant := 5 * 2 ** 29;
25 ILK_DISPLAY_CHICKEN2_VGA_MASK : constant := 1 * 2 ** 25;
26 ILK_DISPLAY_CHICKEN2_VGA_ENABLE : constant := 0 * 2 ** 25;
27
Nico Huber7ad2d652016-12-07 15:19:32 +010028 DSPCNTR_ENABLE : constant := 1 * 2 ** 31;
29 DSPCNTR_GAMMA_CORRECTION : constant := 1 * 2 ** 30;
Nico Huber7ad2d652016-12-07 15:19:32 +010030 DSPCNTR_FORMAT_MASK : constant := 15 * 2 ** 26;
Nico Huberab69e362018-05-29 21:20:30 +020031 DSPCNTR_DISABLE_TRICKLE_FEED : constant := 1 * 2 ** 14;
32 DSPCNTR_TILED_SURFACE_LINEAR : constant := 0 * 2 ** 10;
33 DSPCNTR_TILED_SURFACE_X_TILED : constant := 1 * 2 ** 10;
34
35 DSPCNTR_TILED_SURFACE : constant array (Tiling_Type) of Word32 :=
36 (Linear => DSPCNTR_TILED_SURFACE_LINEAR,
37 X_Tiled => DSPCNTR_TILED_SURFACE_X_TILED,
38 Y_Tiled => 0); -- unsupported
Nico Huber83693c82016-10-08 22:17:55 +020039
40 DSPCNTR_MASK : constant Word32 :=
41 DSPCNTR_ENABLE or
42 DSPCNTR_GAMMA_CORRECTION or
43 DSPCNTR_FORMAT_MASK or
Nico Huberab69e362018-05-29 21:20:30 +020044 DSPCNTR_DISABLE_TRICKLE_FEED or
45 DSPCNTR_TILED_SURFACE_X_TILED;
Nico Huber83693c82016-10-08 22:17:55 +020046
47 PLANE_CTL_PLANE_ENABLE : constant := 1 * 2 ** 31;
48 PLANE_CTL_SRC_PIX_FMT_RGB_32B_8888 : constant := 4 * 2 ** 24;
49 PLANE_CTL_PLANE_GAMMA_DISABLE : constant := 1 * 2 ** 13;
Nico Huber0164b022017-08-24 15:12:51 +020050 PLANE_CTL_TILED_SURFACE_MASK : constant := 7 * 2 ** 10;
51 PLANE_CTL_TILED_SURFACE_LINEAR : constant := 0 * 2 ** 10;
52 PLANE_CTL_TILED_SURFACE_X_TILED : constant := 1 * 2 ** 10;
53 PLANE_CTL_TILED_SURFACE_Y_TILED : constant := 4 * 2 ** 10;
54 PLANE_CTL_TILED_SURFACE_YF_TILED : constant := 5 * 2 ** 10;
55
56 PLANE_CTL_TILED_SURFACE : constant array (Tiling_Type) of Word32 :=
57 (Linear => PLANE_CTL_TILED_SURFACE_LINEAR,
58 X_Tiled => PLANE_CTL_TILED_SURFACE_X_TILED,
59 Y_Tiled => PLANE_CTL_TILED_SURFACE_Y_TILED);
Nico Huber83693c82016-10-08 22:17:55 +020060
Nico Huber9b479412017-08-27 11:55:56 +020061 PLANE_CTL_PLANE_ROTATION_MASK : constant := 3 * 2 ** 0;
62 PLANE_CTL_PLANE_ROTATION : constant array (Rotation_Type) of Word32 :=
63 (No_Rotation => 0 * 2 ** 0,
64 Rotated_90 => 1 * 2 ** 0,
65 Rotated_180 => 2 * 2 ** 0,
66 Rotated_270 => 3 * 2 ** 0);
67
Nico Huber83693c82016-10-08 22:17:55 +020068 PLANE_WM_ENABLE : constant := 1 * 2 ** 31;
69 PLANE_WM_LINES_SHIFT : constant := 14;
70 PLANE_WM_LINES_MASK : constant := 16#001f# * 2 ** 14;
71 PLANE_WM_BLOCKS_MASK : constant := 16#03ff# * 2 ** 0;
72
Nico Huber33912aa2016-12-06 20:36:23 +010073 VGA_SR_INDEX : constant := 16#03c4#;
74 VGA_SR_DATA : constant := 16#03c5#;
75 VGA_SR01 : constant := 16#01#;
76 VGA_SR01_SCREEN_OFF : constant := 1 * 2 ** 5;
Nico Huber3675db52016-11-04 16:27:29 +010077
78 VGA_CONTROL_VGA_DISPLAY_DISABLE : constant := 1 * 2 ** 31;
79 VGA_CONTROL_BLINK_DUTY_CYCLE_MASK : constant := 16#0003# * 2 ** 6;
80 VGA_CONTROL_BLINK_DUTY_CYCLE_50 : constant := 2 * 2 ** 6;
81 VGA_CONTROL_VSYNC_BLINK_RATE_MASK : constant := 16#003f# * 2 ** 0;
82
Nico Huber4dc4c612018-01-10 15:55:09 +010083 CUR_CTL_PIPE_SELECT : constant array (Pipe_Index) of Word32 :=
84 (Primary => 0 * 2 ** 28,
85 Secondary => 1 * 2 ** 28,
86 Tertiary => 2 * 2 ** 28);
87 CUR_CTL_MODE : constant array (Cursor_Mode, Cursor_Size) of Word32 :=
88 (No_Cursor => (others => 16#00#),
89 ARGB_Cursor =>
90 (Cursor_64x64 => 16#27#,
91 Cursor_128x128 => 16#22#,
92 Cursor_256x256 => 16#23#));
93
94 function CUR_POS_Y (Y : Int32) return Word32 is
95 ((if Y >= 0 then 0 else 1 * 2 ** 31) or Shift_Left (Word32 (abs Y), 16))
96 with
97 Pre => Y > Int32'First;
98 function CUR_POS_X (X : Int32) return Word32 is
99 ((if X >= 0 then 0 else 1 * 2 ** 15) or Word32 (abs X))
100 with
101 Pre => X > Int32'First;
102
Nico Huber3675db52016-11-04 16:27:29 +0100103 subtype VGA_Cycle_Count is Pos32 range 2 .. 128;
104 function VGA_CONTROL_VSYNC_BLINK_RATE
105 (Cycles : VGA_Cycle_Count)
106 return Word32
107 is
108 begin
109 return Word32 (Cycles) / 2 - 1;
110 end VGA_CONTROL_VSYNC_BLINK_RATE;
111
Nico Huber7ad2d652016-12-07 15:19:32 +0100112 PF_CTRL_ENABLE : constant := 1 * 2 ** 31;
113 PF_CTRL_PIPE_SELECT_MASK : constant := 3 * 2 ** 29;
114 PF_CTRL_FILTER_MED : constant := 1 * 2 ** 23;
Nico Huber83693c82016-10-08 22:17:55 +0200115
Nico Huber7ad2d652016-12-07 15:19:32 +0100116 PS_CTRL_ENABLE_SCALER : constant := 1 * 2 ** 31;
117 PS_CTRL_SCALER_MODE_7X5_EXTENDED : constant := 1 * 2 ** 28;
118 PS_CTRL_FILTER_SELECT_MEDIUM_2 : constant := 1 * 2 ** 23;
Nico Huber83693c82016-10-08 22:17:55 +0200119
Arthur Heymansd5198442018-03-28 17:05:12 +0200120 GMCH_PFIT_CONTROL_SELECT_MASK : constant := 3 * 2 ** 29;
121 GMCH_PFIT_CONTROL_SELECT_PIPE_A : constant := 0 * 2 ** 29;
122 GMCH_PFIT_CONTROL_SELECT_PIPE_B : constant := 1 * 2 ** 29;
Nico Huber958c5642018-06-02 16:59:31 +0200123 GMCH_PFIT_CONTROL_SCALING_MASK : constant := 3 * 2 ** 26;
124 GMCH_PFIT_CONTROL_SCALING : constant array (Scaling_Aspect) of Word32 :=
125 (Uniform => 0 * 2 ** 26,
126 Pillarbox => 2 * 2 ** 26,
127 Letterbox => 3 * 2 ** 26);
Arthur Heymansd5198442018-03-28 17:05:12 +0200128
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200129 VGACNTRL_REG : constant Registers.Registers_Index :=
130 (if Config.Has_GMCH_VGACNTRL then
131 Registers.GMCH_VGACNTRL
132 else Registers.CPU_VGACNTRL);
133
Nico Huber83693c82016-10-08 22:17:55 +0200134 ---------------------------------------------------------------------------
135
Nico Huber83693c82016-10-08 22:17:55 +0200136 function PLANE_WM_LINES (Lines : Natural) return Word32 is
137 begin
138 return Shift_Left (Word32 (Lines), PLANE_WM_LINES_SHIFT)
139 and PLANE_WM_LINES_MASK;
140 end PLANE_WM_LINES;
141
142 function PLANE_WM_BLOCKS (Blocks : Natural) return Word32 is
143 begin
144 return Word32 (Blocks) and PLANE_WM_BLOCKS_MASK;
145 end PLANE_WM_BLOCKS;
146
147 ---------------------------------------------------------------------------
148
149 function Encode (LSW, MSW : Pos16) return Word32 is
150 begin
Nico Huber7ad2d652016-12-07 15:19:32 +0100151 return Shift_Left (Word32 (MSW) - 1, 16) or (Word32 (LSW) - 1);
Nico Huber83693c82016-10-08 22:17:55 +0200152 end Encode;
153
154 ----------------------------------------------------------------------------
155
Nico Huber83693c82016-10-08 22:17:55 +0200156 procedure Clear_Watermarks (Controller : Controller_Type) is
157 begin
Nico Huber4dc4c612018-01-10 15:55:09 +0100158 Registers.Write (Controller.CUR_BUF_CFG, 16#0000_0000#);
159 for Level in WM_Levels loop
160 Registers.Write (Controller.CUR_WM (Level), 16#0000_0000#);
Nico Huber83693c82016-10-08 22:17:55 +0200161 end loop;
Nico Huber4dc4c612018-01-10 15:55:09 +0100162 Registers.Write (Controller.PLANE_BUF_CFG, 16#0000_0000#);
163 for Level in WM_Levels loop
164 Registers.Write (Controller.PLANE_WM (Level), 16#0000_0000#);
165 end loop;
166 Registers.Write (Controller.WM_LINETIME, 16#0000_0000#);
Nico Huber83693c82016-10-08 22:17:55 +0200167 end Clear_Watermarks;
168
169 procedure Setup_Watermarks (Controller : Controller_Type)
170 is
Nico Huberf3e23662016-12-05 21:33:03 +0100171 type Per_Plane_Buffer_Range is array (Pipe_Index) of Word32;
Nico Huber4dc4c612018-01-10 15:55:09 +0100172 Cur_Buffer_Range : constant Per_Plane_Buffer_Range :=
173 (Primary => Shift_Left ( 7, 16) or 0,
174 Secondary => Shift_Left (167, 16) or 160,
175 Tertiary => Shift_Left (327, 16) or 320);
176 Plane_Buffer_Range : constant Per_Plane_Buffer_Range :=
177 (Primary => Shift_Left (159, 16) or 8,
178 Secondary => Shift_Left (319, 16) or 168,
179 Tertiary => Shift_Left (479, 16) or 328);
Nico Huber83693c82016-10-08 22:17:55 +0200180 begin
181 Registers.Write
182 (Register => Controller.PLANE_BUF_CFG,
Nico Huber4dc4c612018-01-10 15:55:09 +0100183 Value => Plane_Buffer_Range (Controller.Pipe));
Nico Huber83693c82016-10-08 22:17:55 +0200184 Registers.Write
185 (Register => Controller.PLANE_WM (0),
186 Value => PLANE_WM_ENABLE or
187 PLANE_WM_LINES (2) or
Nico Huber4dc4c612018-01-10 15:55:09 +0100188 PLANE_WM_BLOCKS (152));
189 Registers.Write
190 (Register => Controller.CUR_BUF_CFG,
191 Value => Cur_Buffer_Range (Controller.Pipe));
192 Registers.Write
193 (Register => Controller.CUR_WM (0),
194 Value => PLANE_WM_ENABLE or
195 PLANE_WM_LINES (2) or
196 PLANE_WM_BLOCKS (8));
Nico Huber83693c82016-10-08 22:17:55 +0200197 end Setup_Watermarks;
198
199 ----------------------------------------------------------------------------
200
Nico Huber3675db52016-11-04 16:27:29 +0100201 procedure Setup_Hires_Plane
Nico Huber6a4dfc82016-11-04 15:50:58 +0100202 (Controller : Controller_Type;
Nico Huber0164b022017-08-24 15:12:51 +0200203 FB : HW.GFX.Framebuffer_Type)
Nico Huber83693c82016-10-08 22:17:55 +0200204 with
205 Global => (In_Out => Registers.Register_State),
206 Depends =>
207 (Registers.Register_State
208 =>+
209 (Registers.Register_State,
210 Controller,
Nico Huber9b479412017-08-27 11:55:56 +0200211 FB)),
Nico Huber5ef4d602017-12-13 13:56:47 +0100212 Pre => FB.Height + FB.Start_Y <= FB.V_Stride
Nico Huber83693c82016-10-08 22:17:55 +0200213 is
214 -- FIXME: setup correct format, based on framebuffer RGB format
215 Format : constant Word32 := 6 * 2 ** 26;
216 PRI : Word32 := DSPCNTR_ENABLE or Format;
Nico Huber83693c82016-10-08 22:17:55 +0200217 begin
218 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
219
Nico Huber83693c82016-10-08 22:17:55 +0200220 if Config.Has_Plane_Control then
Nico Huber9b479412017-08-27 11:55:56 +0200221 declare
Nico Huber34be6542017-12-13 09:26:24 +0100222 Stride, Offset : Word32;
Nico Huber9b479412017-08-27 11:55:56 +0200223 Width : constant Pos16 := Rotated_Width (FB);
224 Height : constant Pos16 := Rotated_Height (FB);
225 begin
226 if Rotation_90 (FB) then
Nico Huber5ef4d602017-12-13 13:56:47 +0100227 Stride := Word32 (FB_Pitch (FB.V_Stride, FB));
228 Offset := Shift_Left (Word32 (FB.Start_X), 16) or
229 Word32 (FB.V_Stride - FB.Height - FB.Start_Y);
Nico Huber9b479412017-08-27 11:55:56 +0200230 else
Nico Huber5ef4d602017-12-13 13:56:47 +0100231 Stride := Word32 (FB_Pitch (FB.Stride, FB));
232 Offset := Shift_Left (Word32 (FB.Start_Y), 16) or
233 Word32 (FB.Start_X);
Nico Huber9b479412017-08-27 11:55:56 +0200234 end if;
235 Registers.Write
236 (Register => Controller.PLANE_CTL,
237 Value => PLANE_CTL_PLANE_ENABLE or
238 PLANE_CTL_SRC_PIX_FMT_RGB_32B_8888 or
239 PLANE_CTL_PLANE_GAMMA_DISABLE or
240 PLANE_CTL_TILED_SURFACE (FB.Tiling) or
241 PLANE_CTL_PLANE_ROTATION (FB.Rotation));
242 Registers.Write (Controller.PLANE_OFFSET, Offset);
243 Registers.Write (Controller.PLANE_SIZE, Encode (Width, Height));
244 Registers.Write (Controller.PLANE_STRIDE, Stride);
245 Registers.Write (Controller.PLANE_POS, 16#0000_0000#);
Nico Huber34be6542017-12-13 09:26:24 +0100246 Registers.Write (Controller.PLANE_SURF, FB.Offset and 16#ffff_f000#);
Nico Huber9b479412017-08-27 11:55:56 +0200247 end;
Nico Huber83693c82016-10-08 22:17:55 +0200248 else
249 if Config.Disable_Trickle_Feed then
250 PRI := PRI or DSPCNTR_DISABLE_TRICKLE_FEED;
251 end if;
252 -- for now, just disable gamma LUT (can't do anything
253 -- useful without colorimetry information from display)
254 Registers.Unset_And_Set_Mask
255 (Register => Controller.DSPCNTR,
256 Mask_Unset => DSPCNTR_MASK,
Nico Huberab69e362018-05-29 21:20:30 +0200257 Mask_Set => PRI or DSPCNTR_TILED_SURFACE (FB.Tiling));
Nico Huber83693c82016-10-08 22:17:55 +0200258
Nico Huber0164b022017-08-24 15:12:51 +0200259 Registers.Write
260 (Controller.DSPSTRIDE, Word32 (Pixel_To_Bytes (FB.Stride, FB)));
Nico Huberab69e362018-05-29 21:20:30 +0200261 if Config.Has_DSP_Linoff and then FB.Tiling = Linear then
Nico Huber5ef4d602017-12-13 13:56:47 +0100262 Registers.Write
263 (Register => Controller.DSPLINOFF,
264 Value => Word32 (Pixel_To_Bytes
265 (FB.Start_Y * FB.Stride + FB.Start_X, FB)));
266 Registers.Write (Controller.DSPTILEOFF, 0);
267 else
Nico Huberab69e362018-05-29 21:20:30 +0200268 if Config.Has_DSP_Linoff then
269 Registers.Write (Controller.DSPLINOFF, 0);
270 end if;
Nico Huber5ef4d602017-12-13 13:56:47 +0100271 Registers.Write
272 (Register => Controller.DSPTILEOFF,
273 Value => Shift_Left (Word32 (FB.Start_Y), 16) or
274 Word32 (FB.Start_X));
Nico Huber83693c82016-10-08 22:17:55 +0200275 end if;
Nico Huber8fd92a12018-01-02 14:02:59 +0100276 Registers.Write (Controller.DSPSURF, FB.Offset and 16#ffff_f000#);
Nico Huber83693c82016-10-08 22:17:55 +0200277 end if;
Nico Huber3675db52016-11-04 16:27:29 +0100278 end Setup_Hires_Plane;
279
280 procedure Setup_Display
Nico Huber113a14b2016-12-06 21:59:15 +0100281 (Controller : Controller_Type;
282 Framebuffer : Framebuffer_Type;
283 Dither_BPC : BPC_Type;
284 Dither : Boolean)
Nico Huber3675db52016-11-04 16:27:29 +0100285 with
286 Global => (In_Out => (Registers.Register_State, Port_IO.State)),
287 Depends =>
288 (Registers.Register_State
289 =>+
290 (Registers.Register_State,
291 Controller,
Nico Huber113a14b2016-12-06 21:59:15 +0100292 Framebuffer,
293 Dither_BPC,
294 Dither),
Nico Huber3675db52016-11-04 16:27:29 +0100295 Port_IO.State
296 =>+
Nico Huber9b479412017-08-27 11:55:56 +0200297 (Framebuffer)),
298 Pre =>
299 Framebuffer.Offset = VGA_PLANE_FRAMEBUFFER_OFFSET or
Nico Huber5ef4d602017-12-13 13:56:47 +0100300 Framebuffer.Height + Framebuffer.Start_Y <= Framebuffer.V_Stride
Nico Huber3675db52016-11-04 16:27:29 +0100301 is
302 use type Word8;
303
304 Reg8 : Word8;
305 begin
306 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
307
308 if Config.Has_Plane_Control then
309 Setup_Watermarks (Controller);
310 end if;
311
312 if Framebuffer.Offset = VGA_PLANE_FRAMEBUFFER_OFFSET then
Nico Huberfbb42202016-11-07 15:08:26 +0100313 if Config.VGA_Plane_Workaround then
314 Registers.Unset_And_Set_Mask
315 (Register => Registers.ILK_DISPLAY_CHICKEN1,
316 Mask_Unset => ILK_DISPLAY_CHICKEN1_VGA_MASK,
317 Mask_Set => ILK_DISPLAY_CHICKEN1_VGA_ENABLE);
318 Registers.Unset_And_Set_Mask
319 (Register => Registers.ILK_DISPLAY_CHICKEN2,
320 Mask_Unset => ILK_DISPLAY_CHICKEN2_VGA_MASK,
321 Mask_Set => ILK_DISPLAY_CHICKEN2_VGA_ENABLE);
322 end if;
323
Nico Huber3675db52016-11-04 16:27:29 +0100324 Registers.Unset_And_Set_Mask
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200325 (Register => VGACNTRL_REG,
Nico Huber3675db52016-11-04 16:27:29 +0100326 Mask_Unset => VGA_CONTROL_VGA_DISPLAY_DISABLE or
327 VGA_CONTROL_BLINK_DUTY_CYCLE_MASK or
328 VGA_CONTROL_VSYNC_BLINK_RATE_MASK,
329 Mask_Set => VGA_CONTROL_BLINK_DUTY_CYCLE_50 or
330 VGA_CONTROL_VSYNC_BLINK_RATE (30));
331
332 Port_IO.OutB (VGA_SR_INDEX, VGA_SR01);
333 Port_IO.InB (Reg8, VGA_SR_DATA);
334 Port_IO.OutB (VGA_SR_DATA, Reg8 and not (VGA_SR01_SCREEN_OFF));
335 else
Nico Huber6a4dfc82016-11-04 15:50:58 +0100336 Setup_Hires_Plane (Controller, Framebuffer);
Nico Huber3675db52016-11-04 16:27:29 +0100337 end if;
338
339 Registers.Write
340 (Register => Controller.PIPESRC,
341 Value => Encode
Nico Huber9b479412017-08-27 11:55:56 +0200342 (Rotated_Height (Framebuffer), Rotated_Width (Framebuffer)));
Nico Huber83693c82016-10-08 22:17:55 +0200343
Nico Huber113a14b2016-12-06 21:59:15 +0100344 if Config.Has_Pipeconf_Misc then
345 Registers.Write
346 (Register => Controller.PIPEMISC,
Nico Huber7ad2d652016-12-07 15:19:32 +0100347 Value => Transcoder.BPC_Conf (Dither_BPC, Dither));
Nico Huber113a14b2016-12-06 21:59:15 +0100348 end if;
Nico Huber83693c82016-10-08 22:17:55 +0200349 end Setup_Display;
350
351 ----------------------------------------------------------------------------
352
Nico Huber4dc4c612018-01-10 15:55:09 +0100353 procedure Update_Cursor
354 (Pipe : Pipe_Index;
355 FB : Framebuffer_Type;
356 Cursor : Cursor_Type)
357 is
358 begin
359 -- on some platforms writing CUR_CTL disables self-arming of CUR_POS
360 -- so keep it first
361 Registers.Write
362 (Register => Controllers (Pipe).CUR_CTL,
363 Value => CUR_CTL_PIPE_SELECT (Pipe) or
364 CUR_CTL_MODE (Cursor.Mode, Cursor.Size));
365 Place_Cursor (Pipe, FB, Cursor);
366 end Update_Cursor;
367
368 procedure Place_Cursor
369 (Pipe : Pipe_Index;
370 FB : Framebuffer_Type;
371 Cursor : Cursor_Type)
372 is
373 Width : constant Width_Type := Cursor_Width (Cursor.Size);
374 X : Int32 := Cursor.Center_X - Width / 2;
375 Y : Int32 := Cursor.Center_Y - Width / 2;
376 begin
377 -- off-screen cursor needs special care
378 if X <= -Width or Y <= -Width or
379 X >= Int32 (Rotated_Width (FB)) or Y >= Int32 (Rotated_Height (FB)) or
380 X > Config.Maximum_Cursor_X or Y > Config.Maximum_Cursor_Y
381 then
382 X := -Width;
383 Y := -Width;
384 end if;
385 Registers.Write
386 (Register => Controllers (Pipe).CUR_POS,
387 Value => CUR_POS_Y (Y) or CUR_POS_X (X));
388 -- write to CUR_BASE always arms other CUR_* registers
389 Registers.Write
390 (Register => Controllers (Pipe).CUR_BASE,
391 Value => Shift_Left (Word32 (Cursor.GTT_Offset), 12));
392 end Place_Cursor;
393
394 ----------------------------------------------------------------------------
395
Nico Huber4916e342016-11-04 14:37:53 +0100396 procedure Scale_Keep_Aspect
397 (Width : out Pos32;
398 Height : out Pos32;
399 Max_Width : in Pos32;
400 Max_Height : in Pos32;
401 Framebuffer : in Framebuffer_Type)
402 with
403 Pre =>
404 Max_Width <= Pos32 (Pos16'Last) and
405 Max_Height <= Pos32 (Pos16'Last) and
Nico Huber9b479412017-08-27 11:55:56 +0200406 Pos32 (Rotated_Width (Framebuffer)) <= Max_Width and
407 Pos32 (Rotated_Height (Framebuffer)) <= Max_Height,
Nico Huber4916e342016-11-04 14:37:53 +0100408 Post =>
409 Width <= Max_Width and Height <= Max_Height
410 is
Nico Huber9b479412017-08-27 11:55:56 +0200411 Src_Width : constant Pos32 := Pos32 (Rotated_Width (Framebuffer));
412 Src_Height : constant Pos32 := Pos32 (Rotated_Height (Framebuffer));
Nico Huber4916e342016-11-04 14:37:53 +0100413 begin
Nico Huber9b479412017-08-27 11:55:56 +0200414 if (Max_Width * Src_Height) / Src_Width <= Max_Height then
Nico Huber4916e342016-11-04 14:37:53 +0100415 Width := Max_Width;
Nico Huber9b479412017-08-27 11:55:56 +0200416 Height := (Max_Width * Src_Height) / Src_Width;
Nico Huber4916e342016-11-04 14:37:53 +0100417 else
418 Height := Max_Height;
419 Width := Pos32'Min (Max_Width, -- could prove, it's <= Max_Width
Nico Huber9b479412017-08-27 11:55:56 +0200420 (Max_Height * Src_Width) / Src_Height);
Nico Huber4916e342016-11-04 14:37:53 +0100421 end if;
422 end Scale_Keep_Aspect;
423
424 procedure Setup_Skylake_Pipe_Scaler
425 (Controller : in Controller_Type;
426 Mode : in HW.GFX.Mode_Type;
427 Framebuffer : in HW.GFX.Framebuffer_Type)
428 with
429 Pre =>
Nico Huber9b479412017-08-27 11:55:56 +0200430 Rotated_Width (Framebuffer) <= Mode.H_Visible and
431 Rotated_Height (Framebuffer) <= Mode.V_Visible
Nico Huber4916e342016-11-04 14:37:53 +0100432 is
Nico Huber7ad2d652016-12-07 15:19:32 +0100433 use type Registers.Registers_Invalid_Index;
434
Nico Huber4916e342016-11-04 14:37:53 +0100435 -- Enable 7x5 extended mode where possible:
436 Scaler_Mode : constant Word32 :=
437 (if Controller.PS_CTRL_2 /= Registers.Invalid_Register then
438 PS_CTRL_SCALER_MODE_7X5_EXTENDED else 0);
439
Nico Huber9b479412017-08-27 11:55:56 +0200440 Width_In : constant Pos32 := Pos32 (Rotated_Width (Framebuffer));
441 Height_In : constant Pos32 := Pos32 (Rotated_Height (Framebuffer));
442
Nico Huber4916e342016-11-04 14:37:53 +0100443 -- We can scale up to 2.99x horizontally:
Nico Huber9b479412017-08-27 11:55:56 +0200444 Horizontal_Limit : constant Pos32 := (Width_In * 299) / 100;
Nico Huber4916e342016-11-04 14:37:53 +0100445 -- The third scaler is limited to 1.99x
446 -- vertical scaling for source widths > 2048:
447 Vertical_Limit : constant Pos32 :=
Nico Huber9b479412017-08-27 11:55:56 +0200448 (Height_In *
Nico Huber4916e342016-11-04 14:37:53 +0100449 (if Controller.PS_CTRL_2 = Registers.Invalid_Register and
Nico Huber9b479412017-08-27 11:55:56 +0200450 Width_In > 2048
Nico Huber4916e342016-11-04 14:37:53 +0100451 then
452 199
453 else
454 299)) / 100;
455
456 Width, Height : Pos32;
457 begin
458 -- Writes to WIN_SZ arm the PS registers.
459
460 Scale_Keep_Aspect
461 (Width => Width,
462 Height => Height,
463 Max_Width => Pos32'Min (Horizontal_Limit, Pos32 (Mode.H_Visible)),
464 Max_Height => Pos32'Min (Vertical_Limit, Pos32 (Mode.V_Visible)),
465 Framebuffer => Framebuffer);
466
467 Registers.Write
468 (Register => Controller.PS_CTRL_1,
469 Value => PS_CTRL_ENABLE_SCALER or Scaler_Mode);
470 Registers.Write
471 (Register => Controller.PS_WIN_POS_1,
472 Value =>
473 Shift_Left (Word32 (Pos32 (Mode.H_Visible) - Width) / 2, 16) or
474 Word32 (Pos32 (Mode.V_Visible) - Height) / 2);
475 Registers.Write
476 (Register => Controller.PS_WIN_SZ_1,
477 Value => Shift_Left (Word32 (Width), 16) or Word32 (Height));
478 end Setup_Skylake_Pipe_Scaler;
479
480 procedure Setup_Ironlake_Panel_Fitter
481 (Controller : in Controller_Type;
482 Mode : in HW.GFX.Mode_Type;
483 Framebuffer : in HW.GFX.Framebuffer_Type)
484 with
485 Pre =>
Nico Huber9b479412017-08-27 11:55:56 +0200486 Rotated_Width (Framebuffer) <= Mode.H_Visible and
487 Rotated_Height (Framebuffer) <= Mode.V_Visible
Nico Huber4916e342016-11-04 14:37:53 +0100488 is
489 -- Force 1:1 mapping of panel fitter:pipe
490 PF_Ctrl_Pipe_Sel : constant Word32 :=
491 (if Config.Has_PF_Pipe_Select then
492 (case Controller.PF_CTRL is
493 when Registers.PFA_CTL_1 => 0 * 2 ** 29,
494 when Registers.PFB_CTL_1 => 1 * 2 ** 29,
495 when Registers.PFC_CTL_1 => 2 * 2 ** 29,
496 when others => 0) else 0);
497
498 Width, Height : Pos32;
Nico Huberfdb0df12018-02-07 14:30:34 +0100499 X, Y : Int32;
Nico Huber4916e342016-11-04 14:37:53 +0100500 begin
501 -- Writes to WIN_SZ arm the PF registers.
502
503 Scale_Keep_Aspect
504 (Width => Width,
505 Height => Height,
506 Max_Width => Pos32 (Mode.H_Visible),
507 Max_Height => Pos32 (Mode.V_Visible),
508 Framebuffer => Framebuffer);
509
Nico Huberfdb0df12018-02-07 14:30:34 +0100510 -- Do not scale to odd width (at least Haswell has trouble with this).
511 if Width < Pos32 (Mode.H_Visible) and Width mod 2 = 1 then
512 Width := Width + 1;
513 end if;
514
515 X := (Int32 (Mode.H_Visible) - Width) / 2;
516 Y := (Int32 (Mode.V_Visible) - Height) / 2;
517
518 -- Hardware is picky about minimal horizontal gaps.
519 if Pos32 (Mode.H_Visible) - Width <= 3 then
520 Width := Pos32(Mode.H_Visible);
521 X := 0;
522 end if;
523
Nico Huber4916e342016-11-04 14:37:53 +0100524 Registers.Write
525 (Register => Controller.PF_CTRL,
526 Value => PF_CTRL_ENABLE or PF_Ctrl_Pipe_Sel or PF_CTRL_FILTER_MED);
527 Registers.Write
528 (Register => Controller.PF_WIN_POS,
Nico Huberfdb0df12018-02-07 14:30:34 +0100529 Value => Shift_Left (Word32 (X), 16) or Word32 (Y));
Nico Huber4916e342016-11-04 14:37:53 +0100530 Registers.Write
531 (Register => Controller.PF_WIN_SZ,
532 Value => Shift_Left (Word32 (Width), 16) or Word32 (Height));
533 end Setup_Ironlake_Panel_Fitter;
534
Arthur Heymansd5198442018-03-28 17:05:12 +0200535 -- TODO the panel fitter can only be set for one pipe
536 -- If this causes problems:
537 -- Check in Enable_Output if panel fitter has already been enabled
538 -- Pass this information to Validate_Config
539 procedure Setup_Gmch_Panel_Fitter
Nico Huber958c5642018-06-02 16:59:31 +0200540 (Controller : in Controller_Type;
541 Mode : in HW.GFX.Mode_Type;
542 Framebuffer : in HW.GFX.Framebuffer_Type)
Arthur Heymansd5198442018-03-28 17:05:12 +0200543 is
544 PF_Ctrl_Pipe_Sel : constant Word32 :=
545 (case Controller.Pipe is
546 when Primary => GMCH_PFIT_CONTROL_SELECT_PIPE_A,
547 when Secondary => GMCH_PFIT_CONTROL_SELECT_PIPE_B,
548 when others => 0);
Nico Huber958c5642018-06-02 16:59:31 +0200549
550 PF_Ctrl_Scaling : constant Word32 :=
551 GMCH_PFIT_CONTROL_SCALING (Scaling_Type (Framebuffer, Mode));
552
Arthur Heymansd5198442018-03-28 17:05:12 +0200553 In_Use : Boolean;
554 begin
555 Registers.Is_Set_Mask
556 (Register => Registers.GMCH_PFIT_CONTROL,
557 Mask => PF_CTRL_ENABLE,
558 Result => In_Use);
559
560 if not In_Use then
561 Registers.Write
562 (Register => Registers.GMCH_PFIT_CONTROL,
Nico Huber958c5642018-06-02 16:59:31 +0200563 Value => PF_CTRL_ENABLE or PF_Ctrl_Pipe_Sel or PF_Ctrl_Scaling);
Arthur Heymansd5198442018-03-28 17:05:12 +0200564 else
565 Debug.Put_Line ("GMCH Pannel fitter already in use, skipping...");
566 end if;
567 end Setup_Gmch_Panel_Fitter;
568
Nico Huberb4b72792018-01-02 13:45:41 +0100569 procedure Panel_Fitter_Off (Controller : Controller_Type)
570 is
571 use type HW.GFX.GMA.Registers.Registers_Invalid_Index;
Arthur Heymansd5198442018-03-28 17:05:12 +0200572 Used_For_Secondary : Boolean;
Nico Huberb4b72792018-01-02 13:45:41 +0100573 begin
574 -- Writes to WIN_SZ arm the PS/PF registers.
575 if Config.Has_Plane_Control then
576 Registers.Unset_Mask (Controller.PS_CTRL_1, PS_CTRL_ENABLE_SCALER);
577 Registers.Write (Controller.PS_WIN_SZ_1, 16#0000_0000#);
578 if Controller.PS_CTRL_2 /= Registers.Invalid_Register and
579 Controller.PS_WIN_SZ_2 /= Registers.Invalid_Register
580 then
581 Registers.Unset_Mask (Controller.PS_CTRL_2, PS_CTRL_ENABLE_SCALER);
582 Registers.Write (Controller.PS_WIN_SZ_2, 16#0000_0000#);
583 end if;
Arthur Heymansd5198442018-03-28 17:05:12 +0200584 elsif Config.Has_GMCH_PFIT_CONTROL then
585 Registers.Is_Set_Mask
586 (Register => Registers.GMCH_PFIT_CONTROL,
587 Mask => GMCH_PFIT_CONTROL_SELECT_PIPE_B,
588 Result => Used_For_Secondary);
589 if (Controller.Pipe = Primary and not Used_For_Secondary) or
590 (Controller.Pipe = Secondary and Used_For_Secondary)
591 then
592 Registers.Unset_Mask
593 (Register => Registers.GMCH_PFIT_CONTROL,
594 Mask => PF_CTRL_ENABLE);
595 end if;
Nico Huberb4b72792018-01-02 13:45:41 +0100596 else
597 Registers.Unset_Mask (Controller.PF_CTRL, PF_CTRL_ENABLE);
598 Registers.Write (Controller.PF_WIN_SZ, 16#0000_0000#);
599 end if;
600 end Panel_Fitter_Off;
601
Nico Huber4916e342016-11-04 14:37:53 +0100602 procedure Setup_Scaling
603 (Controller : in Controller_Type;
604 Mode : in HW.GFX.Mode_Type;
605 Framebuffer : in HW.GFX.Framebuffer_Type)
606 with
607 Pre =>
Nico Huber9b479412017-08-27 11:55:56 +0200608 Rotated_Width (Framebuffer) <= Mode.H_Visible and
609 Rotated_Height (Framebuffer) <= Mode.V_Visible
Nico Huber4916e342016-11-04 14:37:53 +0100610 is
611 begin
Nico Huber3d06de82018-05-29 01:35:04 +0200612 if Requires_Scaling (Framebuffer, Mode) then
Nico Huber4916e342016-11-04 14:37:53 +0100613 if Config.Has_Plane_Control then
614 Setup_Skylake_Pipe_Scaler (Controller, Mode, Framebuffer);
Arthur Heymansd5198442018-03-28 17:05:12 +0200615 elsif Config.Has_GMCH_PFIT_CONTROL then
Nico Huber958c5642018-06-02 16:59:31 +0200616 Setup_Gmch_Panel_Fitter (Controller, Mode, Framebuffer);
Nico Huber4916e342016-11-04 14:37:53 +0100617 else
618 Setup_Ironlake_Panel_Fitter (Controller, Mode, Framebuffer);
619 end if;
Nico Huberb4b72792018-01-02 13:45:41 +0100620 else
621 Panel_Fitter_Off (Controller);
Nico Huber4916e342016-11-04 14:37:53 +0100622 end if;
623 end Setup_Scaling;
624
625 ----------------------------------------------------------------------------
626
Nico Huberf7f537e2018-01-02 14:15:43 +0100627 procedure Setup_FB
628 (Pipe : Pipe_Index;
629 Mode : Mode_Type;
630 Framebuffer : Framebuffer_Type)
631 is
632 -- Enable dithering if framebuffer BPC differs from port BPC,
633 -- as smooth gradients look really bad without.
634 Dither : constant Boolean := Framebuffer.BPC /= Mode.BPC;
635 begin
636 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
637
Nico Huber4dc4c612018-01-10 15:55:09 +0100638 -- Disable the cursor first.
639 Update_Cursor (Pipe, Framebuffer, Default_Cursor);
640
Nico Huberf7f537e2018-01-02 14:15:43 +0100641 Setup_Display (Controllers (Pipe), Framebuffer, Mode.BPC, Dither);
642 Setup_Scaling (Controllers (Pipe), Mode, Framebuffer);
643 end Setup_FB;
644
Nico Huber83693c82016-10-08 22:17:55 +0200645 procedure On
Nico Huberf3e23662016-12-05 21:33:03 +0100646 (Pipe : Pipe_Index;
Nico Huber83693c82016-10-08 22:17:55 +0200647 Port_Cfg : Port_Config;
Nico Huber4dc4c612018-01-10 15:55:09 +0100648 Framebuffer : Framebuffer_Type;
649 Cursor : Cursor_Type)
Nico Huber83693c82016-10-08 22:17:55 +0200650 is
651 begin
652 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
653
Nico Huber7ad2d652016-12-07 15:19:32 +0100654 Transcoder.Setup (Pipe, Port_Cfg);
Nico Huber83693c82016-10-08 22:17:55 +0200655
Nico Huberf7f537e2018-01-02 14:15:43 +0100656 Setup_FB (Pipe, Port_Cfg.Mode, Framebuffer);
Nico Huber4dc4c612018-01-10 15:55:09 +0100657 Update_Cursor (Pipe, Framebuffer, Cursor);
Nico Huber83693c82016-10-08 22:17:55 +0200658
Nico Huberabb16d92018-05-29 01:44:26 +0200659 Transcoder.On
660 (Pipe => Pipe,
661 Port_Cfg => Port_Cfg,
662 Dither => Framebuffer.BPC /= Port_Cfg.Mode.BPC,
663 Scale => Requires_Scaling (Framebuffer, Port_Cfg.Mode));
Nico Huber83693c82016-10-08 22:17:55 +0200664 end On;
665
666 ----------------------------------------------------------------------------
667
668 procedure Planes_Off (Controller : Controller_Type) is
669 begin
Nico Huber4dc4c612018-01-10 15:55:09 +0100670 Registers.Write (Controller.CUR_CTL, 16#0000_0000#);
671 if Config.Has_Cursor_FBC_Control then
672 Registers.Write (Controller.CUR_FBC_CTL, 16#0000_0000#);
673 end if;
Nico Huber7ad2d652016-12-07 15:19:32 +0100674 Registers.Unset_Mask (Controller.SPCNTR, DSPCNTR_ENABLE);
Nico Huber83693c82016-10-08 22:17:55 +0200675 if Config.Has_Plane_Control then
676 Clear_Watermarks (Controller);
677 Registers.Unset_Mask (Controller.PLANE_CTL, PLANE_CTL_PLANE_ENABLE);
678 Registers.Write (Controller.PLANE_SURF, 16#0000_0000#);
679 else
680 Registers.Unset_Mask (Controller.DSPCNTR, DSPCNTR_ENABLE);
681 end if;
682 end Planes_Off;
683
Nico Huber7ad2d652016-12-07 15:19:32 +0100684 procedure Off (Pipe : Pipe_Index)
Nico Huberf3e23662016-12-05 21:33:03 +0100685 is
Nico Huber83693c82016-10-08 22:17:55 +0200686 begin
687 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
688
Nico Huberf3e23662016-12-05 21:33:03 +0100689 Planes_Off (Controllers (Pipe));
Nico Huber7ad2d652016-12-07 15:19:32 +0100690 Transcoder.Off (Pipe);
Nico Huberf3e23662016-12-05 21:33:03 +0100691 Panel_Fitter_Off (Controllers (Pipe));
Nico Huber7ad2d652016-12-07 15:19:32 +0100692 Transcoder.Clk_Off (Pipe);
Nico Huber83693c82016-10-08 22:17:55 +0200693 end Off;
694
Nico Huber33912aa2016-12-06 20:36:23 +0100695 procedure Legacy_VGA_Off
696 is
697 use type HW.Word8;
698 Reg8 : Word8;
699 begin
700 Port_IO.OutB (VGA_SR_INDEX, VGA_SR01);
701 Port_IO.InB (Reg8, VGA_SR_DATA);
702 Port_IO.OutB (VGA_SR_DATA, Reg8 or VGA_SR01_SCREEN_OFF);
703 Time.U_Delay (100); -- PRM says 100us, Linux does 300
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200704 Registers.Set_Mask (VGACNTRL_REG, VGA_CONTROL_VGA_DISPLAY_DISABLE);
Nico Huber33912aa2016-12-06 20:36:23 +0100705 end Legacy_VGA_Off;
706
Nico Huber83693c82016-10-08 22:17:55 +0200707 procedure All_Off
708 is
Nico Huber83693c82016-10-08 22:17:55 +0200709 begin
710 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
711
Nico Huber33912aa2016-12-06 20:36:23 +0100712 Legacy_VGA_Off;
713
Nico Huberf3e23662016-12-05 21:33:03 +0100714 for Pipe in Pipe_Index loop
715 Planes_Off (Controllers (Pipe));
Nico Huber7ad2d652016-12-07 15:19:32 +0100716 Transcoder.Off (Pipe);
Nico Huberf3e23662016-12-05 21:33:03 +0100717 Panel_Fitter_Off (Controllers (Pipe));
Nico Huber7ad2d652016-12-07 15:19:32 +0100718 Transcoder.Clk_Off (Pipe);
Nico Huber83693c82016-10-08 22:17:55 +0200719 end loop;
Nico Huber83693c82016-10-08 22:17:55 +0200720 end All_Off;
721
Nico Huber83693c82016-10-08 22:17:55 +0200722end HW.GFX.GMA.Pipe_Setup;