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Nico Huber83693c82016-10-08 22:17:55 +02001--
Nico Huber3be61d42017-01-09 13:58:18 +01002-- Copyright (C) 2014-2017 secunet Security Networks AG
Nico Huber83693c82016-10-08 22:17:55 +02003--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +02006-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +02008--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
Nico Huber83693c82016-10-08 22:17:55 +020015with HW.GFX.GMA.Config;
Nico Huber8c45bcf2016-11-20 17:30:57 +010016with HW.GFX.GMA.Config_Helpers;
Nico Huber83693c82016-10-08 22:17:55 +020017with HW.GFX.GMA.Registers;
18with HW.GFX.GMA.Power_And_Clocks;
19with HW.GFX.GMA.Panel;
20with HW.GFX.GMA.PLLs;
21with HW.GFX.GMA.Port_Detect;
22with HW.GFX.GMA.Connectors;
23with HW.GFX.GMA.Connector_Info;
24with HW.GFX.GMA.Pipe_Setup;
25
26with System;
27
28with HW.Debug;
29with GNAT.Source_Info;
30
Nico Huber83693c82016-10-08 22:17:55 +020031use type HW.Int32;
32
33package body HW.GFX.GMA
34 with Refined_State =>
35 (State =>
36 (Registers.Address_State,
37 PLLs.State, Panel.Panel_State,
Nico Huber1a712d32017-01-09 15:11:04 +010038 Cur_Configs, Allocated_PLLs,
Nico Huber83693c82016-10-08 22:17:55 +020039 HPD_Delay, Wait_For_HPD),
40 Init_State => Initialized,
41 Config_State => Config.Valid_Port_GPU,
42 Device_State =>
43 (Registers.Register_State, Registers.GTT_State))
44is
45
46 subtype Port_Name is String (1 .. 8);
47 type Port_Name_Array is array (Port_Type) of Port_Name;
48 Port_Names : constant Port_Name_Array :=
49 (Disabled => "Disabled",
50 Internal => "Internal",
51 DP1 => "DP1 ",
52 DP2 => "DP2 ",
53 DP3 => "DP3 ",
Nico Huber0d454cd2016-11-21 13:33:43 +010054 HDMI1 => "HDMI1 ",
55 HDMI2 => "HDMI2 ",
56 HDMI3 => "HDMI3 ",
Nico Huber83693c82016-10-08 22:17:55 +020057 Analog => "Analog ");
58
59 package Display_Controller renames Pipe_Setup;
60
Nico Huber99f10f32016-11-20 00:34:05 +010061 type PLLs_Type is array (Pipe_Index) of PLLs.T;
Nico Huber83693c82016-10-08 22:17:55 +020062
Nico Huber83693c82016-10-08 22:17:55 +020063 type HPD_Type is array (Port_Type) of Boolean;
Nico Huber3be61d42017-01-09 13:58:18 +010064 type HPD_Delay_Type is array (Active_Port_Type) of Time.T;
Nico Huber83693c82016-10-08 22:17:55 +020065
Nico Huber83693c82016-10-08 22:17:55 +020066 Allocated_PLLs : PLLs_Type;
Nico Huber83693c82016-10-08 22:17:55 +020067 HPD_Delay : HPD_Delay_Type;
68 Wait_For_HPD : HPD_Type;
69 Initialized : Boolean := False;
70
Nico Huber83693c82016-10-08 22:17:55 +020071 ----------------------------------------------------------------------------
72
Nico Huberf54d0962016-10-20 14:17:18 +020073 PCH_RAWCLK_FREQ_MASK : constant := 16#3ff# * 2 ** 0;
74
75 function PCH_RAWCLK_FREQ (Freq : Frequency_Type) return Word32
76 is
77 begin
78 return Word32 (Freq / 1_000_000);
79 end PCH_RAWCLK_FREQ;
80
81 ----------------------------------------------------------------------------
82
Nico Huber43370ba2017-01-09 15:26:19 +010083 procedure Enable_Output
84 (Pipe : in Pipe_Index;
85 Pipe_Cfg : in Pipe_Config;
86 Success : out Boolean)
87 is
88 Port_Cfg : Port_Config;
89 begin
Nico Huber3be61d42017-01-09 13:58:18 +010090 pragma Debug (Debug.New_Line);
91 pragma Debug (Debug.Put_Line
92 ("Trying to enable port " & Port_Names (Pipe_Cfg.Port)));
93
Nico Huber43370ba2017-01-09 15:26:19 +010094 Config_Helpers.Fill_Port_Config
95 (Port_Cfg, Pipe, Pipe_Cfg.Port, Pipe_Cfg.Mode, Success);
96
97 if Success then
98 Success := Config_Helpers.Validate_Config
99 (Pipe_Cfg.Framebuffer, Port_Cfg, Pipe);
100 end if;
101
Nico Huber43370ba2017-01-09 15:26:19 +0100102 if Success then
Nico Huber43370ba2017-01-09 15:26:19 +0100103 Connector_Info.Preferred_Link_Setting (Port_Cfg, Success);
104 end if;
105
106 -- loop over all possible DP-lane configurations
107 -- (non-DP ports use a single fake configuration)
108 while Success loop
109 pragma Loop_Invariant
110 (Pipe_Cfg.Port in Active_Port_Type and
111 Port_Cfg.Mode = Port_Cfg.Mode'Loop_Entry);
112
113 PLLs.Alloc
114 (Port_Cfg => Port_Cfg,
115 PLL => Allocated_PLLs (Pipe),
116 Success => Success);
117
118 if Success then
119 -- try each DP-lane configuration twice
120 for Try in 1 .. 2 loop
121 pragma Loop_Invariant
122 (Pipe_Cfg.Port in Active_Port_Type);
123
124 Connectors.Pre_On
125 (Pipe => Pipe,
126 Port_Cfg => Port_Cfg,
127 PLL_Hint => PLLs.Register_Value (Allocated_PLLs (Pipe)),
128 Success => Success);
129
130 if Success then
131 Display_Controller.On
132 (Pipe => Pipe,
133 Port_Cfg => Port_Cfg,
134 Framebuffer => Pipe_Cfg.Framebuffer);
135
136 Connectors.Post_On
137 (Port_Cfg => Port_Cfg,
138 PLL_Hint => PLLs.Register_Value (Allocated_PLLs (Pipe)),
139 Success => Success);
140
141 if not Success then
142 Display_Controller.Off (Pipe);
143 Connectors.Post_Off (Port_Cfg);
144 end if;
145 end if;
146
147 exit when Success;
148 end loop;
149 exit when Success; -- connection established => stop loop
150
151 -- connection failed
152 PLLs.Free (Allocated_PLLs (Pipe));
153 end if;
154
155 Connector_Info.Next_Link_Setting (Port_Cfg, Success);
156 end loop;
157
158 if Success then
159 pragma Debug (Debug.Put_Line
160 ("Enabled port " & Port_Names (Pipe_Cfg.Port)));
161 else
162 Wait_For_HPD (Pipe_Cfg.Port) := True;
163 if Pipe_Cfg.Port = Internal then
164 Panel.Off;
165 end if;
166 end if;
167 end Enable_Output;
168
Nico Huber3be61d42017-01-09 13:58:18 +0100169 procedure Disable_Output (Pipe : Pipe_Index; Pipe_Cfg : Pipe_Config)
170 is
171 Port_Cfg : Port_Config;
172 Success : Boolean;
173 begin
174 Config_Helpers.Fill_Port_Config
175 (Port_Cfg, Pipe, Pipe_Cfg.Port, Pipe_Cfg.Mode, Success);
176 if Success then
177 pragma Debug (Debug.New_Line);
178 pragma Debug (Debug.Put_Line
179 ("Disabling port " & Port_Names (Pipe_Cfg.Port)));
180 pragma Debug (Debug.New_Line);
181
182 Connectors.Pre_Off (Port_Cfg);
183 Display_Controller.Off (Pipe);
184 Connectors.Post_Off (Port_Cfg);
185
186 PLLs.Free (Allocated_PLLs (Pipe));
187 end if;
188 end Disable_Output;
189
Nico Huber99f10f32016-11-20 00:34:05 +0100190 procedure Update_Outputs (Configs : Pipe_Configs)
Nico Huber83693c82016-10-08 22:17:55 +0200191 is
192 Did_Power_Up : Boolean := False;
193
Nico Huber43370ba2017-01-09 15:26:19 +0100194 HPD, Success : Boolean;
Nico Huber99f10f32016-11-20 00:34:05 +0100195 Old_Config, New_Config : Pipe_Config;
196 Old_Configs : Pipe_Configs;
Nico Huber3be61d42017-01-09 13:58:18 +0100197
198 procedure Check_HPD (Port : in Active_Port_Type; Detected : out Boolean)
199 is
200 HPD_Delay_Over : constant Boolean := Time.Timed_Out (HPD_Delay (Port));
201 begin
202 if HPD_Delay_Over then
203 Port_Detect.Hotplug_Detect (Port, Detected);
204 HPD_Delay (Port) := Time.MS_From_Now (333);
205 else
206 Detected := False;
207 end if;
208 end Check_HPD;
Nico Huber83693c82016-10-08 22:17:55 +0200209 begin
210 Old_Configs := Cur_Configs;
211
Nico Huber99f10f32016-11-20 00:34:05 +0100212 for I in Pipe_Index loop
Nico Huber83693c82016-10-08 22:17:55 +0200213 HPD := False;
214
215 Old_Config := Cur_Configs (I);
216 New_Config := Configs (I);
217
Nico Huber3be61d42017-01-09 13:58:18 +0100218 if Old_Config.Port /= Disabled then
219 Check_HPD (Old_Config.Port, HPD);
Nico Huber83693c82016-10-08 22:17:55 +0200220 end if;
221
Nico Huber3be61d42017-01-09 13:58:18 +0100222 -- hotplug event or configuration changed?
223 if HPD or
Nico Huber83693c82016-10-08 22:17:55 +0200224 Old_Config.Port /= New_Config.Port or
225 Old_Config.Mode /= New_Config.Mode
226 then
Nico Huber3be61d42017-01-09 13:58:18 +0100227 -- disable old configuration if any
Nico Huber83693c82016-10-08 22:17:55 +0200228 if Old_Config.Port /= Disabled then
Nico Huber3be61d42017-01-09 13:58:18 +0100229 Disable_Output (I, Old_Config);
Nico Huber83693c82016-10-08 22:17:55 +0200230 Cur_Configs (I).Port := Disabled;
231 end if;
232
Nico Huber3be61d42017-01-09 13:58:18 +0100233 -- enable new configuration if any
Nico Huber83693c82016-10-08 22:17:55 +0200234 if New_Config.Port /= Disabled then
Nico Huber3be61d42017-01-09 13:58:18 +0100235 if Wait_For_HPD (New_Config.Port) then
236 Check_HPD (New_Config.Port, Success);
237 Wait_For_HPD (New_Config.Port) := not Success;
238 else
239 Success := True;
Nico Huber8c45bcf2016-11-20 17:30:57 +0100240 end if;
Nico Huberc7a4fee2016-11-03 18:18:03 +0100241
Nico Huber3be61d42017-01-09 13:58:18 +0100242 if Success then
243 if not Did_Power_Up then
244 Power_And_Clocks.Power_Up (Old_Configs, Configs);
245 Did_Power_Up := True;
246 end if;
247 Enable_Output (I, New_Config, Success);
248 end if;
Nico Huber83693c82016-10-08 22:17:55 +0200249
250 if Success then
Nico Huber83693c82016-10-08 22:17:55 +0200251 Cur_Configs (I) := New_Config;
Nico Huber83693c82016-10-08 22:17:55 +0200252 end if;
253 else
254 Cur_Configs (I) := New_Config;
255 end if;
Nico Huber3be61d42017-01-09 13:58:18 +0100256
257 -- update framebuffer offset only
Nico Huber83693c82016-10-08 22:17:55 +0200258 elsif Old_Config.Framebuffer /= New_Config.Framebuffer and
259 Old_Config.Port /= Disabled
260 then
Nico Huberf3e23662016-12-05 21:33:03 +0100261 Display_Controller.Update_Offset (I, New_Config.Framebuffer);
Nico Huber83693c82016-10-08 22:17:55 +0200262 Cur_Configs (I) := New_Config;
263 end if;
264 end loop;
265
266 if Did_Power_Up then
267 Power_And_Clocks.Power_Down (Old_Configs, Configs, Cur_Configs);
268 end if;
269
270 end Update_Outputs;
271
272 ----------------------------------------------------------------------------
273
274 procedure Initialize
275 (MMIO_Base : in Word64 := 0;
276 Write_Delay : in Word64 := 0;
Nico Huber793a8d42016-11-21 18:57:03 +0100277 Clean_State : in Boolean := False;
Nico Huber83693c82016-10-08 22:17:55 +0200278 Success : out Boolean)
279 with
280 Refined_Global =>
281 (In_Out =>
282 (Config.Valid_Port_GPU,
283 Registers.Register_State, Port_IO.State),
284 Input =>
285 (Time.State),
286 Output =>
287 (Registers.Address_State,
288 PLLs.State, Panel.Panel_State,
Nico Huber1a712d32017-01-09 15:11:04 +0100289 Cur_Configs, Allocated_PLLs,
Nico Huber83693c82016-10-08 22:17:55 +0200290 HPD_Delay, Wait_For_HPD, Initialized))
291 is
292 use type HW.Word64;
293
294 Now : constant Time.T := Time.Now;
295
296 procedure Check_Platform (Success : out Boolean)
297 is
298 Audio_VID_DID : Word32;
299 begin
300 case Config.CPU is
301 when Haswell .. Skylake =>
302 Registers.Read (Registers.AUD_VID_DID, Audio_VID_DID);
303 when Ironlake .. Ivybridge =>
304 Registers.Read (Registers.PCH_AUD_VID_DID, Audio_VID_DID);
305 end case;
306 Success :=
307 (case Config.CPU is
308 when Skylake => Audio_VID_DID = 16#8086_2809#,
309 when Broadwell => Audio_VID_DID = 16#8086_2808#,
310 when Haswell => Audio_VID_DID = 16#8086_2807#,
311 when Ivybridge |
312 Sandybridge => Audio_VID_DID = 16#8086_2806# or
313 Audio_VID_DID = 16#8086_2805#,
Nico Hubereeb5a392016-10-09 19:28:30 +0200314 when Ironlake => Audio_VID_DID = 16#0000_0000#);
Nico Huber83693c82016-10-08 22:17:55 +0200315 end Check_Platform;
316 begin
317 pragma Warnings (GNATprove, Off, "unused variable ""Write_Delay""",
318 Reason => "Write_Delay is used for debugging only");
319
320 pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
321
322 pragma Debug (Debug.Set_Register_Write_Delay (Write_Delay));
323
324 Wait_For_HPD := HPD_Type'(others => False);
325 HPD_Delay := HPD_Delay_Type'(others => Now);
Nico Huber83693c82016-10-08 22:17:55 +0200326 Allocated_PLLs := (others => PLLs.Invalid);
Nico Huber99f10f32016-11-20 00:34:05 +0100327 Cur_Configs := Pipe_Configs'
328 (others => Pipe_Config'
Nico Huber83693c82016-10-08 22:17:55 +0200329 (Port => Disabled,
330 Framebuffer => HW.GFX.Default_FB,
331 Mode => HW.GFX.Invalid_Mode));
332 Registers.Set_Register_Base
333 (if MMIO_Base /= 0 then
334 MMIO_Base
335 else
336 Config.Default_MMIO_Base);
337 PLLs.Initialize;
338
339 Check_Platform (Success);
340 if not Success then
341 pragma Debug (Debug.Put_Line ("ERROR: Incompatible CPU or PCH."));
342
343 Panel.Static_Init; -- for flow analysis
344
345 Initialized := False;
346 return;
347 end if;
348
349 Panel.Setup_PP_Sequencer;
350 Port_Detect.Initialize;
351
Nico Huber793a8d42016-11-21 18:57:03 +0100352 if Clean_State then
353 Power_And_Clocks.Pre_All_Off;
354 Connectors.Pre_All_Off;
355 Display_Controller.All_Off;
356 Connectors.Post_All_Off;
357 PLLs.All_Off;
358 Power_And_Clocks.Post_All_Off;
Nico Huber33912aa2016-12-06 20:36:23 +0100359 else
360 -- According to PRMs, VGA plane is the only thing
361 -- that's enabled by default after reset.
362 Display_Controller.Legacy_VGA_Off;
Nico Huber793a8d42016-11-21 18:57:03 +0100363 end if;
Nico Huber83693c82016-10-08 22:17:55 +0200364
365 -------------------- Now restart from a clean state ---------------------
366 Power_And_Clocks.Initialize;
367
Nico Huberf54d0962016-10-20 14:17:18 +0200368 Registers.Unset_And_Set_Mask
369 (Register => Registers.PCH_RAWCLK_FREQ,
370 Mask_Unset => PCH_RAWCLK_FREQ_MASK,
371 Mask_Set => PCH_RAWCLK_FREQ (Config.Default_RawClk_Freq));
372
Nico Huber83693c82016-10-08 22:17:55 +0200373 Initialized := True;
374
375 end Initialize;
376
377 function Is_Initialized return Boolean
378 with
379 Refined_Post => Is_Initialized'Result = Initialized
380 is
381 begin
382 return Initialized;
383 end Is_Initialized;
384
385 ----------------------------------------------------------------------------
386
387 procedure Write_GTT
388 (GTT_Page : GTT_Range;
389 Device_Address : GTT_Address_Type;
390 Valid : Boolean) is
391 begin
392 Registers.Write_GTT (GTT_Page, Device_Address, Valid);
393 end Write_GTT;
394
395 procedure Setup_Default_GTT (FB : Framebuffer_Type; Phys_FB : Word32)
396 is
397 FB_Size : constant Pos32 :=
398 FB.Stride * FB.Height * Pos32 (((FB.BPC * 4) / 8));
399 Phys_Addr : GTT_Address_Type := GTT_Address_Type (Phys_FB);
400 begin
401 for Idx in GTT_Range range 0 .. GTT_Range (((FB_Size + 4095) / 4096) - 1)
402 loop
403 Registers.Write_GTT
404 (GTT_Page => Idx,
405 Device_Address => Phys_Addr,
406 Valid => True);
407 Phys_Addr := Phys_Addr + 4096;
408 end loop;
409 end Setup_Default_GTT;
410
411 ----------------------------------------------------------------------------
412
Nico Huber99f10f32016-11-20 00:34:05 +0100413 procedure Dump_Configs (Configs : Pipe_Configs)
Nico Huber83693c82016-10-08 22:17:55 +0200414 is
415 subtype Pipe_Name is String (1 .. 9);
Nico Huber99f10f32016-11-20 00:34:05 +0100416 type Pipe_Name_Array is array (Pipe_Index) of Pipe_Name;
Nico Huber83693c82016-10-08 22:17:55 +0200417 Pipe_Names : constant Pipe_Name_Array :=
418 (Primary => "Primary ",
419 Secondary => "Secondary",
420 Tertiary => "Tertiary ");
421 begin
422 Debug.New_Line;
423 Debug.Put_Line ("CONFIG => ");
Nico Huber99f10f32016-11-20 00:34:05 +0100424 for Pipe in Pipe_Index loop
425 if Pipe = Pipe_Index'First then
Nico Huber83693c82016-10-08 22:17:55 +0200426 Debug.Put (" (");
427 else
428 Debug.Put (" ");
429 end if;
430 Debug.Put_Line (Pipe_Names (Pipe) & " =>");
431 Debug.Put_Line
432 (" (Port => " & Port_Names (Configs (Pipe).Port) & ",");
433 Debug.Put_Line (" Framebuffer =>");
434 Debug.Put (" (Width => ");
435 Debug.Put_Int32 (Configs (Pipe).Framebuffer.Width);
436 Debug.Put_Line (",");
437 Debug.Put (" Height => ");
438 Debug.Put_Int32 (Configs (Pipe).Framebuffer.Height);
439 Debug.Put_Line (",");
440 Debug.Put (" Stride => ");
441 Debug.Put_Int32 (Configs (Pipe).Framebuffer.Stride);
442 Debug.Put_Line (",");
443 Debug.Put (" Offset => ");
444 Debug.Put_Word32 (Configs (Pipe).Framebuffer.Offset);
445 Debug.Put_Line (",");
446 Debug.Put (" BPC => ");
447 Debug.Put_Int64 (Configs (Pipe).Framebuffer.BPC);
448 Debug.Put_Line ("),");
449 Debug.Put_Line (" Mode =>");
450 Debug.Put (" (Dotclock => ");
451 Debug.Put_Int64 (Configs (Pipe).Mode.Dotclock);
452 Debug.Put_Line (",");
453 Debug.Put (" H_Visible => ");
454 Debug.Put_Int16 (Configs (Pipe).Mode.H_Visible);
455 Debug.Put_Line (",");
456 Debug.Put (" H_Sync_Begin => ");
457 Debug.Put_Int16 (Configs (Pipe).Mode.H_Sync_Begin);
458 Debug.Put_Line (",");
459 Debug.Put (" H_Sync_End => ");
460 Debug.Put_Int16 (Configs (Pipe).Mode.H_Sync_End);
461 Debug.Put_Line (",");
462 Debug.Put (" H_Total => ");
463 Debug.Put_Int16 (Configs (Pipe).Mode.H_Total);
464 Debug.Put_Line (",");
465 Debug.Put (" V_Visible => ");
466 Debug.Put_Int16 (Configs (Pipe).Mode.V_Visible);
467 Debug.Put_Line (",");
468 Debug.Put (" V_Sync_Begin => ");
469 Debug.Put_Int16 (Configs (Pipe).Mode.V_Sync_Begin);
470 Debug.Put_Line (",");
471 Debug.Put (" V_Sync_End => ");
472 Debug.Put_Int16 (Configs (Pipe).Mode.V_Sync_End);
473 Debug.Put_Line (",");
474 Debug.Put (" V_Total => ");
475 Debug.Put_Int16 (Configs (Pipe).Mode.V_Total);
476 Debug.Put_Line (",");
477 Debug.Put_Line (" H_Sync_Active_High => " &
478 (if Configs (Pipe).Mode.H_Sync_Active_High
479 then "True,"
480 else "False,"));
481 Debug.Put_Line (" V_Sync_Active_High => " &
482 (if Configs (Pipe).Mode.V_Sync_Active_High
483 then "True,"
484 else "False,"));
485 Debug.Put (" BPC => ");
486 Debug.Put_Int64 (Configs (Pipe).Mode.BPC);
Nico Huber99f10f32016-11-20 00:34:05 +0100487 if Pipe /= Pipe_Index'Last then
Nico Huber83693c82016-10-08 22:17:55 +0200488 Debug.Put_Line (")),");
489 else
490 Debug.Put_Line (")));");
491 end if;
492 end loop;
493 end Dump_Configs;
494
495end HW.GFX.GMA;