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review.sourcearcade.org / libgfxinit / f54d0962018b0443973f84e525e0d112ce956800 / . / common / hw-gfx-gma-config.ads.template
blob: cba1396c95c5e28be4d442b8a7ae5ce0f41f417f [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
2-- Copyright (C) 2015-2016 secunet Security Networks AG
3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +0200[diff] [blame]6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15private package HW.GFX.GMA.Config
16with
17 Initializes => Valid_Port_GPU
18is
19
20 CPU : constant CPU_Type := <<CPU>>;
21
22 CPU_Var : constant CPU_Variant := <<CPU_VARIANT>>;
23
24 Internal_Display : constant Internal_Type := <<INTERNAL_PORT>>;
25
26 EDP_Low_Voltage_Swing : constant Boolean := False;
27
28 Default_MMIO_Base : constant := <<DEFAULT_MMIO_BASE>>;
29
30 LVDS_Dual_Threshold : constant := 95_000_000;
31
32 ----------------------------------------------------------------------------
33
34 Has_Internal_Display : constant Boolean := Internal_Display /= None;
35 Internal_Is_EDP : constant Boolean := Internal_Display = DP;
36
37 ----- CPU pipe: --------
38 Disable_Trickle_Feed : constant Boolean := not
39 (CPU in Haswell .. Broadwell);
40 Pipe_Enabled_Workaround : constant Boolean := CPU = Broadwell;
41 Has_EDP_Pipe : constant Boolean := CPU >= Haswell;
42 Has_Pipe_DDI_Func : constant Boolean := CPU >= Haswell;
43 Has_Trans_Clk_Sel : constant Boolean := CPU >= Haswell;
44 Has_Pipe_MSA_Misc : constant Boolean := CPU >= Haswell;
45 Has_Pipeconf_Misc : constant Boolean := CPU >= Broadwell;
46 Has_Pipeconf_BPC : constant Boolean := CPU /= Haswell;
47 Has_Plane_Control : constant Boolean := CPU >= Skylake;
48 Has_DSP_Linoff : constant Boolean := CPU <= Ivybridge;
49
50 ----- Panel power: -----
51 Has_PP_Write_Protection : constant Boolean := CPU <= Ivybridge;
52 Has_PP_Port_Select : constant Boolean := CPU <= Ivybridge;
53 Use_PP_VDD_Override : constant Boolean := CPU <= Ivybridge;
54
55 ----- PCH/FDI: ---------
56 Has_PCH_DAC : constant Boolean := CPU in Ironlake .. Ivybridge or
57 (CPU in Broadwell .. Haswell
58 and CPU_Var = Normal);
59
60 Has_PCH_Aux_Channels : constant Boolean := CPU in Ironlake .. Broadwell;
61
62 VGA_Has_Sync_Disable : constant Boolean := CPU <= Ivybridge;
63
64 Has_Trans_Timing_Ovrrde : constant Boolean := CPU >= Sandybridge;
65
66 Has_DPLL_SEL : constant Boolean := CPU in Ironlake .. Ivybridge;
67 Has_FDI_BPC : constant Boolean := CPU in Ironlake .. Ivybridge;
68 Has_FDI_Composite_Sel : constant Boolean := CPU = Ivybridge;
69 Has_Trans_DP_Ctl : constant Boolean := CPU in
70 Sandybridge .. Ivybridge;
71 Has_FDI_C : constant Boolean := CPU = Ivybridge;
72
73 Has_FDI_RX_Power_Down : constant Boolean := CPU in Haswell .. Broadwell;
74
75 ----- DDI: -------------
76 End_EDP_Training_Late : constant Boolean := CPU in Haswell .. Broadwell;
77 Has_Per_DDI_Clock_Sel : constant Boolean := CPU in Haswell .. Broadwell;
78 Has_HOTPLUG_CTL : constant Boolean := CPU in Haswell .. Broadwell;
79 Has_SHOTPLUG_CTL_A : constant Boolean := (CPU in Haswell .. Broadwell
80 and CPU_Var = ULT) or
81 CPU >= Skylake;
82
83 Has_DDI_D : constant Boolean := (CPU in Haswell .. Broadwell
84 and CPU_Var = Normal)
85 or CPU >= Skylake;
86
87 Has_Low_Voltage_Swing : constant Boolean := CPU >= Skylake;
88
89 Need_DP_Aux_Mutex : constant Boolean := False; -- Skylake & (PSR | GTC)
90
91 Ungate_GMBUS_Unit_Level : constant Boolean := CPU >= Skylake;
92
93 ----- Power: -----------
94 Has_IPS : constant Boolean := (CPU = Haswell and
95 CPU_Var = ULT) or
96 CPU = Broadwell;
97 Has_IPS_CTL_Mailbox : constant Boolean := CPU = Broadwell;
98
99 Has_Per_Pipe_SRD : constant Boolean := CPU >= Broadwell;
100
101 ----- GTT: -----
102 Fold_39Bit_GTT_PTE : constant Boolean := CPU <= Haswell;
103
104 ----------------------------------------------------------------------------
105
106 type Supported_Pipe_Array is array (Config_Index) of Boolean;
107 Supported_Pipe : constant Supported_Pipe_Array :=
108 (Primary => True,
109 Secondary => True,
110 Tertiary => CPU >= Ivybridge);
111
112 type Valid_Per_Port is array (Port_Type) of Boolean;
113 type Valid_Per_GPU is array (CPU_Type) of Valid_Per_Port;
114 Valid_Port_GPU : Valid_Per_GPU :=
115 (Ironlake => Valid_Per_Port'
116 (Disabled => False,
117 Internal => Config.Internal_Display = LVDS,
118 others => True),
119 Sandybridge => Valid_Per_Port'
120 (Disabled => False,
121 Internal => Config.Internal_Display = LVDS,
122 others => True),
123 Ivybridge => Valid_Per_Port'
124 (Disabled => False,
125 Internal => Config.Internal_Display /= None,
126 others => True),
127 Haswell => Valid_Per_Port'
128 (Disabled => False,
129 Internal => Config.Internal_Display = DP,
130 Digital3 => CPU_Var = Normal,
131 DP3 => CPU_Var = Normal,
132 Analog => CPU_Var = Normal,
133 others => True),
134 Broadwell => Valid_Per_Port'
135 (Disabled => False,
136 Internal => Config.Internal_Display = DP,
137 Digital3 => CPU_Var = Normal,
138 DP3 => CPU_Var = Normal,
139 Analog => CPU_Var = Normal,
140 others => True),
141 Skylake => Valid_Per_Port'
142 (Disabled => False,
143 Internal => Config.Internal_Display = DP,
144 Analog => False,
145 others => True))
146 with
147 Part_Of => GMA.Config_State;
148 Valid_Port : Valid_Per_Port renames Valid_Port_GPU (CPU);
149
150 ----------------------------------------------------------------------------
151
152 type FDI_Per_Port is array (GPU_Port) of Boolean;
153 type FDI_Per_GPU is array (CPU_Type) of FDI_Per_Port;
154 FDI_GPU : constant FDI_Per_GPU :=
155 (Ironlake => FDI_Per_Port'
156 (DIGI_A => False, -- directly connected eDP
157 DIGI_B => True,
158 DIGI_C => True,
159 DIGI_D => True,
160 others => False),
161 Sandybridge => FDI_Per_Port'
162 (DIGI_A => False, -- directly connected eDP
163 DIGI_B => True,
164 DIGI_C => True,
165 DIGI_D => True,
166 others => False),
167 Ivybridge => FDI_Per_Port'
168 (DIGI_A => False, -- directly connected eDP
169 DIGI_B => True,
170 DIGI_C => True,
171 DIGI_D => True,
172 others => False),
173 Haswell => FDI_Per_Port'
174 (DIGI_A => False,
175 DIGI_B => False,
176 DIGI_C => False,
177 DIGI_D => False,
178 DIGI_E => True, -- VGA option through FDI
179 others => False),
180 Broadwell => FDI_Per_Port'
181 (DIGI_A => False,
182 DIGI_B => False,
183 DIGI_C => False,
184 DIGI_D => False,
185 DIGI_E => CPU_Var = Normal, -- VGA option through FDI
186 others => False),
187 Skylake => FDI_Per_Port'
188 (others => False));
189 FDI_Port : FDI_Per_Port renames FDI_GPU (CPU);
190
191 type FDI_Lanes_Per_Port is array (GPU_Port) of DP_Lane_Count;
192 FDI_Lane_Count : constant FDI_Lanes_Per_Port :=
193 (DIGI_D => DP_Lane_Count_2,
194 others =>
195 (if CPU in Ironlake .. Ivybridge then
196 DP_Lane_Count_4
197 else
198 DP_Lane_Count_2));
199
200 FDI_Training : constant FDI_Training_Type :=
201 (case CPU is
202 when Ironlake => Simple_Training,
203 when Sandybridge => Full_Training,
204 when others => Auto_Training);
205
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame^]206 ----------------------------------------------------------------------------
207
208 Default_RawClk_Freq : constant Frequency_Type :=
209 (case CPU is
210 when Ironlake |
211 Sandybridge |
212 Ivybridge => 125_000_000,
213 when Haswell |
214 Broadwell => (if CPU_Var = Normal then
215 125_000_000
216 else
217 24_000_000),
218 when Skylake => 24_000_000);
219
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]220end HW.GFX.GMA.Config;