)]}'
{
  "commit": "3f37cce66ef8b36932db08a1fb5e6486647da308",
  "tree": "b14750a924f1384018f2b56854bb82a0803441a4",
  "parents": [
    "7e08e5d2803914af4e46280b558ec1307ead9031"
  ],
  "author": {
    "name": "Arthur Heymans",
    "email": "arthur@aheymans.xyz",
    "time": "Tue Mar 03 18:52:12 2026 +0100"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Sun Jun 28 09:24:08 2026 +0000"
  },
  "message": "gma g45: Add support for Intel GM965 (Crestline)\n\nAdd GM965 as a new CPU type under the G45 generation. GM965 shares\nthe GMCH display architecture with G45/GM45 (no PCH, same connector\nregisters) but differs in PLL limits, VCO/CDClk tables, and register\nfield encoding.\n\nKey differences from G45/GM45:\n - PLL limits: Uses i9xx limits (VCO 1.4-2.8 GHz) instead of g4x\n   limits. Add I9XX_LVDS_Limits; refactor Calculate_Clock_Parameters\n   to take Limits as a parameter, with a new Select_Limits function.\n - VCO: Uses Crestline (CL) VCO tables with different frequencies\n   and divisors than GM45\u0027s Cantiga (CTG) tables.\n - CDClk: GCFGC register decoding uses bits 12:8 minus 1 (3 possible\n   divisor selections), unlike GM45\u0027s single bit 12.\n - No native DisplayPort (SDVO B/C only).\n - No HD Audio (G4X_AUD_VID_DID reads as 0).\n - Has integrated LVDS transmitter (mobile platform).\n - PCI IDs: 0x2a02 (I965_GM), 0x2a12 (I965_GME).\n\nAll implementation details cross-referenced against the Linux kernel\ni915 driver (intel_dpll.c, intel_cdclk.c, intel_display_device.c).\n\nChange-Id: I0d5d698cc1c2aa84778f0fc6c2752cb5ce4f1cb2\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/499\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n",
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