commit fbb422015506b6c175ff35d084e5cf267dfc0096
author Nico Huber <nico.huber@secunet.com> Mon Nov 07 15:08:26 2016 +0100
committer Nico Huber <nico.h@gmx.de> Mon Dec 05 12:35:25 2016 +0100
tree 800db7e4028ed730b7c4c10d08e0252062fd5eae
parent 3675db58aa729bfb565b61389d3b2568360095af

gma: Implement Ivy Bridge VGA plane workaround

It's a documented requirement, even though it doesn't seem necessary.

Change-Id: Id4f579c1ca34633ee00c771b39e6ff45cdcfbf69
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17277
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

common/hw-gfx-gma-config.ads.template

diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template
index 7289dff..ccc5c1a 100644
--- a/common/hw-gfx-gma-config.ads.template
+++ b/common/hw-gfx-gma-config.ads.template
@@ -49,6 +49,7 @@
    Has_Plane_Control       : constant Boolean := CPU >= Skylake;
    Has_DSP_Linoff          : constant Boolean := CPU <= Ivybridge;
    Has_PF_Pipe_Select      : constant Boolean := CPU in Ivybridge .. Haswell;
+   VGA_Plane_Workaround    : constant Boolean := CPU = Ivybridge;
 
    ----- Panel power: -----
    Has_PP_Write_Protection : constant Boolean := CPU <= Ivybridge;

common/hw-gfx-gma-pipe_setup.adb

diff --git a/common/hw-gfx-gma-pipe_setup.adb b/common/hw-gfx-gma-pipe_setup.adb
index 1f13c86..4176ffe 100644
--- a/common/hw-gfx-gma-pipe_setup.adb
+++ b/common/hw-gfx-gma-pipe_setup.adb
@@ -25,6 +25,11 @@
 
 package body HW.GFX.GMA.Pipe_Setup is
 
+   ILK_DISPLAY_CHICKEN1_VGA_MASK       : constant := 7 * 2 ** 29;
+   ILK_DISPLAY_CHICKEN1_VGA_ENABLE     : constant := 5 * 2 ** 29;
+   ILK_DISPLAY_CHICKEN2_VGA_MASK       : constant := 1 * 2 ** 25;
+   ILK_DISPLAY_CHICKEN2_VGA_ENABLE     : constant := 0 * 2 ** 25;
+
    DSPCNTR_ENABLE               : constant :=  1 * 2 ** 31;
    DSPCNTR_GAMMA_CORRECTION     : constant :=  1 * 2 ** 30;
    DSPCNTR_DISABLE_TRICKLE_FEED : constant :=  1 * 2 ** 14;
@@ -416,6 +421,17 @@
       end if;
 
       if Framebuffer.Offset = VGA_PLANE_FRAMEBUFFER_OFFSET then
+         if Config.VGA_Plane_Workaround then
+            Registers.Unset_And_Set_Mask
+              (Register    => Registers.ILK_DISPLAY_CHICKEN1,
+               Mask_Unset  => ILK_DISPLAY_CHICKEN1_VGA_MASK,
+               Mask_Set    => ILK_DISPLAY_CHICKEN1_VGA_ENABLE);
+            Registers.Unset_And_Set_Mask
+              (Register    => Registers.ILK_DISPLAY_CHICKEN2,
+               Mask_Unset  => ILK_DISPLAY_CHICKEN2_VGA_MASK,
+               Mask_Set    => ILK_DISPLAY_CHICKEN2_VGA_ENABLE);
+         end if;
+
          Registers.Unset_And_Set_Mask
            (Register    => Registers.VGACNTRL,
             Mask_Unset  => VGA_CONTROL_VGA_DISPLAY_DISABLE or

common/hw-gfx-gma-registers.ads

diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads
index 1633bac..68763c8 100644
--- a/common/hw-gfx-gma-registers.ads
+++ b/common/hw-gfx-gma-registers.ads
@@ -67,7 +67,7 @@
       GAB_CTL_REG,
       VGACNTRL,
       FUSE_STATUS,
-      QUIRK_42004,
+      ILK_DISPLAY_CHICKEN2,
       DSPCLK_GATE_D,
       FBA_CFB_BASE,
       FBC_CTL,
@@ -965,7 +965,7 @@
       VCS_PP_DCLV_LOW       => 16#01_2228# / Register_Width,
       BCS_PP_DCLV_HIGH      => 16#02_2220# / Register_Width,
       BCS_PP_DCLV_LOW       => 16#02_2228# / Register_Width,
-      QUIRK_42004           => 16#04_2004# / Register_Width,
+      ILK_DISPLAY_CHICKEN2  => 16#04_2004# / Register_Width,
       UCGCTL1               => 16#00_9400# / Register_Width,
       UCGCTL2               => 16#00_9404# / Register_Width,
       MBCTL                 => 16#00_907c# / Register_Width,
@@ -1029,6 +1029,7 @@
    DP_AUX_DATA_A_3      : constant Registers_Index := DDI_AUX_DATA_A_3;
    DP_AUX_DATA_A_4      : constant Registers_Index := DDI_AUX_DATA_A_4;
    DP_AUX_DATA_A_5      : constant Registers_Index := DDI_AUX_DATA_A_5;
+   ILK_DISPLAY_CHICKEN1 : constant Registers_Index := FUSE_STATUS;
 
    ---------------------------------------------------------------------------