diff --git a/common/broxton/hw-gfx-gma-power_and_clocks.adb b/common/broxton/hw-gfx-gma-power_and_clocks.adb
index 12ab308..c0f3075 100644
--- a/common/broxton/hw-gfx-gma-power_and_clocks.adb
+++ b/common/broxton/hw-gfx-gma-power_and_clocks.adb
@@ -316,6 +316,8 @@
 
       Set_Mask (DBUF_CTL, DBUF_CTL_DBUF_POWER_REQUEST);
       Wait_Set_Mask (DBUF_CTL, DBUF_CTL_DBUF_POWER_STATE);
+
+      Config.Raw_Clock := Config.Default_RawClk_Freq;
    end Initialize;
 
 end HW.GFX.GMA.Power_And_Clocks;
diff --git a/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.adb b/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.adb
index 41d340a..c0d1e78 100644
--- a/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.adb
+++ b/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.adb
@@ -207,6 +207,7 @@
    begin
       -- HSW: disable power down well
       PDW_Off;
+      Config.Raw_Clock := Config.Default_RawClk_Freq;
    end Initialize;
 
    procedure Power_Set_To (Configs : Pipe_Configs) is
diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template
index 5d136b2..a8e89d3 100644
--- a/common/hw-gfx-gma-config.ads.template
+++ b/common/hw-gfx-gma-config.ads.template
@@ -14,7 +14,7 @@
 
 private package HW.GFX.GMA.Config
 with
-   Initializes => Valid_Port_GPU
+   Initializes => (Valid_Port_GPU, Raw_Clock)
 is
 
    CPU : constant CPU_Type := <<CPU>>;
@@ -246,6 +246,9 @@
          when Broxton      => Frequency_Type'First,   -- none needed
          when Skylake      => 24_000_000);
 
+    Raw_Clock : Frequency_Type := Default_RawClk_Freq
+    with Part_Of => GMA.Config_State;
+
    ----------------------------------------------------------------------------
 
    -- Maximum source width with enabled scaler. This only accounts
diff --git a/common/hw-gfx-gma-dp_aux_request.adb b/common/hw-gfx-gma-dp_aux_request.adb
index 22064ab..97083b2 100644
--- a/common/hw-gfx-gma-dp_aux_request.adb
+++ b/common/hw-gfx-gma-dp_aux_request.adb
@@ -19,6 +19,7 @@
 
 with HW.GFX.GMA.Config;
 with HW.GFX.GMA.Registers;
+with HW.GFX.GMA.Power_And_Clocks;
 
 use type HW.Word8;
 use type HW.GFX.GMA.Registers.Registers_Invalid_Index;
@@ -162,7 +163,7 @@
       Success           :    out Boolean)
    with
       Global => (In_Out => Registers.Register_State,
-                 Input  => Time.State),
+                 Input  => (Time.State, Config.Raw_Clock)),
       Depends =>
         ((Registers.Register_State,
           Response,
@@ -170,6 +171,7 @@
           Success)
              =>
                (Registers.Register_State,
+                Config.Raw_Clock,
                 Time.State,
                 Port,
                 Request,
@@ -232,7 +234,7 @@
            (if Port = DP_A then
                Word32 ((Config.Default_CDClk_Freq + 1_000_000) / 2_000_000)
             else
-               Word32 ((Config.Default_RawClk_Freq + 1_000_000) / 2_000_000))
+               Word32 ((Config.Raw_Clock + 1_000_000) / 2_000_000))
          else 0);
 
       Busy : Boolean;
diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb
index d8438ab..a4445ba 100644
--- a/common/hw-gfx-gma.adb
+++ b/common/hw-gfx-gma.adb
@@ -46,7 +46,7 @@
          HPD_Delay, Wait_For_HPD,
          Linear_FB_Base),
       Init_State => Initialized,
-      Config_State => Config.Valid_Port_GPU,
+      Config_State => (Config.Valid_Port_GPU, Config.Raw_Clock),
       Device_State =>
         (Dev.PCI_State, Registers.Register_State, Registers.GTT_State))
 is
@@ -307,7 +307,8 @@
       Refined_Global =>
         (In_Out =>
            (Config.Valid_Port_GPU, Dev.PCI_State,
-            Registers.Register_State, Port_IO.State),
+            Registers.Register_State, Port_IO.State,
+            Config.Raw_Clock),
          Input =>
            (Time.State),
          Output =>
diff --git a/common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.adb b/common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.adb
index bff4750..a7b1035 100644
--- a/common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.adb
+++ b/common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.adb
@@ -50,6 +50,8 @@
          Registers.Posting_Read (Registers.PCH_DREF_CONTROL);
          Time.U_Delay (20);   -- DMI latency
       end if;
+
+      Config.Raw_Clock := Config.Default_RawClk_Freq;
    end Initialize;
 
 end HW.GFX.GMA.Power_And_Clocks_Ironlake;
diff --git a/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb b/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb
index e79ea87..ea84992 100644
--- a/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb
+++ b/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb
@@ -315,6 +315,8 @@
            (Register    => Registers.DBUF_CTL,
             Mask        => DBUF_CTL_DBUF_POWER_STATE);
       end if;
+
+      Config.Raw_Clock := Config.Default_RawClk_Freq;
    end Initialize;
 
    procedure Power_Set_To (Configs : Pipe_Configs) is