gma hsw: Implement CDClk switching
For Haswell, we only read out the current CDClk setting and work with
that (CDClk is supposed to be set only once per boot, so we leave that
to the firmware). Broadwell supports actual frequency switching, with
the following limits:
o a fuse may restrict us to 450MHz,
o ULX supports at most 450MHz w/o additional cooling,
o ULT supports at most 540MHz w/o additional cooling,
o others support up to 675MHz.
We assume there is no `additional cooling`. With the CDClk now being
switchable, we have to update `DP_Aux_Request` to assume the current
CDClk frequency instead of the default.
Dot clocks, on these platforms, may run with full CDClk speed.
Change-Id: I8fb23a49b334f9f0045884c3af4087764397b941
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/35717
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/common/hw-gfx-gma-dp_aux_request.adb b/common/hw-gfx-gma-dp_aux_request.adb
index c057059..54500e2 100644
--- a/common/hw-gfx-gma-dp_aux_request.adb
+++ b/common/hw-gfx-gma-dp_aux_request.adb
@@ -232,7 +232,7 @@
DP_AUX_CTL_2x_Clock : constant Word32 :=
(if Config.Has_PCH_Aux_Channels then
(if Port = DP_A then
- Word32 ((Config.Default_CDClk_Freq + 1_000_000) / 2_000_000)
+ Word32 ((Config.CDClk + 1_000_000) / 2_000_000)
else
Word32 ((Config.Raw_Clock + 1_000_000) / 2_000_000))
elsif Config.Has_GMCH_RawClk then