gma config: Turn Alder Lake into its own generation
It's not physically compatible to Tiger Lake. Hence no binary has
to support both and we can compile them separately. Also, the new
generation actually starts with Alder Lake P, so we name it accor-
dingly.
Change-Id: I66f01609326204d9a93a2206c048bd59bfdbef6b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/503
Reviewed-by: Thomas Heijligen <src@posteo.de>
Tested-by: Ada SPARK <gnatbot@sourcearcade.org>
diff --git a/common/Makefile.inc b/common/Makefile.inc
index 175c152..236a323 100644
--- a/common/Makefile.inc
+++ b/common/Makefile.inc
@@ -64,7 +64,7 @@
CONFIG_GFX_GMA_ANALOG_I2C_PORT := $(call strip_quotes,$(CONFIG_GFX_GMA_ANALOG_I2C_PORT))
CONFIG_GFX_GMA_IGNORE_PRESENCE_STRAPS := $(if $(filter y,$(CONFIG_GFX_GMA_IGNORE_PRESENCE_STRAPS)),True,False)
-_GEN_TLA_SUBSTITUTIONS := i945 g45 ilk hsw skl tgl
+_GEN_TLA_SUBSTITUTIONS := i945 g45 ilk hsw skl tgl adl
_GEN_NONCONST := $(strip \
$(if $(filter I945,$(CONFIG_GFX_GMA_GENERATION)),i945, \
@@ -72,7 +72,8 @@
$(if $(filter Ironlake,$(CONFIG_GFX_GMA_GENERATION)),ilk, \
$(if $(filter Haswell,$(CONFIG_GFX_GMA_GENERATION)),hsw, \
$(if $(filter Skylake,$(CONFIG_GFX_GMA_GENERATION)),skl, \
- $(if $(filter Tigerlake,$(CONFIG_GFX_GMA_GENERATION)),tgl)))))))
+ $(if $(filter Tigerlake,$(CONFIG_GFX_GMA_GENERATION)),tgl, \
+ $(if $(filter AlderlakeP,$(CONFIG_GFX_GMA_GENERATION)),adl))))))))
# GNATprove (GPL 2017) doesn't realize when a boolean expression
# that depends both on static values and variables can be evalu-
# ated at compile time (e.g. `False and then Variable` is always
@@ -138,6 +139,6 @@
subdirs-y += haswell_shared broxton
else ifneq ($(filter Skylake,$(CONFIG_GFX_GMA_GENERATION)),)
subdirs-y += haswell_shared skylake
-else ifneq ($(filter Tigerlake,$(CONFIG_GFX_GMA_GENERATION)),)
+else ifneq ($(filter Tigerlake AlderlakeP,$(CONFIG_GFX_GMA_GENERATION)),)
subdirs-y += tigerlake
endif
diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template
index 43efe2f..987e315 100644
--- a/common/hw-gfx-gma-config.ads.template
+++ b/common/hw-gfx-gma-config.ads.template
@@ -20,29 +20,35 @@
CPU_First : constant CPU_Type :=
(case Gen is
- when I945 => I945G,
- when G45 => GM965,
- when Ironlake => Ironlake,
- when Haswell => Haswell,
- when Broxton => Broxton,
- when Skylake => Skylake,
- when Tigerlake => Tigerlake);
+ when I945 => I945G,
+ when G45 => GM965,
+ when Ironlake => Ironlake,
+ when Haswell => Haswell,
+ when Broxton => Broxton,
+ when Skylake => Skylake,
+ when Tigerlake => Tigerlake,
+ when AlderlakeP => AlderlakeP);
CPU_Last : constant CPU_Type :=
(case Gen is
- when I945 => Pineview_M,
- when G45 => GM45,
- when Ironlake => Ivybridge,
- when Haswell => Broadwell,
- when Broxton => Broxton,
- when Skylake => Kabylake,
- when Tigerlake => Alderlake);
+ when I945 => Pineview_M,
+ when G45 => GM45,
+ when Ironlake => Ivybridge,
+ when Haswell => Broadwell,
+ when Broxton => Broxton,
+ when Skylake => Kabylake,
+ when Tigerlake => Tigerlake,
+ when AlderlakeP => AlderlakeP);
+ CPU_Var_First : constant CPU_Variant :=
+ (case Gen is
+ when AlderlakeP => ULT,
+ when others => Normal);
CPU_Var_Last : constant CPU_Variant :=
(case Gen is
- when Haswell | Skylake => ULX,
- when Tigerlake => ULT,
- when others => Normal);
+ when Haswell | Skylake => ULX,
+ when Tigerlake | AlderlakeP => ULT,
+ when others => Normal);
subtype Gen_CPU_Type is CPU_Type range CPU_First .. CPU_Last;
- subtype Gen_CPU_Variant is CPU_Variant range Normal .. CPU_Var_Last;
+ subtype Gen_CPU_Variant is CPU_Variant range CPU_Var_First .. CPU_Var_Last;
CPU : constant Gen_CPU_Type := <<CPU>>;
@@ -50,22 +56,24 @@
PCH_First : constant PCH_Type :=
(case Gen is
- when I945 => No_PCH,
- when G45 => No_PCH,
- when Ironlake => Ibex_Peak,
- when Haswell => Lynx_Point,
- when Broxton => No_PCH,
- when Skylake => Sunrise_Point,
- when Tigerlake => Tiger_Point);
+ when I945 => No_PCH,
+ when G45 => No_PCH,
+ when Ironlake => Ibex_Peak,
+ when Haswell => Lynx_Point,
+ when Broxton => No_PCH,
+ when Skylake => Sunrise_Point,
+ when Tigerlake => Tiger_Point,
+ when AlderlakeP => Alder_Point);
PCH_Last : constant PCH_Type :=
(case Gen is
- when I945 => No_PCH,
- when G45 => No_PCH,
- when Ironlake => Cougar_Point,
- when Haswell => Lynx_Point,
- when Broxton => No_PCH,
- when Skylake => Cannon_Point,
- when Tigerlake => Alder_Point);
+ when I945 => No_PCH,
+ when G45 => No_PCH,
+ when Ironlake => Cougar_Point,
+ when Haswell => Lynx_Point,
+ when Broxton => No_PCH,
+ when Skylake => Cannon_Point,
+ when Tigerlake => Tiger_Point,
+ when AlderlakeP => Alder_Point);
subtype Gen_PCH_Type is PCH_Type range PCH_First .. PCH_Last;
PCH : constant Gen_PCH_Type := <<PCH>>;
@@ -153,6 +161,7 @@
Gen_Broxton : <genbool> := Gen = Broxton;
Gen_Skylake : <genbool> := Gen = Skylake;
Gen_Tigerlake : <genbool> := Gen = Tigerlake;
+ Gen_AlderlakeP : <genbool> := Gen = AlderlakeP;
Up_To_G45 : <genbool> := Gen <= G45;
Up_To_Ironlake : <genbool> := Gen <= Ironlake;
@@ -162,6 +171,7 @@
Broxton_On : <genbool> := Gen >= Broxton;
Skylake_On : <genbool> := Gen >= Skylake;
Tigerlake_On : <genbool> := Gen >= Tigerlake;
+ AlderlakeP_On : <genbool> := Gen >= AlderlakeP;
GMCH_I945GM : <i945bool> := Gen_I945 and then CPU = I945GM;
GMCH_GM965 : <g45bool> := Gen_G45 and then CPU = GM965;
@@ -177,8 +187,8 @@
CPU_Broadwell : <hswbool> := Gen_Haswell and then CPU = Broadwell;
CPU_Skylake : <sklbool> := Gen_Skylake and then CPU = Skylake;
CPU_Kabylake : <sklbool> := Gen_Skylake and then CPU = Kabylake;
- CPU_Tigerlake : <tglbool> := Gen_Tigerlake and then CPU = Tigerlake;
- CPU_Alderlake : <tglbool> := Gen_Tigerlake and then CPU = Alderlake;
+ CPU_Tigerlake : <genbool> := Gen_Tigerlake;
+ CPU_AlderlakeP : <genbool> := Gen_AlderlakeP;
Sandybridge_On : <ilkbool> :=
((Gen_Ironlake and then CPU >= Sandybridge) or Haswell_On);
@@ -186,8 +196,6 @@
((Gen_Ironlake and then CPU >= Ivybridge) or Haswell_On);
Broadwell_On : <hswbool> :=
((Gen_Haswell and then CPU >= Broadwell) or Broxton_On);
- Alderlake_On : <tglbool> :=
- (Gen_Tigerlake and then CPU >= Alderlake);
PCH_Cougar_Point : <genbool> := Gen_Ironlake and then PCH = Cougar_Point;
@@ -196,6 +204,12 @@
Cannon_Point_On : <genbool> := Skylake_On and then PCH >= Cannon_Point;
Tiger_Point_On : <genbool> := Tigerlake_On and then PCH >= Tiger_Point;
+ pragma Warnings (GNAT, Off, "condition can only be * if invalid values present");
+ Is_ULT : <hswskltglbool> := CPU_Var = ULT;
+ Is_ULX : <hswsklbool> := CPU_Var = ULX;
+ Is_LP : <hswskltglbool> := Is_ULT or Is_ULX;
+ pragma Warnings (GNAT, On, "condition can only be * if invalid values present");
+
----------------------------------------------------------------------------
Have_HDMI_Buf_Override : constant Boolean := DDI_HDMI_Buffer_Translation >= 0;
@@ -204,11 +218,6 @@
Have_DVI_I : constant Boolean := Analog_I2C_Port /= PCH_DAC;
Has_Presence_Straps : <genbool> := not Gen_Broxton and not Gen_I945;
- Is_ULT : <hswskltglbool> :=
- ((Gen_Haswell or Gen_Skylake or Gen_Tigerlake) and then CPU_Var = ULT);
- Is_ULX : <hswsklbool> :=
- ((Gen_Haswell or Gen_Skylake) and then CPU_Var = ULX);
- Is_LP : <hswskltglbool> := Is_ULT or Is_ULX;
---------- CPU pipe: ---------
Has_Tertiary_Pipe : <ilkbool> := Ivybridge_On;
@@ -235,16 +244,16 @@
----------- Transcoder -------
Need_Early_Transcoder_Setup : <genbool> := Tigerlake_On;
- Need_Pipe_Arb_Slots : <tglbool> := Alderlake_On;
+ Need_Pipe_Arb_Slots : <genbool> := AlderlakeP_On;
----------- Planes -----------
Has_Mbus_Dbox_Credits : <genbool> := Tigerlake_On;
+ Has_New_Mbus_Dbox_Credits : <genbool> := AlderlakeP_On;
Has_Wide_Watermarks : <genbool> := Tigerlake_On;
Has_Plane_Color_Control : <genbool> := Tigerlake_On;
- Has_New_Mbus_Dbox_Credits : <tglbool> := (Alderlake_On and Is_LP);
----------- Pipe -------------
- Need_Underrun_Rec_Disable : <tglbool> := Alderlake_On;
+ Need_Underrun_Rec_Disable : <genbool> := AlderlakeP_On;
--------- Panel power: -------
Has_PP_Write_Protection : <genbool> := Up_To_Ironlake;
@@ -293,7 +302,7 @@
Has_Broadwell_CDClk : <hswbool> := CPU_Broadwell;
Can_Switch_CDClk : <hswbool> := Broadwell_On;
Has_Fractional_RawClk : <genbool> := Cannon_Point_On;
- Has_New_Type_C_PLL_Enable : <tglbool> := Alderlake_On;
+ Has_New_Type_C_PLL_Enable : <genbool> := AlderlakeP_On;
----------- DDI: -------------
End_EDP_Training_Late : <genbool> := Gen_Haswell;
@@ -347,7 +356,7 @@
Need_Rawclk_Numerator : <genbool> := Tigerlake_On;
----------- Combo Phy --------
- Has_TGL_Buffer_Translations : <tglbool> := CPU_Tigerlake;
+ Has_TGL_Buffer_Translations : <genbool> := CPU_Tigerlake;
----------------------------------------------------------------------------
@@ -444,7 +453,7 @@
Maximum_Cursor_X : constant :=
(case Gen is
when I945 .. Ironlake => 4095,
- when Haswell .. Tigerlake => 8191);
+ when Haswell .. AlderlakeP => 8191);
Maximum_Cursor_Y : constant := 4095;
@@ -453,10 +462,10 @@
-- FIXME: Unknown for Broxton, Linux' i915 contains a fixme too :-D
HDMI_Max_Clock_24bpp : constant Frequency_Type :=
(case Gen is
- when Generation'First .. G45 => 165_000_000, -- i945: no HDMI, moot
- when Ironlake => 225_000_000,
- when Haswell .. Skylake => 300_000_000,
- when Tigerlake .. Generation'Last => 600_000_000);
+ when Generation'First .. G45 => 165_000_000, -- i945: no HDMI, moot
+ when Ironlake => 225_000_000,
+ when Haswell .. Skylake => 300_000_000,
+ when Tigerlake .. AlderlakeP => 600_000_000);
----------------------------------------------------------------------------
@@ -622,7 +631,7 @@
Device_Id = 16#a7ab# or
Device_Id = 16#a7ac# or
Device_Id = 16#a7ad#);
- function Is_Alder_Lake (Device_Id : Word16) return Boolean is
+ function Is_Alder_Lake_P_Gen (Device_Id : Word16) return Boolean is
(Is_Alder_Lake_P (Device_Id) or
Is_Alder_Lake_N (Device_Id) or
Is_Raptor_Lake_P (Device_Id));
@@ -673,9 +682,9 @@
Is_Tiger_Lake_U (Device_Id),
when ULX =>
False),
- when Alderlake => (case CPU_Var is
+ when AlderlakeP => (case CPU_Var is
when ULT =>
- Is_Alder_Lake (Device_Id),
+ Is_Alder_Lake_P_Gen (Device_Id),
when others =>
False));
diff --git a/common/hw-gfx-gma-config_helpers.adb b/common/hw-gfx-gma-config_helpers.adb
index 348c3e2..fab7145 100644
--- a/common/hw-gfx-gma-config_helpers.adb
+++ b/common/hw-gfx-gma-config_helpers.adb
@@ -58,7 +58,7 @@
when Primary => DIGI_B,
when Secondary => DIGI_C,
when Tertiary => DIGI_D)),
- when Tigerlake =>
+ when Tigerlake | AlderlakeP =>
(case Port is
when DP_TC1 | HDMI_TC1 | USBC1 => DDI_TC1,
when DP_TC2 | HDMI_TC2 | USBC2 => DDI_TC2,
@@ -68,7 +68,7 @@
Combo_PHY (Config.Panel_Ports (Panel_1)),
when others =>
Combo_PHY (Port)),
- when others => -- everything but VGA directly on CPU
+ when Haswell | Broxton | Skylake => -- everything but VGA directly on CPU
(case Port is
when LVDS => LVDS, -- n/a, actually
when eDP => DIGI_A,
diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads
index 2b1177c..18ca5d4 100644
--- a/common/hw-gfx-gma.ads
+++ b/common/hw-gfx-gma.ads
@@ -35,7 +35,15 @@
subtype GTT_Range is Natural range 0 .. 16#8_0000# - 1;
GTT_Rotation_Offset : constant GTT_Range := GTT_Range'Last / 2 + 1;
- type Generation is (I945, G45, Ironlake, Haswell, Broxton, Skylake, Tigerlake);
+ type Generation is
+ (I945,
+ G45,
+ Ironlake,
+ Haswell,
+ Broxton,
+ Skylake,
+ Tigerlake,
+ AlderlakeP);
type CPU_Type is
(I945G,
@@ -54,7 +62,7 @@
Skylake,
Kabylake,
Tigerlake,
- Alderlake);
+ AlderlakeP);
type CPU_Variant is (Normal, ULT, ULX);