commit b6df68391741f9cbcb8e286624d6994a6f9dbdf1
author Tim Wawrzynczak <twawrzynczak@chromium.org> Fri Sep 09 11:47:27 2022 -0600
committer Nico Huber <nico.h@gmx.de> Mon May 29 19:23:08 2023 +0000
tree 5c51a3f93ff02da2e65fef4121c9d8fd492a414b
parent 24748f320cff6c7f1d78e78aacc0e15bd68a52ac

gma registers: Update for Tiger Lake and Alder Lake

Add all of the necessary registers at once, so they do not distract
from the rest of the patches.

Change-Id: I32102b58018b62874d708b31621c3ca8f676ca02
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/70890
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>

common/skylake/hw-gfx-gma-power_and_clocks.adb

diff --git a/common/skylake/hw-gfx-gma-power_and_clocks.adb b/common/skylake/hw-gfx-gma-power_and_clocks.adb
index 21bb303..2841208 100644
--- a/common/skylake/hw-gfx-gma-power_and_clocks.adb
+++ b/common/skylake/hw-gfx-gma-power_and_clocks.adb
@@ -223,10 +223,10 @@
       end loop;
 
       Registers.Unset_Mask
-        (Register    => Registers.DBUF_CTL,
+        (Register    => Registers.DBUF_CTL_S0,
          Mask        => DBUF_CTL_DBUF_POWER_REQUEST);
       Registers.Wait_Unset_Mask
-        (Register    => Registers.DBUF_CTL,
+        (Register    => Registers.DBUF_CTL_S0,
          Mask        => DBUF_CTL_DBUF_POWER_STATE);
 
       Registers.Unset_Mask
@@ -304,10 +304,10 @@
                            when 450_000_000 => 1,
                            when others      => 0));
       Registers.Set_Mask
-        (Register    => Registers.DBUF_CTL,
+        (Register    => Registers.DBUF_CTL_S0,
          Mask        => DBUF_CTL_DBUF_POWER_REQUEST);
       Registers.Wait_Set_Mask
-        (Register    => Registers.DBUF_CTL,
+        (Register    => Registers.DBUF_CTL_S0,
          Mask        => DBUF_CTL_DBUF_POWER_STATE);
 
       Config.CDClk := CDClk;