gma g45: Read CDClk and calculate dot-clock limits
Numbers are taken from `intel_cdclk.c` of Linux' i915 driver.
We introduce three new procedures to the `Power_And_Clocks` interface:
o Limit_Dotclocks() limits the dot clocks of all pipe configs
according to the maximum supported CDClk. It also reports if
CDClk has to be switched for these configs.
o Update_CDClk() performs the CDClk switch if necessary. It may
further limit the dot clocks if the switch didn't succeed.
o Enable_CDClk() ensures that the CDClk is running. This may be
necessary to probe for DP displays when no pipes are active.
The latter two are no-ops for G45, as the CDClk runs at a fixed rate.
Dot clocks are limited to 90% of CDClk.
Change-Id: Ie50c0f8f51b3a0a6ed58c6461069c556cc92f51e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/35715
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template
index f7312fe..481897c 100644
--- a/common/hw-gfx-gma-config.ads.template
+++ b/common/hw-gfx-gma-config.ads.template
@@ -125,6 +125,7 @@
Broxton_On : <genbool> := Gen >= Broxton;
Skylake_On : <genbool> := Gen >= Skylake;
+ GMCH_GM45 : <g45bool> := Gen_G45 and then CPU = GM45;
CPU_Ironlake : <ilkbool> := Gen_Ironlake and then CPU = Ironlake;
CPU_Sandybridge : <ilkbool> := Gen_Ironlake and then CPU = Sandybridge;
CPU_Ivybridge : <ilkbool> := Gen_Ironlake and then CPU = Ivybridge;
@@ -205,6 +206,7 @@
Has_FDI_RX_Power_Down : <genbool> := Gen_Haswell;
Has_GMCH_RawClk : <genbool> := Gen_G45;
+ Has_GMCH_Mobile_VCO : <g45bool> := GMCH_GM45;
----------- DDI: -------------
End_EDP_Training_Late : <genbool> := Gen_Haswell;