Fix style issues and enable style checks
The enabled checks `3abdefhiklnprSx` are what we already live by
but didn't enforce so far. One check that we use internally, yet
omit here is `t`, token spacing. It's too aggressive and doesn't
allow for manual alignment of tables. The set of checks seems to
to fit our code base rather well, otherwise.
So following checks will be performed:
`3` Specify indentation level: 3 spaces.
`a` Check attribute casing: Attributes should appear in mixed case
`b` Blanks not allowed at statement end
`d` Check no DOS line terminators present: No CR/LF
`e` Check end/exit labels
`f` No form feeds or vertical tabs
`h` No horizontal tabs: We always use spaces
`i` Check if-then layout
`k` Check keyword casing: Keywords should appear in lower case
`l` Check layout: Follow layout recommendation of the Ada RM
`n` Check casing of entities in Standard: Should follow the Ada RM
`p` Check pragma casing: Should appear in mixed case
`r` Check reference: Identifiers should appear as in the declaration
`S` Check no statements after then/else
`x` Check extra parentheses: No C-syle parents arounds conditions
Change-Id: Ia07c571c3e3e4e49d8559099511b217ade86f33f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/533
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: Nico Huber <nico.h@gmx.de>
diff --git a/common/tigerlake/hw-gfx-gma-connectors-combo_phy.adb b/common/tigerlake/hw-gfx-gma-connectors-combo_phy.adb
index 057f221..46ed7db 100644
--- a/common/tigerlake/hw-gfx-gma-connectors-combo_phy.adb
+++ b/common/tigerlake/hw-gfx-gma-connectors-combo_phy.adb
@@ -303,15 +303,16 @@
function PORT_TX_DW2_RCOMP_SCALAR (R : Rcomp_Scalar) return Word32 is
(Word32 (R));
- procedure Set_Tx_Training (Port : Combo_Port; Training : Training_Values) is
+ procedure Set_Tx_Training (Port : Combo_Port; Training : Training_Values)
+ is
DW5 : Word32;
begin
- Registers.Read (Port_Regs (Port).PORT_TX_DW5_LN0, DW5);
- Registers.Write
- (Register => Port_Regs (Port).PORT_TX_DW5_GRP,
- Value => (if Training = Training_Enable
- then DW5 or PORT_TX_DW5_TX_TRAINING_EN
- else DW5 and not PORT_TX_DW5_TX_TRAINING_EN));
+ Registers.Read (Port_Regs (Port).PORT_TX_DW5_LN0, DW5);
+ Registers.Write
+ (Register => Port_Regs (Port).PORT_TX_DW5_GRP,
+ Value => (if Training = Training_Enable
+ then DW5 or PORT_TX_DW5_TX_TRAINING_EN
+ else DW5 and not PORT_TX_DW5_TX_TRAINING_EN));
end Set_Tx_Training;
Tmp : Word32;
@@ -444,7 +445,7 @@
if Link.Bandwidth > DP_Bandwidth_2_7 then
if Config.Is_LP then
return TGL_Buffer_Trans_DP_HBR2_U_Y;
- else
+ else
return TGL_Buffer_Trans_DP_HBR2;
end if;
else