Fix style issues and enable style checks
The enabled checks `3abdefhiklnprSx` are what we already live by
but didn't enforce so far. One check that we use internally, yet
omit here is `t`, token spacing. It's too aggressive and doesn't
allow for manual alignment of tables. The set of checks seems to
to fit our code base rather well, otherwise.
So following checks will be performed:
`3` Specify indentation level: 3 spaces.
`a` Check attribute casing: Attributes should appear in mixed case
`b` Blanks not allowed at statement end
`d` Check no DOS line terminators present: No CR/LF
`e` Check end/exit labels
`f` No form feeds or vertical tabs
`h` No horizontal tabs: We always use spaces
`i` Check if-then layout
`k` Check keyword casing: Keywords should appear in lower case
`l` Check layout: Follow layout recommendation of the Ada RM
`n` Check casing of entities in Standard: Should follow the Ada RM
`p` Check pragma casing: Should appear in mixed case
`r` Check reference: Identifiers should appear as in the declaration
`S` Check no statements after then/else
`x` Check extra parentheses: No C-syle parents arounds conditions
Change-Id: Ia07c571c3e3e4e49d8559099511b217ade86f33f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/533
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: Nico Huber <nico.h@gmx.de>
diff --git a/common/tigerlake/hw-gfx-gma-combo_phy.adb b/common/tigerlake/hw-gfx-gma-combo_phy.adb
index 446fa66..aafe581 100644
--- a/common/tigerlake/hw-gfx-gma-combo_phy.adb
+++ b/common/tigerlake/hw-gfx-gma-combo_phy.adb
@@ -159,7 +159,7 @@
Registers.Read (Phy_Regs (Phy).PORT_COMP_DW3, DW3);
Tmp := Shift_Right (DW3 and VOLTAGE_MASK, 24);
- case (Tmp) is
+ case Tmp is
when 0 => Voltage := VOLT_0_85;
when 1 => Voltage := VOLT_0_95;
when 2 => Voltage := VOLT_1_05;
@@ -167,23 +167,23 @@
end case;
Tmp := Shift_Right (DW3 and PROCESS_MASK, 26);
- case (Tmp) is
+ case Tmp is
when 0 => Process := DOT0;
when 1 => Process := DOT1;
when others => Process := DOT0;
end case;
if Process = DOT0 then
- case (Voltage) is
+ case Voltage is
when VOLT_0_85 => References := DOT0_VOLT_0_85;
when VOLT_0_95 => References := DOT0_VOLT_0_95;
- when VOLT_1_05 => References := DOT0_VOLT_1_05;
+ when VOLT_1_05 => References := DOT0_VOLT_1_05;
end case;
else
- case (Voltage) is
+ case Voltage is
-- [DOT1, VOLT_0_85] is actually an invalid combination
- when VOLT_0_95 | VOLT_0_85 => References := DOT1_VOLT_0_95;
- when VOLT_1_05 => References := DOT1_VOLT_1_05;
+ when VOLT_0_95 | VOLT_0_85 => References := DOT1_VOLT_0_95;
+ when VOLT_1_05 => References := DOT1_VOLT_1_05;
end case;
end if;
end Read_DW3;
@@ -211,8 +211,8 @@
Was_Enabled : Boolean;
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
- -- Initialize all combo PHYs with Combo PHY DDI Buffer Combo PHY Init Sequence
- for Phy in Combo_Phy'range loop
+ -- Initialize all combo PHYs with Combo PHY DDI Buffer Combo PHY Init Sequence
+ for Phy in Combo_Phy'Range loop
Registers.Is_Set_Mask (
Phy_Regs (Phy).PORT_COMP_DW0,
PORT_COMP_DW0_COMP_INIT,
@@ -243,7 +243,7 @@
procedure All_Off is
begin
- for Phy in Combo_Phy'range loop
+ for Phy in Combo_Phy'Range loop
Registers.Set_Mask (Phy_Regs (Phy).PHY_MISC,
PHY_MISC_DE_TO_IO_COMP_PWR_DOWN);