diff --git a/Makefile b/Makefile
index 008b2b3..215f292 100644
--- a/Makefile
+++ b/Makefile
@@ -11,6 +11,11 @@
 libhw-dir ?= ../libhwbase/dest
 include $(libhw-dir)/Makefile
 
+$(gfxinit-objs): ADAFLAGS += -gnaty3abdefhiklnprSx
+
+# Allow statements after then/else as we arrange cmdline parsing as a table
+$(call src-to-obj,,gfxtest/hw-gfx-gma-gfx_test.adb): ADAFLAGS += -gnaty-S
+
 gfx_test: $(binary)
 
 .PHONY: gfx_test
diff --git a/common/g45/hw-gfx-gma-plls.adb b/common/g45/hw-gfx-gma-plls.adb
index fcc08ad..2b93444 100644
--- a/common/g45/hw-gfx-gma-plls.adb
+++ b/common/g45/hw-gfx-gma-plls.adb
@@ -118,7 +118,7 @@
       P2_Fast      =>   7,           P2_Slow   =>   7,
       P2_Threshold => Clock_Range'First,
       VCO_Lower    => 1_750_000_000, VCO_Upper => 3_500_000_000);
-    SDVO_Limits : constant Limits_Type := Limits_Type'
+   SDVO_Limits : constant Limits_Type := Limits_Type'
      (N_Lower      =>   3,           N_Upper   =>   6,
       M_Lower      =>  104,          M_Upper   => 138,
       M1_Lower     =>  16,           M1_Upper  =>  25,
@@ -129,7 +129,7 @@
       P2_Fast      =>   5,          P2_Slow   =>  10,
       P2_Threshold =>   270_000_000,
       VCO_Lower    => 1_750_000_000, VCO_Upper => 3_500_000_000);
-    HDMI_Analog_Limits : constant Limits_Type := Limits_Type'
+   HDMI_Analog_Limits : constant Limits_Type := Limits_Type'
      (N_Lower      =>   3,           N_Upper   =>   6,
       M_Lower      =>  104,          M_Upper   => 138,
       M1_Lower     =>  18,           M1_Upper  =>  25,
@@ -203,7 +203,7 @@
       DP       => MODE_DPLL_DP,
       HDMI     => MODE_DPLL_HDMI,
       VGA      => MODE_DPLL_DAC,
-      Others   => MODE_DPLL_HDMI); --TODO Add SDVO
+      others   => MODE_DPLL_HDMI); --TODO Add SDVO
 
    FP0 : constant Regs := Regs'(Registers.GMCH_FPA0, Registers.GMCH_FPB0);
    FP1 : constant Regs := Regs'(Registers.GMCH_FPA1, Registers.GMCH_FPB1);
diff --git a/common/g45/hw-gfx-gma-port_detect.adb b/common/g45/hw-gfx-gma-port_detect.adb
index 6fdb527..f1d15ca 100644
--- a/common/g45/hw-gfx-gma-port_detect.adb
+++ b/common/g45/hw-gfx-gma-port_detect.adb
@@ -49,7 +49,7 @@
       DIGI_C => Registers.GMCH_DP_C,
       DIGI_D => Registers.GMCH_DP_D);
 
-   HOTPLUG_INT_STATUS : constant array (Active_Port_Type) of word32 :=
+   HOTPLUG_INT_STATUS : constant array (Active_Port_Type) of Word32 :=
      (DP1    => 3 * 2 ** 17,
       DP2    => 3 * 2 ** 19,
       DP3    => 3 * 2 ** 21,
@@ -109,7 +109,7 @@
       Detected := (Ctl32 and HOTPLUG_INT_STATUS (Port)) /= 0;
 
       if Detected then
-         registers.Set_Mask
+         Registers.Set_Mask
            (Register => Registers.PORT_HOTPLUG_STAT,
             Mask     => HOTPLUG_INT_STATUS (Port));
       end if;
diff --git a/common/hw-gfx-dp_aux_ch.adb b/common/hw-gfx-dp_aux_ch.adb
index 20c2c3c..7bfbab6 100644
--- a/common/hw-gfx-dp_aux_ch.adb
+++ b/common/hw-gfx-dp_aux_ch.adb
@@ -173,12 +173,12 @@
    ----------------------------------------------------------------------------
 
    procedure I2C_Out_Packet
-     (Port              : in     T;
-      Command           : in     DP_Defs.Aux_Message_Command;
-      Address           : in     DP_Defs.Aux_Message_Address;
-      Length            : in     DP_Defs.Aux_Payload_Length;
-      Data              : in     DP_Defs.Aux_Payload;
-      Success           :    out Boolean)
+     (Port     : in     T;
+      Command  : in     DP_Defs.Aux_Message_Command;
+      Address  : in     DP_Defs.Aux_Message_Address;
+      Length   : in     DP_Defs.Aux_Payload_Length;
+      Data     : in     DP_Defs.Aux_Payload;
+      Success  :    out Boolean)
    is
       Request : DP_Defs.Aux_Request;
 
@@ -265,10 +265,10 @@
    end I2C_In_Packet;
 
    procedure I2C_Empty_Packet
-     (Port              : in     T;
-      Command           : in     DP_Defs.Aux_Message_Command;
-      Address           : in     DP_Defs.Aux_Message_Address;
-      Success           :    out Boolean)
+     (Port     : in     T;
+      Command  : in     DP_Defs.Aux_Message_Command;
+      Address  : in     DP_Defs.Aux_Message_Address;
+      Success  :    out Boolean)
    is
       Ignored_Response        : DP_Defs.Aux_Response;
       Ignored_Response_Length : DP_Defs.Aux_Response_Length;
@@ -306,12 +306,12 @@
 
       if Success then
          I2C_Out_Packet
-           (Port              => Port,
-            Command           => DP_AUX_I2C_WRITE or DP_AUX_I2C_MOT,
-            Address           => DP_Defs.Aux_Message_Address (Address),
-            Length            => Length,
-            Data              => Data,
-            Success           => Success);
+           (Port     => Port,
+            Command  => DP_AUX_I2C_WRITE or DP_AUX_I2C_MOT,
+            Address  => DP_Defs.Aux_Message_Address (Address),
+            Length   => Length,
+            Data     => Data,
+            Success  => Success);
 
          pragma Warnings
            (GNATprove, Off, "unused assignment to ""Ignored_Success""",
diff --git a/common/hw-gfx-dp_info.adb b/common/hw-gfx-dp_info.adb
index 74e77a2..09e3da6 100644
--- a/common/hw-gfx-dp_info.adb
+++ b/common/hw-gfx-dp_info.adb
@@ -268,7 +268,7 @@
          N     : in out Calc_N_Type;
          N_Max : in     N_Rounded_Type)
       with
-         Depends => ((M, N) => (M, N, N_max)),
+         Depends => ((M, N) => (M, N, N_Max)),
          Pre => (N > 0 and M in 0 .. Calc_M_Type'Last / 2),
          Post => (M <= M_N_Max and N <= M_N_Max)
       is
@@ -294,7 +294,7 @@
 
          -- The automatic provers need a little nudge here.
          pragma Assert
-            (if M <= Calc_M_Type'Last/2 and
+            (if M <= Calc_M_Type'Last / 2 and
                 N <= Orig_N * 2 and
                 Orig_N > 0 and
                 M > 0
diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template
index a041e2c..763a22d 100644
--- a/common/hw-gfx-gma-config.ads.template
+++ b/common/hw-gfx-gma-config.ads.template
@@ -446,7 +446,7 @@
          when Generation'First .. G45      => 165_000_000, -- i945: no HDMI, moot
          when Ironlake                     => 225_000_000,
          when Haswell .. Skylake           => 300_000_000,
-	 when Tigerlake .. Generation'Last => 600_000_000);
+         when Tigerlake .. Generation'Last => 600_000_000);
 
    ----------------------------------------------------------------------------
 
@@ -578,7 +578,7 @@
       Device_Id = 16#9a68# or
       Device_Id = 16#9a70#);
 
-   function Is_Alder_Lake_P (Device_ID : Word16) return Boolean is
+   function Is_Alder_Lake_P (Device_Id : Word16) return Boolean is
      (Device_Id = 16#46a0# or
       Device_Id = 16#46a1# or
       Device_Id = 16#46a2# or
@@ -597,11 +597,11 @@
       Device_Id = 16#46c1# or
       Device_Id = 16#46c2# or
       Device_Id = 16#46c3#);
-   function Is_Alder_Lake_N (Device_ID : Word16) return Boolean is
+   function Is_Alder_Lake_N (Device_Id : Word16) return Boolean is
      (Device_Id = 16#46d0# or
       Device_Id = 16#46d1# or
       Device_Id = 16#46d2#);
-   function Is_Raptor_Lake_P (Device_ID : Word16) return Boolean is
+   function Is_Raptor_Lake_P (Device_Id : Word16) return Boolean is
      (Device_Id = 16#a720# or
       Device_Id = 16#a721# or
       Device_Id = 16#a7a0# or
@@ -663,7 +663,7 @@
                                 when Normal =>
                                    False,
                                 when ULT | ULX =>
-                                   Is_Alder_Lake (Device_ID)));
+                                   Is_Alder_Lake (Device_Id)));
 
    function Compatible_GPU (Device_Id : Word16) return Boolean is
      (Is_GPU (Device_Id, CPU, CPU_Var));
diff --git a/common/hw-gfx-gma-i2c.adb b/common/hw-gfx-gma-i2c.adb
index 2e0dde0..737d240 100644
--- a/common/hw-gfx-gma-i2c.adb
+++ b/common/hw-gfx-gma-i2c.adb
@@ -119,17 +119,17 @@
    begin
       return
         (if Config.Has_Type_C_Ports then
-	   (case Port is
-	       when PCH_HDMI_A   => GMBUS0_PIN_PAIR_SELECT_TGL_1,
-	       when PCH_HDMI_B   => GMBUS0_PIN_PAIR_SELECT_TGL_2,
-	       when PCH_HDMI_C   => GMBUS0_PIN_PAIR_SELECT_TGL_3,
-	       when PCH_TC1      => GMBUS0_PIN_PAIR_SELECT_TGL_TC1,
-	       when PCH_TC2      => GMBUS0_PIN_PAIR_SELECT_TGL_TC2,
-	       when PCH_TC3      => GMBUS0_PIN_PAIR_SELECT_TGL_TC3,
-	       when PCH_TC4      => GMBUS0_PIN_PAIR_SELECT_TGL_TC4,
-	       when PCH_TC5      => GMBUS0_PIN_PAIR_SELECT_TGL_TC5,
-	       when PCH_TC6      => GMBUS0_PIN_PAIR_SELECT_TGL_TC6,
-	       when others       => GMBUS0_PIN_PAIR_SELECT_NONE)
+           (case Port is
+               when PCH_HDMI_A   => GMBUS0_PIN_PAIR_SELECT_TGL_1,
+               when PCH_HDMI_B   => GMBUS0_PIN_PAIR_SELECT_TGL_2,
+               when PCH_HDMI_C   => GMBUS0_PIN_PAIR_SELECT_TGL_3,
+               when PCH_TC1      => GMBUS0_PIN_PAIR_SELECT_TGL_TC1,
+               when PCH_TC2      => GMBUS0_PIN_PAIR_SELECT_TGL_TC2,
+               when PCH_TC3      => GMBUS0_PIN_PAIR_SELECT_TGL_TC3,
+               when PCH_TC4      => GMBUS0_PIN_PAIR_SELECT_TGL_TC4,
+               when PCH_TC5      => GMBUS0_PIN_PAIR_SELECT_TGL_TC5,
+               when PCH_TC6      => GMBUS0_PIN_PAIR_SELECT_TGL_TC6,
+               when others       => GMBUS0_PIN_PAIR_SELECT_NONE)
         elsif Config.GMBUS_Alternative_Pins then
            (case Port is
                when PCH_HDMI_B   => GMBUS0_PIN_PAIR_SELECT_BXT_B,
@@ -256,11 +256,11 @@
                         GMBUS1_DIRECTION_READ);
 
          while Success and then Transfered < Length loop
-	    -- Some GMBUS state machines never set HW_RDY nor NAK.
-	    --
-	    -- Keep delay at a minimum, but big enough that
-	    -- regular EDID transfers can be finished within
-	    -- the timeout.
+            -- Some GMBUS state machines never set HW_RDY nor NAK.
+            --
+            -- Keep delay at a minimum, but big enough that
+            -- regular EDID transfers can be finished within
+            -- the timeout.
             Registers.Wait_Set_Mask
               (Register => GMBUS_Regs (2),
                Mask     => GMBUS2_HARDWARE_READY,
diff --git a/common/hw-gfx-gma-panel.adb b/common/hw-gfx-gma-panel.adb
index 532bf67..e46c607 100644
--- a/common/hw-gfx-gma-panel.adb
+++ b/common/hw-gfx-gma-panel.adb
@@ -443,9 +443,9 @@
 
       pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
 
-     Registers.Unset_Mask
-       (Register => PP (Panel).CONTROL,
-        Mask     => PCH_PP_CONTROL_BACKLIGHT_ENABLE);
+      Registers.Unset_Mask
+        (Register => PP (Panel).CONTROL,
+         Mask     => PCH_PP_CONTROL_BACKLIGHT_ENABLE);
 
       if Config.Has_New_Backlight_Control then
          Registers.Unset_Mask
diff --git a/common/hw-gfx-gma-pipe_setup.adb b/common/hw-gfx-gma-pipe_setup.adb
index 3fcdc4d..5e32281 100644
--- a/common/hw-gfx-gma-pipe_setup.adb
+++ b/common/hw-gfx-gma-pipe_setup.adb
@@ -841,7 +841,7 @@
             Result   => Used_For_Secondary);
          Pipe := (if Used_For_Secondary then Secondary else Primary);
       end if;
-   end;
+   end Gmch_Panel_Fitter_Pipe;
 
    procedure Panel_Fitter_Off (Controller : Controller_Type)
    is
diff --git a/common/hw-gfx-gma-registers.adb b/common/hw-gfx-gma-registers.adb
index a59a4f7..012ccf6 100644
--- a/common/hw-gfx-gma-registers.adb
+++ b/common/hw-gfx-gma-registers.adb
@@ -504,7 +504,7 @@
       Success    :    out Boolean) is
    begin
       Wait (Register, Mask, 0, TOut_MS, Verbose, Success);
-   end;
+   end Wait_Unset_Mask;
 
    procedure Wait_Unset_Mask
      (Register : Registers_Index;
diff --git a/common/hw-gfx-gma-transcoder.adb b/common/hw-gfx-gma-transcoder.adb
index 213af3b..2452b44 100644
--- a/common/hw-gfx-gma-transcoder.adb
+++ b/common/hw-gfx-gma-transcoder.adb
@@ -269,11 +269,11 @@
       if Config.Need_Early_Transcoder_Setup and then
          Trans.CLK_SEL /= Registers.Invalid_Register and then
          Port_Cfg.Port in TGL_Digital_Port
-         then
-            Registers.Unset_And_Set_Mask
-              (Register   => Trans.CLK_SEL,
-               Mask_Unset => TRANS_CLK_SEL_MASK,
-               Mask_Set   => TGL_TRANS_CLK_SEL_PORT (Port_Cfg.Port));
+      then
+         Registers.Unset_And_Set_Mask
+           (Register   => Trans.CLK_SEL,
+            Mask_Unset => TRANS_CLK_SEL_MASK,
+            Mask_Set   => TGL_TRANS_CLK_SEL_PORT (Port_Cfg.Port));
       end if;
    end Enable_Pipe_Clock;
 
diff --git a/common/i945/hw-gfx-gma-plls.adb b/common/i945/hw-gfx-gma-plls.adb
index 96ba6af..a5e272c 100644
--- a/common/i945/hw-gfx-gma-plls.adb
+++ b/common/i945/hw-gfx-gma-plls.adb
@@ -166,7 +166,7 @@
      (LVDS     => MODE_DPLL_LVDS,
       VGA      => MODE_DPLL_DAC,
       HDMI     => MODE_DPLL_SDVO,  -- SDVO outputs use HDMI display type
-      Others   => MODE_DPLL_SDVO);
+      others   => MODE_DPLL_SDVO);
 
    FP0 : constant Regs := Regs'(Registers.GMCH_FPA0, Registers.GMCH_FPB0);
    FP1 : constant Regs := Regs'(Registers.GMCH_FPA1, Registers.GMCH_FPB1);
diff --git a/common/tigerlake/hw-gfx-gma-combo_phy.adb b/common/tigerlake/hw-gfx-gma-combo_phy.adb
index 446fa66..aafe581 100644
--- a/common/tigerlake/hw-gfx-gma-combo_phy.adb
+++ b/common/tigerlake/hw-gfx-gma-combo_phy.adb
@@ -159,7 +159,7 @@
          Registers.Read (Phy_Regs (Phy).PORT_COMP_DW3, DW3);
 
          Tmp := Shift_Right (DW3 and VOLTAGE_MASK, 24);
-         case (Tmp) is
+         case Tmp is
             when 0 => Voltage := VOLT_0_85;
             when 1 => Voltage := VOLT_0_95;
             when 2 => Voltage := VOLT_1_05;
@@ -167,23 +167,23 @@
          end case;
 
          Tmp := Shift_Right (DW3 and PROCESS_MASK, 26);
-         case (Tmp) is
+         case Tmp is
             when 0 => Process := DOT0;
             when 1 => Process := DOT1;
             when others => Process := DOT0;
          end case;
 
          if Process = DOT0 then
-            case (Voltage) is
+            case Voltage is
                when VOLT_0_85 => References := DOT0_VOLT_0_85;
                when VOLT_0_95 => References := DOT0_VOLT_0_95;
-               when VOLT_1_05 =>  References := DOT0_VOLT_1_05;
+               when VOLT_1_05 => References := DOT0_VOLT_1_05;
             end case;
          else
-            case (Voltage) is
+            case Voltage is
                -- [DOT1, VOLT_0_85] is actually an invalid combination
-	       when VOLT_0_95 | VOLT_0_85 => References := DOT1_VOLT_0_95;
-               when VOLT_1_05 =>  References := DOT1_VOLT_1_05;
+               when VOLT_0_95 | VOLT_0_85 => References := DOT1_VOLT_0_95;
+               when VOLT_1_05             => References := DOT1_VOLT_1_05;
             end case;
          end if;
       end Read_DW3;
@@ -211,8 +211,8 @@
       Was_Enabled : Boolean;
    begin
       pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
-       -- Initialize all combo PHYs with Combo PHY DDI Buffer Combo PHY Init Sequence
-      for Phy in Combo_Phy'range loop
+      -- Initialize all combo PHYs with Combo PHY DDI Buffer Combo PHY Init Sequence
+      for Phy in Combo_Phy'Range loop
          Registers.Is_Set_Mask (
             Phy_Regs (Phy).PORT_COMP_DW0,
             PORT_COMP_DW0_COMP_INIT,
@@ -243,7 +243,7 @@
 
    procedure All_Off is
    begin
-      for Phy in Combo_Phy'range loop
+      for Phy in Combo_Phy'Range loop
          Registers.Set_Mask (Phy_Regs (Phy).PHY_MISC,
                              PHY_MISC_DE_TO_IO_COMP_PWR_DOWN);
 
diff --git a/common/tigerlake/hw-gfx-gma-connectors-combo_phy.adb b/common/tigerlake/hw-gfx-gma-connectors-combo_phy.adb
index 057f221..46ed7db 100644
--- a/common/tigerlake/hw-gfx-gma-connectors-combo_phy.adb
+++ b/common/tigerlake/hw-gfx-gma-connectors-combo_phy.adb
@@ -303,15 +303,16 @@
       function PORT_TX_DW2_RCOMP_SCALAR (R : Rcomp_Scalar) return Word32 is
          (Word32 (R));
 
-      procedure Set_Tx_Training (Port : Combo_Port; Training : Training_Values) is
+      procedure Set_Tx_Training (Port : Combo_Port; Training : Training_Values)
+      is
          DW5 : Word32;
       begin
-        Registers.Read (Port_Regs (Port).PORT_TX_DW5_LN0, DW5);
-        Registers.Write
-          (Register => Port_Regs (Port).PORT_TX_DW5_GRP,
-           Value    => (if Training = Training_Enable
-                        then DW5 or PORT_TX_DW5_TX_TRAINING_EN
-                        else DW5 and not PORT_TX_DW5_TX_TRAINING_EN));
+         Registers.Read (Port_Regs (Port).PORT_TX_DW5_LN0, DW5);
+         Registers.Write
+           (Register => Port_Regs (Port).PORT_TX_DW5_GRP,
+            Value    => (if Training = Training_Enable
+                         then DW5 or PORT_TX_DW5_TX_TRAINING_EN
+                         else DW5 and not PORT_TX_DW5_TX_TRAINING_EN));
       end Set_Tx_Training;
 
       Tmp : Word32;
@@ -444,7 +445,7 @@
                if Link.Bandwidth > DP_Bandwidth_2_7 then
                   if Config.Is_LP then
                      return TGL_Buffer_Trans_DP_HBR2_U_Y;
-                 else
+                  else
                      return TGL_Buffer_Trans_DP_HBR2;
                   end if;
                else
diff --git a/common/tigerlake/hw-gfx-gma-connectors-tc.adb b/common/tigerlake/hw-gfx-gma-connectors-tc.adb
index 4b84f3c..5cce6c4 100644
--- a/common/tigerlake/hw-gfx-gma-connectors-tc.adb
+++ b/common/tigerlake/hw-gfx-gma-connectors-tc.adb
@@ -42,7 +42,7 @@
       DDI_TC5 => Registers.DKL_DP_MODE_5,
       DDI_TC6 => Registers.DKL_DP_MODE_6);
 
-   function DP_PIN_ASSIGNMENT_SHIFT (P : USBC_Port) return natural is
+   function DP_PIN_ASSIGNMENT_SHIFT (P : USBC_Port) return Natural is
      (case P is
       when DDI_TC1 => 0,
       when DDI_TC2 => 4,
@@ -104,7 +104,7 @@
          Registers.PORT_TX_DFLEXDPCSSS_FIA3,
          Registers.PORT_TX_DFLEXPA1_FIA3));
 
-   function Fia_Index (Port : USBC_Port) return natural
+   function Fia_Index (Port : USBC_Port) return Natural
    is (case Port is
        when DDI_TC1 | DDI_TC3 | DDI_TC5 => 0,
        when DDI_TC2 | DDI_TC4 | DDI_TC6 => 1);
@@ -129,7 +129,7 @@
       (Shift_Left (1, Fia_Index (Port) * 8 + 5));
    function DP_LANE_ASSIGNMENT_MASK (Port : USBC_Port) return Word32 is
       (Shift_Left (16#f#, Fia_Index (Port) * 8));
-   function DP_LANE_ASSIGNMENT_SHIFT (Port : USBC_Port) return natural is
+   function DP_LANE_ASSIGNMENT_SHIFT (Port : USBC_Port) return Natural is
       (Fia_Index (Port) * 8);
 
    DDI_BUF_CTL_BUFFER_ENABLE        : constant :=      1 * 2 ** 31;
@@ -159,7 +159,7 @@
       Deemphasis_Control : Word32;
    end record;
 
-   type Buffer_Trans_Range is new natural range 0 .. 9;
+   type Buffer_Trans_Range is new Natural range 0 .. 9;
    type Buffer_Trans_Array is array (Buffer_Trans_Range) of Buffer_Trans;
    TGL_Buffer_Trans_DP_HBR2 : constant Buffer_Trans_Array :=
      ((16#7#, 16#0#, 16#00#),
@@ -261,7 +261,7 @@
       Registers.Write (HIP_INDEX_REG (P), HIP_INDEX_VAL (P, Word32 (N)));
    end Set_HIP_For_Port;
 
-   subtype Pin_Assignment_Type is natural range 0 .. 6;
+   subtype Pin_Assignment_Type is Natural range 0 .. 6;
    procedure Get_Pin_Assignment
      (P          : in    USBC_Port;
       Assignment : out   Pin_Assignment_Type)
@@ -273,7 +273,7 @@
       A := Shift_Right (Tmp, DP_PIN_ASSIGNMENT_SHIFT (P));
       A := A and DP_PIN_ASSIGNMENT_MASK;
 
-      if natural (A) in Pin_Assignment_Type then
+      if Natural (A) in Pin_Assignment_Type then
          Assignment := Pin_Assignment_Type (A);
       else
          Assignment := Pin_Assignment_Type'First;
@@ -411,8 +411,8 @@
    is
       procedure Get_Lane_Assignment_Count (Lanes : out DP_Lane_Count)
       is
-          Lane_Mask : Word32;
-          Tmp : Word32;
+         Lane_Mask : Word32;
+         Tmp : Word32;
       begin
          Registers.Read (Fia_Regs (Port).PORT_TX_DFLEXDPSP, Tmp);
          Lane_Mask := Shift_Right (Tmp and DP_LANE_ASSIGNMENT_MASK (Port),
diff --git a/common/tigerlake/hw-gfx-gma-connectors.adb b/common/tigerlake/hw-gfx-gma-connectors.adb
index 02a208b..4c1171f 100644
--- a/common/tigerlake/hw-gfx-gma-connectors.adb
+++ b/common/tigerlake/hw-gfx-gma-connectors.adb
@@ -152,9 +152,9 @@
             Mask     => DDI_BUF_CTL_IDLE_STATUS);
       end if;
 
-     Registers.Set_Mask
-       (Register => Registers.DPCLKA_CFGCR0,
-        Mask     => DDI_CLK_OFF (Port));
+      Registers.Set_Mask
+        (Register => Registers.DPCLKA_CFGCR0,
+         Mask     => DDI_CLK_OFF (Port));
    end Off;
 
    procedure Off (Port_Info : Training_Port_Info) is
diff --git a/common/tigerlake/hw-gfx-gma-plls-combo_phy.adb b/common/tigerlake/hw-gfx-gma-plls-combo_phy.adb
index d74cf56..f08b6fb 100644
--- a/common/tigerlake/hw-gfx-gma-plls-combo_phy.adb
+++ b/common/tigerlake/hw-gfx-gma-plls-combo_phy.adb
@@ -51,17 +51,17 @@
 
    procedure Encode_DCO (DCO_Integer, DCO_Fraction : out Word32; DCO : DCO_Range)
    is
-      Refclk_Freq : Power_And_Clocks.Refclk_Range;
+      RefClk_Freq : Power_And_Clocks.RefClk_Range;
       Enc_DCO : Int64;
    begin
-      Power_And_Clocks.Get_Refclk (Refclk_Freq);
+      Power_And_Clocks.Get_RefClk (RefClk_Freq);
 
       -- DPLL will auto-divide by 2 if refclk is 38.4 MHz
-      if Refclk_Freq = 38_400_000 then
-         Refclk_Freq := 19_200_000;
+      if RefClk_Freq = 38_400_000 then
+         RefClk_Freq := 19_200_000;
       end if;
 
-      Enc_DCO := (DCO / 1_000) * (2 ** 15) / (Refclk_Freq / 1_000);
+      Enc_DCO := (DCO / 1_000) * (2 ** 15) / (RefClk_Freq / 1_000);
       DCO_Integer := Word32 (Enc_DCO / (2 ** 15));
       DCO_Fraction := Word32 (Enc_DCO) and 16#7fff#;
    end Encode_DCO;
@@ -162,10 +162,10 @@
      (Bandwidth : in     DP_Bandwidth;
       Params    :    out PLL_Params)
    is
-      Refclk : Frequency_Type;
+      RefClk : Frequency_Type;
    begin
-      Power_And_Clocks.Get_Refclk (Refclk);
-      if Refclk = 24_000_000 then
+      Power_And_Clocks.Get_RefClk (RefClk);
+      if RefClk = 24_000_000 then
          Params := PLL_Params_24MHz (Bandwidth);
       else
          Params := PLL_Params_19_2MHz (Bandwidth);
@@ -276,7 +276,7 @@
       Success  :    out Boolean)
    is
       Params : PLL_Params;
-      Refclk : Frequency_Type;
+      RefClk : Frequency_Type;
    begin
       if Port_Cfg.Display = DP then
          Calc_DP_PLL_Dividers (Port_Cfg.DP.Bandwidth, Params);
@@ -303,8 +303,8 @@
       -- Display WA #22010492432: ehl, tgl, adl-p
       -- Program half of the nominal DCO divider fraction value
       -- for 38.4 MHz refclk
-      Power_And_Clocks.Get_Refclk (Refclk);
-      if Refclk = 38_400_000 then
+      Power_And_Clocks.Get_RefClk (RefClk);
+      if RefClk = 38_400_000 then
          Params.DCO_Fraction := Shift_Right (Params.DCO_Fraction, 1);
       end if;
 
@@ -335,7 +335,7 @@
         (Register => PLL_Regs (PLL).DPLL_CFGCR1,
          Value => Shift_Left (Word32 (Params.QDiv), 10) or
                   Shift_Left (Word32 (QDiv_Mode (Params.QDiv)), 9) or
-                  Shift_left (Word32 (Params.KDiv), 6) or
+                  Shift_Left (Word32 (Params.KDiv), 6) or
                   Shift_Left (Word32 (Params.PDiv), 2));
       Registers.Posting_Read(PLL_Regs (PLL).DPLL_CFGCR1);
 
diff --git a/common/tigerlake/hw-gfx-gma-plls-dekel_phy.adb b/common/tigerlake/hw-gfx-gma-plls-dekel_phy.adb
index 9172dad..2926288 100644
--- a/common/tigerlake/hw-gfx-gma-plls-dekel_phy.adb
+++ b/common/tigerlake/hw-gfx-gma-plls-dekel_phy.adb
@@ -143,10 +143,10 @@
    procedure Calc_Dividers
       (Clock                   : in     Frequency_Type;
        Display                 : in     Display_Type;
-       DKL_Refclkin_Ctl        :    out Word32;
-       DKL_Clktop2_Coreclkctl1 :    out Word32;
-       DKL_Clktop2_HSClkCtl    :    out Word32;
-       DCO_Khz                 :    out DCO_Range_KHz;
+       DKL_RefClkin_Ctl        :    out Word32;
+       DKL_ClkTop2_CoreClkCtl1 :    out Word32;
+       DKL_ClkTop2_HSClkCtl    :    out Word32;
+       DCO_KHz                 :    out DCO_Range_KHz;
        Success                 :    out Boolean)
    is
       DCO_Min_Freq, DCO_Max_Freq : Int64;
@@ -176,9 +176,9 @@
          DCO_Max_Freq := DCO_Range_KHz'Last;
       end if;
 
-      DKL_Refclkin_Ctl := 0;
-      DKL_clktop2_coreclkctl1 := 0;
-      DKL_CLKTOP2_hsclkctl := 0;
+      DKL_RefClkin_Ctl := 0;
+      DKL_ClkTop2_CoreClkCtl1 := 0;
+      DKL_ClkTop2_HSClkCtl := 0;
 
       DCO_KHz := DCO_Min_Freq;
       Success := False;
@@ -205,10 +205,10 @@
                             when 5 => DKL_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5,
                             when 7 => DKL_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7,
                             when others => DKL_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2);
-                  DKL_Refclkin_Ctl := DKL_REFCLKIN_CTL_OD_2_MUX (1);
-                  DKL_clktop2_coreclkctl1 :=
+                  DKL_RefClkin_Ctl := DKL_REFCLKIN_CTL_OD_2_MUX (1);
+                  DKL_ClkTop2_CoreClkCtl1 :=
                                 DKL_CLKTOP2_CORECLKCTL1_A_DIVRATIO (A_DivRatio);
-                  DKL_CLKTOP2_hsclkctl :=
+                  DKL_ClkTop2_HSClkCtl :=
                      DKL_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL (TLineDrv) or
                      DKL_CLKTOP2_HSCLKCTL_CORE_INPUTSEL (Inputsel) or
                      Hsdiv or
@@ -227,10 +227,10 @@
       Port_Cfg : in     Port_Config;
       Success  :    out Boolean)
    is
-      DKL_Refclkin_Ctl : Word32;
-      DKL_Clktop2_Coreclkctl1 : Word32;
-      DKL_Clktop2_HSClkCtl : Word32;
-      DCO_Khz : DCO_Range_KHz;
+      DKL_RefClkin_Ctl : Word32;
+      DKL_ClkTop2_CoreClkCtl1 : Word32;
+      DKL_ClkTop2_HSClkCtl : Word32;
+      DCO_KHz : DCO_Range_KHz;
       Clock : Frequency_Type;
    begin
       if Port_Cfg.Display = HDMI then
@@ -242,10 +242,10 @@
       Calc_Dividers
         (Clock                   => Clock,
          Display                 => Port_Cfg.Display,
-         DKL_Refclkin_Ctl        => DKL_Refclkin_Ctl,
-         DKL_Clktop2_Coreclkctl1 => DKL_Clktop2_Coreclkctl1,
-         DKL_Clktop2_HSClkCtl    => DKL_Clktop2_HSClkCtl,
-         DCO_Khz                 => DCO_Khz,
+         DKL_RefClkin_Ctl        => DKL_RefClkin_Ctl,
+         DKL_ClkTop2_CoreClkCtl1 => DKL_ClkTop2_CoreClkCtl1,
+         DKL_ClkTop2_HSClkCtl    => DKL_ClkTop2_HSClkCtl,
+         DCO_KHz                 => DCO_KHz,
          Success                 => Success);
 
       if not Success then
@@ -263,24 +263,24 @@
 
       declare
          Tmp : Int64;
-         Refclk : Power_And_Clocks.Refclk_Range;
-         Refclk_Khz : Power_And_Clocks.Refclk_Range_KHz;
+         RefClk : Power_And_Clocks.RefClk_Range;
+         RefClk_Khz : Power_And_Clocks.RefClk_Range_KHz;
          FeedFwGain : Word32;
          M1Div : constant := 2;
          M2Div_Int, M2Div_Rem: Int64;
          M2Div_Frac : Word32;
          TDC_Target : Word32;
          Prop_Coeff, Int_Coeff : Word32;
-         IRef_Ndiv, Iref_Itrim : Word32;
+         Iref_Ndiv, Iref_Itrim : Word32;
       begin
-         Power_And_Clocks.Get_Refclk (Refclk);
-         Refclk_Khz := Power_And_Clocks.Refclk_Range_KHz (Refclk / 1_000);
-         M2Div_Int := Int64(DCO_Khz / (Refclk_Khz * M1Div));
-         M2Div_Rem := Int64(DCO_Khz rem (Refclk_Khz * M1Div));
+         Power_And_Clocks.Get_RefClk (RefClk);
+         RefClk_Khz := Power_And_Clocks.RefClk_Range_KHz (RefClk / 1_000);
+         M2Div_Int := Int64(DCO_KHz / (RefClk_Khz * M1Div));
+         M2Div_Rem := Int64(DCO_KHz rem (RefClk_Khz * M1Div));
          Tmp := M2Div_Rem * 2 ** 22;
-         M2Div_Frac := Word32 (Tmp / Int64(Refclk_Khz * M1Div));
+         M2Div_Frac := Word32 (Tmp / Int64(RefClk_Khz * M1Div));
 
-         case Refclk is
+         case RefClk is
             when 24_000_000 =>
                Iref_Ndiv := 1;
                Iref_Itrim := 25;
@@ -294,15 +294,15 @@
 
          -- Real number math converted to fixed point
          -- see note in i915 about these calculations
-         TDC_Target := Word32 (2 * 1_000 * 100_000 * 10 / (132 * Refclk_Khz) + 5) / 10;
+         TDC_Target := Word32 (2 * 1_000 * 100_000 * 10 / (132 * RefClk_Khz) + 5) / 10;
 
          if M2Div_Rem > 0 then
-            FeedFwGain := (M1Div * 1_000_000 * 100) / (Word32 (DCO_Khz) * 3 / 10);
+            FeedFwGain := (M1Div * 1_000_000 * 100) / (Word32 (DCO_KHz) * 3 / 10);
          else
             FeedFwGain := 0;
          end if;
 
-         if DCO_Khz >= 9_000_000 then
+         if DCO_KHz >= 9_000_000 then
             Prop_Coeff := 5;
             Int_Coeff := 10;
          else
@@ -316,19 +316,19 @@
          Registers.Unset_And_Set_Mask
            (Register   => PLL_Regs (PLL).DKL_REFCLKIN_CTL,
             Mask_Unset => DKL_REFCLKIN_CTL_OD_2_MUX_MASK,
-            Mask_Set   => DKL_Refclkin_Ctl);
+            Mask_Set   => DKL_RefClkin_Ctl);
 
          Registers.Unset_And_Set_Mask
            (Register   => PLL_Regs (PLL).DKL_CLKTOP2_CORECLKCTL1,
             Mask_Unset => DKL_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK,
-            Mask_Set   => DKL_Clktop2_Coreclkctl1);
+            Mask_Set   => DKL_ClkTop2_CoreClkCtl1);
 
          Registers.Unset_And_Set_Mask
            (Register   => PLL_Regs (PLL).DKL_CLKTOP2_HSCLKCTL,
             Mask_Unset => DKL_CLKTOP2_HSCLKCTL_MASK,
-            Mask_Set   => DKL_CLKTOP2_hsclkctl);
+            Mask_Set   => DKL_ClkTop2_HSClkCtl);
 
-         Registers.Unset_And_Set_mask
+         Registers.Unset_And_Set_Mask
            (Register   => PLL_Regs (PLL).DKL_PLL_DIV0,
             Mask_Unset => DKL_PLL_DIV0_MASK,
             Mask_Set   => Shift_Left (Int_Coeff, 16) or
diff --git a/common/tigerlake/hw-gfx-gma-power_and_clocks.adb b/common/tigerlake/hw-gfx-gma-power_and_clocks.adb
index 3425053..bbbbd6f 100644
--- a/common/tigerlake/hw-gfx-gma-power_and_clocks.adb
+++ b/common/tigerlake/hw-gfx-gma-power_and_clocks.adb
@@ -362,7 +362,7 @@
             when Port_Domain'Range => Any_Port_Is (To_GPU_Port (PD)));
    end Need_PD;
 
-   procedure Get_RefClk (Refclk : out Refclk_Range)
+   procedure Get_RefClk (RefClk : out RefClk_Range)
    is
       DSSM : Word32;
       DSSM_REFERENCE_FREQUENCY_MASK    : constant := 16#e000_0000#;
@@ -371,13 +371,13 @@
       DSSM_REFERENCE_FREQUENCY_38_4MHZ : constant := 16#4000_0000#;
    begin
       Registers.Read (Registers.DSSM, DSSM);
-      Refclk :=
+      RefClk :=
         (case DSSM and DSSM_REFERENCE_FREQUENCY_MASK is
          when DSSM_REFERENCE_FREQUENCY_24MHZ   => 24_000_000,
          when DSSM_REFERENCE_FREQUENCY_19_2MHZ => 19_200_000,
          when DSSM_REFERENCE_FREQUENCY_38_4MHZ => 38_400_000,
          when others                           => 24_000_000);
-   end Get_Refclk;
+   end Get_RefClk;
 
    procedure Get_RawClk (Rawclk : out Frequency_Type)
    is
@@ -397,11 +397,11 @@
 
    procedure Get_Max_CDClk (CDClk : out CDClk_Range)
    is
-      Refclk_Freq : Refclk_Range;
+      RefClk_Freq : RefClk_Range;
    begin
-      Get_Refclk (Refclk_Freq);
+      Get_RefClk (RefClk_Freq);
       CDClk :=
-        (case Refclk_Freq is
+        (case RefClk_Freq is
          when 24_000_000 => 648_000_000,
          when others     => 652_800_000);
    end Get_Max_CDClk;
@@ -412,11 +412,11 @@
    with
       Post => Normalized >= 172_800_000
    is
-      Refclk_Freq : Refclk_Range;
+      RefClk_Freq : RefClk_Range;
    begin
-      Get_Refclk (Refclk_Freq);
+      Get_RefClk (RefClk_Freq);
       Normalized :=
-        (case Refclk_Freq is
+        (case RefClk_Freq is
          when 19_200_000 | 38_400_000 =>
             (if    CDClk <= 172_800_000 then 172_800_000
              elsif CDClk <= 192_000_000 then 192_000_000
@@ -459,7 +459,7 @@
          end case;
       end Ratio_For_19_2_MHz;
 
-      function Ratio_For_24_MHz (CDCLk : CDClk_Range) return PLL_Ratio_Range is
+      function Ratio_For_24_MHz (CDClk : CDClk_Range) return PLL_Ratio_Range is
       begin
          case CDClk is
             when 180_800_000 => return 15;
@@ -484,14 +484,14 @@
       CD2X : Word32;
       PLL_Ratio : PLL_Ratio_Range;
       CDClk : CDClk_Range;
-      Refclk_Freq : Refclk_Range;
+      RefClk_Freq : RefClk_Range;
       VCO : Pos64;
    begin
       pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
 
       Normalize_CDClk (CDClk_Range'Min (CDClk_In, Config.Max_CDClk), CDClk);
-      Get_Refclk (Refclk_Freq);
-      PLL_Ratio := (case Refclk_Freq is
+      Get_RefClk (RefClk_Freq);
+      PLL_Ratio := (case RefClk_Freq is
          when 19_200_000 => Ratio_For_19_2_MHz (CDClk),
          when 38_400_000 => Ratio_For_19_2_MHz (CDClk) / 2,
          when 24_000_000 => Ratio_For_24_MHz (CDClk),
@@ -499,12 +499,12 @@
 
       if PLL_Ratio = 0 then
          pragma Debug (Debug.Put_Line
-                       ("ERROR: Invalid Refclk frequency, bad hardware?"));
+                       ("ERROR: Invalid RefClk frequency, bad hardware?"));
          return;
       end if;
 
       PCode.Mailbox_Request
-        (Mbox       => TGL_PCODE_CDCLK_CONTROL,
+        (MBox       => TGL_PCODE_CDCLK_CONTROL,
          Command    => TGL_CDCLK_PREPARE_FOR_CHANGE,
          Reply_Mask => TGL_CDCLK_READY_FOR_CHANGE,
          Wait_Ready => True,
@@ -539,7 +539,7 @@
          return;
       end if;
 
-      VCO := (Refclk_Freq / 1_000) * Pos64 (PLL_Ratio);
+      VCO := (RefClk_Freq / 1_000) * Pos64 (PLL_Ratio);
       CD2X :=
          (case (Div_Round_Closest (VCO, CDClk / 1_000)) is
           when 2 => CDCLK_CD2X_DIV_SEL_1,
@@ -616,7 +616,7 @@
          return;
       end if;
 
-      case (Result and 16#f#) is
+      case Result and 16#f# is
          when 0 => Module_Type := DDR4;
          when 1 => Module_Type := DDR5;
          when 2 => Module_Type := LPDDR5;
@@ -818,11 +818,11 @@
       pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
 
       for PD in reverse Dynamic_Domain loop
-        if (Need_PD (PD, Old_Configs) or Need_PD (PD, Tmp_Configs)) and
-           not Need_PD (PD, New_Configs)
-        then
-           PD_Off (PD);
-        end if;
+         if (Need_PD (PD, Old_Configs) or Need_PD (PD, Tmp_Configs)) and
+            not Need_PD (PD, New_Configs)
+         then
+            PD_Off (PD);
+         end if;
       end loop;
    end Power_Down;
 
diff --git a/common/tigerlake/hw-gfx-gma-power_and_clocks.ads b/common/tigerlake/hw-gfx-gma-power_and_clocks.ads
index 881d0f1..c1ab521 100644
--- a/common/tigerlake/hw-gfx-gma-power_and_clocks.ads
+++ b/common/tigerlake/hw-gfx-gma-power_and_clocks.ads
@@ -16,9 +16,9 @@
 
 private package HW.GFX.GMA.Power_And_Clocks is
 
-   subtype Refclk_Range is Frequency_Type range 19_200_000 .. 38_400_000;
-   subtype Refclk_Range_KHz is Pos64
-      range (Refclk_Range'First / 1000) .. (Refclk_Range'Last / 1000);
+   subtype RefClk_Range is Frequency_Type range 19_200_000 .. 38_400_000;
+   subtype RefClk_Range_KHz is Pos64
+      range (RefClk_Range'First / 1000) .. (RefClk_Range'Last / 1000);
 
    procedure Pre_All_Off;
    procedure Post_All_Off;
@@ -41,6 +41,6 @@
    procedure Power_Up (Old_Configs, New_Configs : Pipe_Configs);
    procedure Power_Down (Old_Configs, Tmp_Configs, New_Configs : Pipe_Configs);
 
-   procedure Get_Refclk (Refclk : out Refclk_Range);
+   procedure Get_RefClk (RefClk : out RefClk_Range);
 
 end HW.GFX.GMA.Power_And_Clocks;
diff --git a/gfxtest/hw-gfx-gma-gfx_test.adb b/gfxtest/hw-gfx-gma-gfx_test.adb
index c6a3019..5042f77 100644
--- a/gfxtest/hw-gfx-gma-gfx_test.adb
+++ b/gfxtest/hw-gfx-gma-gfx_test.adb
@@ -484,7 +484,7 @@
          else
             CI.Size := Cursor_Size'Val
               ((Cursor_Size'Pos (CI.Size) + 1 + Rand (Gen) mod 2) mod 3);
-	    if Cursor_Width (CI.Size) > Pipes (P).Framebuffer.Width or
+            if Cursor_Width (CI.Size) > Pipes (P).Framebuffer.Width or
                Cursor_Width (CI.Size) > Pipes (P).Framebuffer.Height
             then
                CI.Size := Cursor_64x64;
@@ -527,14 +527,14 @@
                C.Center_X := C.Center_X + CI.X_Velo / 100;
                C.Center_Y := C.Center_Y + CI.Y_Velo / 100;
                if C.Center_X not in 0 .. Width - 1 then
-                 C.Center_X := Int32'Max (0, Int32'Min (Width, C.Center_X));
-                 CI.X_Velo := -CI.X_Velo;
-                 Update := True;
+                  C.Center_X := Int32'Max (0, Int32'Min (Width, C.Center_X));
+                  CI.X_Velo := -CI.X_Velo;
+                  Update := True;
                end if;
                if C.Center_Y not in 0 .. Height - 1 then
-                 C.Center_Y := Int32'Max (0, Int32'Min (Height, C.Center_Y));
-                 CI.Y_Velo := -CI.Y_Velo;
-                 Update := True;
+                  C.Center_Y := Int32'Max (0, Int32'Min (Height, C.Center_Y));
+                  CI.Y_Velo := -CI.Y_Velo;
+                  Update := True;
                end if;
                if Update then
                   Select_New_Cursor (Pipe, C, CI);