commit abe3de257c482ebeb90cf9f93d69ae744c60f9a6
author Nico Huber <nico.huber@secunet.com> Thu Oct 20 15:03:46 2016 +0200
committer Nico Huber <nico.h@gmx.de> Sat Oct 29 01:23:09 2016 +0200
tree 6181e69238840704e1370e005ddca3ee7e1f1d4d
parent f54d0962018b0443973f84e525e0d112ce956800

gma dp aux: Program 2x bit clock divider

This setting exists for any platform before Skylake. Some have sane
defaults after reset, some don't. So we always set the correct divisor.

This makes external DP output work with coreboot on Ivy Bridge.

Change-Id: I91d8030a985cc35c7cf826c0276753137b5d6b77
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17072
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

common/hw-gfx-gma-dp_aux_request.adb

diff --git a/common/hw-gfx-gma-dp_aux_request.adb b/common/hw-gfx-gma-dp_aux_request.adb
index 133b40c..22064ab 100644
--- a/common/hw-gfx-gma-dp_aux_request.adb
+++ b/common/hw-gfx-gma-dp_aux_request.adb
@@ -40,7 +40,7 @@
    DP_AUX_CTL_PRECHARGE_TIME_MASK   : constant :=   15 * 2 ** 16;
    DP_AUX_CTL_PRECHARGE_TIME_SHIFT  : constant :=        2 ** 16;
    DP_AUX_CTL_2X_BIT_CLOCK_DIV_MASK : constant := 2047 * 2 **  0;
-   -- TODO: 2x bit clock divider should be programmed once before any training.
+   -- TODO: HSW/BDW with LPT-H might need a workaround for the 2x bit clock.
 
    subtype DP_AUX_CTL_MESSAGE_SIZE_T is Natural range 1 .. 20;
    function DP_AUX_CTL_MESSAGE_SIZE
@@ -224,6 +224,17 @@
          end if;
       end Read_Data_Reg;
 
+      DP_AUX_CTL_2x_Clock_Mask : constant :=
+        (if Config.Has_PCH_Aux_Channels then
+            DP_AUX_CTL_2X_BIT_CLOCK_DIV_MASK else 0);
+      DP_AUX_CTL_2x_Clock : constant Word32 :=
+        (if Config.Has_PCH_Aux_Channels then
+           (if Port = DP_A then
+               Word32 ((Config.Default_CDClk_Freq + 1_000_000) / 2_000_000)
+            else
+               Word32 ((Config.Default_RawClk_Freq + 1_000_000) / 2_000_000))
+         else 0);
+
       Busy : Boolean;
       Status : Word32;
    begin
@@ -258,13 +269,15 @@
            (Register    => AUX_CH (Port).CTL,
             Mask_Unset  => DP_AUX_CTL_INTERRUPT_ON_DONE or
                            DP_AUX_CTL_TIME_OUT_TIMER_MASK or
-                           DP_AUX_CTL_MESSAGE_SIZE_MASK,
+                           DP_AUX_CTL_MESSAGE_SIZE_MASK or
+                           DP_AUX_CTL_2x_Clock_Mask,
             Mask_Set    => DP_AUX_CTL_SEND_BUSY or          -- starts transfer
                            DP_AUX_CTL_DONE or               -- clears the status
                            DP_AUX_CTL_TIME_OUT_ERROR or     -- clears the status
                            DP_AUX_CTL_RECEIVE_ERROR or      -- clears the status
                            DP_AUX_CTL_TIME_OUT_TIMER_600US or
-                           DP_AUX_CTL_MESSAGE_SIZE (Request_Length));
+                           DP_AUX_CTL_MESSAGE_SIZE (Request_Length) or
+                           DP_AUX_CTL_2x_Clock);
 
          Registers.Wait_Unset_Mask
            (Register => AUX_CH (Port).CTL,