)]}'
{
  "commit": "94fb916ea6ab1e6ae901e5ab264d4e1e8e8b5f2b",
  "tree": "e0d6052ceefda16e21c60af73c707fbcb41e4b1e",
  "parents": [
    "f80c3e4e103dcd717825158d274ffcbae648ff0b"
  ],
  "author": {
    "name": "Nico Huber",
    "email": "nico.huber@secunet.com",
    "time": "Fri May 10 13:44:11 2019 +0200"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Sat Jul 20 16:34:01 2019 +0000"
  },
  "message": "dp training: Write correct training data when switching patterns\n\nApparently this was wrong all the time. When switching the training\npattern, i.e. writes to DPCD+0x102, we also have to write the current\nsignal levels to subsequent offsets. We always wrote 0s in this case,\neven if we already negotiated higher values during the clock-recovery\nphase. Obviously, this results in havoc if the sink takes the 0s\nserious.\n\nTEST\u003dRun a few hundred training rounds with a Terra 2462W display.\n     This display almost always requested an increase of the voltage\n     swing to level 1. Trainings where it recovered the clock with\n     level 0 always succeeded, while trainings with level 1 almost\n     always lost synchronization at the start of channel equalization.\n     With the patch applied, all trainings succeeded.\n\nChange-Id: I6ae2f9aaec0b042e8dee6e8b0099ea62c82f611b\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/libgfxinit/+/32732\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "079d49c242fbc5dddb17d3b7c6f1c6d9009aa4ec",
      "old_mode": 33188,
      "old_path": "common/hw-gfx-dp_training.adb",
      "new_id": "d613d85fd2ea896de00e7c94ae63d57b0f73e7dc",
      "new_mode": 33188,
      "new_path": "common/hw-gfx-dp_training.adb"
    }
  ]
}