diff --git a/common/ironlake/Makefile.inc b/common/ironlake/Makefile.inc
new file mode 100644
index 0000000..468bb95
--- /dev/null
+++ b/common/ironlake/Makefile.inc
@@ -0,0 +1,17 @@
+gfxinit-y += hw-gfx-gma-connectors-edp.adb
+gfxinit-y += hw-gfx-gma-connectors-edp.ads
+gfxinit-y += hw-gfx-gma-connectors-fdi.adb
+gfxinit-y += hw-gfx-gma-connectors-fdi.ads
+gfxinit-y += hw-gfx-gma-connectors.adb
+gfxinit-y += hw-gfx-gma-pch-dp.adb
+gfxinit-y += hw-gfx-gma-pch-dp.ads
+gfxinit-y += hw-gfx-gma-pch-hdmi.adb
+gfxinit-y += hw-gfx-gma-pch-hdmi.ads
+gfxinit-y += hw-gfx-gma-pch-lvds.adb
+gfxinit-y += hw-gfx-gma-pch-lvds.ads
+gfxinit-y += hw-gfx-gma-plls.adb
+gfxinit-y += hw-gfx-gma-plls.ads
+gfxinit-y += hw-gfx-gma-port_detect.adb
+gfxinit-y += hw-gfx-gma-power_and_clocks.ads
+gfxinit-y += hw-gfx-gma-power_and_clocks_ironlake.adb
+gfxinit-y += hw-gfx-gma-power_and_clocks_ironlake.ads
diff --git a/common/ironlake/hw-gfx-gma-connectors-edp.adb b/common/ironlake/hw-gfx-gma-connectors-edp.adb
new file mode 100644
index 0000000..96930f3
--- /dev/null
+++ b/common/ironlake/hw-gfx-gma-connectors-edp.adb
@@ -0,0 +1,297 @@
+--
+-- Copyright (C) 2015-2016 secunet Security Networks AG
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; version 2 of the License.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+
+with HW.Time;
+with HW.GFX.DP_Training;
+with HW.GFX.GMA.DP_Info;
+with HW.GFX.GMA.DP_Aux_Ch;
+with HW.GFX.GMA.Registers;
+
+with HW.Debug;
+with GNAT.Source_Info;
+
+package body HW.GFX.GMA.Connectors.EDP
+is
+
+   DP_CTL_DISPLAYPORT_ENABLE        : constant :=  1 * 2 ** 31;
+   DP_CTL_PIPE_SELECT_MASK          : constant :=  3 * 2 ** 29;
+   DP_CTL_PIPE_SELECT_SHIFT         : constant :=           29;
+   DP_CTL_VSWING_EMPH_SET_MASK      : constant := 63 * 2 ** 22;
+   DP_CTL_PORT_WIDTH_MASK           : constant :=  7 * 2 ** 19;
+   DP_CTL_PORT_WIDTH_1_LANE         : constant :=  0 * 2 ** 19;
+   DP_CTL_PORT_WIDTH_2_LANES        : constant :=  1 * 2 ** 19;
+   DP_CTL_PORT_WIDTH_4_LANES        : constant :=  3 * 2 ** 19;
+   DP_CTL_ENHANCED_FRAMING_ENABLE   : constant :=  1 * 2 ** 18;
+   DP_CTL_PLL_FREQUENCY_MASK        : constant :=  3 * 2 ** 16;
+   DP_CTL_PLL_FREQUENCY_270         : constant :=  0 * 2 ** 16;
+   DP_CTL_PLL_FREQUENCY_162         : constant :=  1 * 2 ** 16;
+   DP_CTL_PORT_REVERSAL             : constant :=  1 * 2 ** 15;
+   DP_CTL_PLL_ENABLE                : constant :=  1 * 2 ** 14;
+   DP_CTL_LINK_TRAIN_MASK           : constant :=  3 * 2 **  8;
+   DP_CTL_LINK_TRAIN_PAT1           : constant :=  0 * 2 **  8;
+   DP_CTL_LINK_TRAIN_PAT2           : constant :=  1 * 2 **  8;
+   DP_CTL_LINK_TRAIN_IDLE           : constant :=  2 * 2 **  8;
+   DP_CTL_LINK_TRAIN_NORMAL         : constant :=  3 * 2 **  8;
+   DP_CTL_ALT_SCRAMBLER_RESET       : constant :=  1 * 2 **  6;
+   DP_CTL_VSYNC_ACTIVE_HIGH         : constant :=  1 * 2 **  4;
+   DP_CTL_HSYNC_ACTIVE_HIGH         : constant :=  1 * 2 **  3;
+   DP_CTL_PORT_DETECT               : constant :=  1 * 2 **  2;
+
+   -- TODO? Values are for Ivy Bridge only
+   DP_CTL_VSWING_0_EMPH_0 : constant := 1 * 2 ** 27 + 1 * 2 ** 24 + 0 * 2 ** 22;
+   DP_CTL_VSWING_0_EMPH_1 : constant := 1 * 2 ** 27 + 2 * 2 ** 24 + 2 * 2 ** 22;
+   DP_CTL_VSWING_0_EMPH_2 : constant := 1 * 2 ** 27 + 3 * 2 ** 24 + 3 * 2 ** 22;
+   DP_CTL_VSWING_1_EMPH_0 : constant := 1 * 2 ** 27 + 4 * 2 ** 24 + 0 * 2 ** 22;
+   DP_CTL_VSWING_1_EMPH_1 : constant := 1 * 2 ** 27 + 5 * 2 ** 24 + 2 * 2 ** 22;
+   DP_CTL_VSWING_2_EMPH_0 : constant := 1 * 2 ** 27 + 6 * 2 ** 24 + 0 * 2 ** 22;
+   DP_CTL_VSWING_2_EMPH_1 : constant := 1 * 2 ** 27 + 7 * 2 ** 24 + 2 * 2 ** 22;
+
+   type DP_CTL_PORT_WIDTH_T is array (DP_Lane_Count) of Word32;
+   DP_CTL_PORT_WIDTH : constant DP_CTL_PORT_WIDTH_T :=
+      DP_CTL_PORT_WIDTH_T'
+     (DP_Lane_Count_1 => DP_CTL_PORT_WIDTH_1_LANE,
+      DP_Lane_Count_2 => DP_CTL_PORT_WIDTH_2_LANES,
+      DP_Lane_Count_4 => DP_CTL_PORT_WIDTH_4_LANES);
+
+   type DP_CTL_LINK_TRAIN_Array is array (DP_Info.Training_Pattern) of Word32;
+   DP_CTL_LINK_TRAIN : constant DP_CTL_LINK_TRAIN_Array :=
+      DP_CTL_LINK_TRAIN_Array'
+     (DP_Info.TP_1      => DP_CTL_LINK_TRAIN_PAT1,
+      DP_Info.TP_2      => DP_CTL_LINK_TRAIN_PAT2,
+      DP_Info.TP_3      => DP_CTL_LINK_TRAIN_PAT2,
+      DP_Info.TP_Idle   => DP_CTL_LINK_TRAIN_IDLE,
+      DP_Info.TP_None   => DP_CTL_LINK_TRAIN_NORMAL);
+
+   ----------------------------------------------------------------------------
+
+   procedure Pre_Training is
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      Registers.Unset_And_Set_Mask
+        (Register    => Registers.DP_CTL_A,
+         Mask_Unset  => DP_CTL_LINK_TRAIN_MASK,
+         Mask_Set    => DP_CTL_LINK_TRAIN (DP_Info.TP_1) or
+                        DP_CTL_DISPLAYPORT_ENABLE);
+   end Pre_Training;
+
+   ----------------------------------------------------------------------------
+
+   pragma Warnings (GNATprove, Off, "unused variable ""Port""",
+                    Reason => "Needed for a common interface");
+   function Max_V_Swing
+     (Port : Digital_Port)
+      return DP_Info.DP_Voltage_Swing
+   is
+   begin
+      return DP_Info.VS_Level_2;
+   end Max_V_Swing;
+
+   function Max_Pre_Emph
+     (Port        : Digital_Port;
+      Train_Set   : DP_Info.Train_Set)
+      return DP_Info.DP_Pre_Emph
+   is
+   begin
+      return
+        (case Train_Set.Voltage_Swing is
+            when DP_Info.VS_Level_0 => DP_Info.Emph_Level_2,
+            when DP_Info.VS_Level_1 |
+                 DP_Info.VS_Level_2 => DP_Info.Emph_Level_1,
+            when others             => DP_Info.Emph_Level_0);
+   end Max_Pre_Emph;
+
+   ----------------------------------------------------------------------------
+
+   pragma Warnings (GNATprove, Off, "unused variable ""Link""",
+                    Reason => "Needed for a common interface");
+   procedure Set_Training_Pattern
+     (Port     : Digital_Port;
+      Link     : DP_Link;
+      Pattern  : DP_Info.Training_Pattern)
+   is
+      use type DP_Info.Training_Pattern;
+   begin
+      if Pattern < DP_Info.TP_Idle then
+         Registers.Unset_And_Set_Mask
+           (Register    => Registers.DP_CTL_A,
+            Mask_Unset  => DP_CTL_LINK_TRAIN_MASK,
+            Mask_Set    => DP_CTL_LINK_TRAIN (Pattern));
+      else
+         -- send at least 5 idle patterns
+         Registers.Unset_And_Set_Mask
+           (Register    => Registers.DP_CTL_A,
+            Mask_Unset  => DP_CTL_LINK_TRAIN_MASK,
+            Mask_Set    => DP_CTL_LINK_TRAIN (DP_Info.TP_Idle));
+
+         -- we switch to normal frame delivery later in Post_On procedure
+      end if;
+   end Set_Training_Pattern;
+
+   procedure Set_Signal_Levels
+     (Port        : Digital_Port;
+      Link        : DP_Link;
+      Train_Set   : DP_Info.Train_Set)
+   is
+      VSwing_Emph : Word32;
+   begin
+      VSwing_Emph :=
+        (case Train_Set.Voltage_Swing is
+            when DP_Info.VS_Level_0 =>
+              (case Train_Set.Pre_Emph is
+                  when DP_Info.Emph_Level_0  => DP_CTL_VSWING_0_EMPH_0,
+                  when DP_Info.Emph_Level_1  => DP_CTL_VSWING_0_EMPH_1,
+                  when DP_Info.Emph_Level_2  => DP_CTL_VSWING_0_EMPH_2,
+                  when others                => DP_CTL_VSWING_0_EMPH_0),
+            when DP_Info.VS_Level_1 =>
+              (case Train_Set.Pre_Emph is
+                  when DP_Info.Emph_Level_0  => DP_CTL_VSWING_1_EMPH_0,
+                  when DP_Info.Emph_Level_1  => DP_CTL_VSWING_1_EMPH_1,
+                  when others                => DP_CTL_VSWING_1_EMPH_0),
+            when DP_Info.VS_Level_2 =>
+              (case Train_Set.Pre_Emph is
+                  when DP_Info.Emph_Level_0  => DP_CTL_VSWING_2_EMPH_0,
+                  when DP_Info.Emph_Level_1  => DP_CTL_VSWING_2_EMPH_1,
+                  when others                => DP_CTL_VSWING_2_EMPH_0),
+            when others                      => DP_CTL_VSWING_0_EMPH_0);
+
+      Registers.Unset_And_Set_Mask
+        (Register    => Registers.DP_CTL_A,
+         Mask_Unset  => DP_CTL_VSWING_EMPH_SET_MASK,
+         Mask_Set    => VSwing_Emph);
+   end Set_Signal_Levels;
+   pragma Warnings (GNATprove, On, "unused variable ""Port""");
+   pragma Warnings (GNATprove, On, "unused variable ""Link""");
+
+   ----------------------------------------------------------------------------
+
+   procedure Pre_On
+     (Port_Cfg    : Port_Config;
+      Pipe_Hint   : Word32)
+   is
+      DP_CTL_Set : Word32;
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      DP_CTL_Set :=
+         Shift_Left (Pipe_Hint, DP_CTL_PIPE_SELECT_SHIFT) or
+         DP_CTL_PORT_WIDTH (Port_Cfg.DP.Lane_Count);
+
+      if Port_Cfg.DP.Enhanced_Framing then
+         DP_CTL_Set := DP_CTL_Set or DP_CTL_ENHANCED_FRAMING_ENABLE;
+      end if;
+
+      case Port_Cfg.DP.Bandwidth is
+         when DP_Bandwidth_1_62 =>
+            DP_CTL_Set := DP_CTL_Set or DP_CTL_PLL_FREQUENCY_162;
+         when DP_Bandwidth_2_7 =>
+            DP_CTL_Set := DP_CTL_Set or DP_CTL_PLL_FREQUENCY_270;
+         when others =>
+            null;
+      end case;
+
+      if Port_Cfg.Mode.V_Sync_Active_High then
+         DP_CTL_Set := DP_CTL_Set or DP_CTL_VSYNC_ACTIVE_HIGH;
+      end if;
+      if Port_Cfg.Mode.H_Sync_Active_High then
+         DP_CTL_Set := DP_CTL_Set or DP_CTL_HSYNC_ACTIVE_HIGH;
+      end if;
+
+      Registers.Write
+        (Register => Registers.DP_CTL_A,
+         Value    => DP_CTL_Set);
+
+      Registers.Write
+        (Register => Registers.DP_CTL_A,
+         Value    => DP_CTL_PLL_ENABLE or DP_CTL_Set);
+      Registers.Posting_Read (Registers.DP_CTL_A);
+      Time.U_Delay (20);
+   end Pre_On;
+
+   ----------------------------------------------------------------------------
+
+   procedure Post_On
+     (Link     : in     DP_Link;
+      Success  :    out Boolean)
+   is
+      pragma Warnings (GNATprove, Off, "unused variable ""Port""",
+                       Reason => "Needed for a common interface");
+      function To_DP (Port : Digital_Port) return DP_Port
+      is
+      begin
+         return DP_A;
+      end To_DP;
+      pragma Warnings (GNATprove, On, "unused variable ""Port""");
+      package Training is new DP_Training
+        (TPS3_Supported    => False,
+         T                 => Digital_Port,
+         Aux_T             => DP_Port,
+         Aux_Ch            => DP_Aux_Ch,
+         DP_Info           => DP_Info,
+         To_Aux            => To_DP,
+         Max_V_Swing       => Max_V_Swing,
+         Max_Pre_Emph      => Max_Pre_Emph,
+         Set_Pattern       => Set_Training_Pattern,
+         Set_Signal_Levels => Set_Signal_Levels,
+         Off               => Off);
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      Training.Train_DP
+        (Port        => DIGI_A,
+         Link        => Link,
+         Success     => Success);
+
+      if Success then
+         Registers.Unset_And_Set_Mask
+           (Register    => Registers.DP_CTL_A,
+            Mask_Unset  => DP_CTL_LINK_TRAIN_MASK,
+            Mask_Set    => DP_CTL_LINK_TRAIN_NORMAL);
+      end if;
+   end Post_On;
+
+   ----------------------------------------------------------------------------
+
+   procedure Off (Port : Digital_Port)
+   is
+      Enabled : Boolean;
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      Registers.Unset_And_Set_Mask
+        (Register    => Registers.DP_CTL_A,
+         Mask_Unset  => DP_CTL_LINK_TRAIN_MASK,
+         Mask_Set    => DP_CTL_LINK_TRAIN_IDLE);
+      Registers.Posting_Read (Registers.DP_CTL_A);
+
+      Registers.Unset_Mask
+        (Register => Registers.DP_CTL_A,
+         Mask     => DP_CTL_DISPLAYPORT_ENABLE);
+      -- implicit Posting_Read below
+
+      Registers.Is_Set_Mask
+        (Register => Registers.DP_CTL_A,
+         Mask     => DP_CTL_PLL_ENABLE,
+         Result   => Enabled);
+
+      Registers.Write
+        (Register => Registers.DP_CTL_A,
+         Value    => 16#0000_0000#);
+      Registers.Posting_Read (Registers.DP_CTL_A);
+
+      if Enabled then
+         Time.U_Delay (20);
+      end if;
+   end Off;
+
+end HW.GFX.GMA.Connectors.EDP;
diff --git a/common/ironlake/hw-gfx-gma-connectors-edp.ads b/common/ironlake/hw-gfx-gma-connectors-edp.ads
new file mode 100644
index 0000000..516e093
--- /dev/null
+++ b/common/ironlake/hw-gfx-gma-connectors-edp.ads
@@ -0,0 +1,32 @@
+--
+-- Copyright (C) 2015-2016 secunet Security Networks AG
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; version 2 of the License.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+
+private package HW.GFX.GMA.Connectors.EDP
+is
+
+   procedure Pre_On
+     (Port_Cfg    : Port_Config;
+      Pipe_Hint   : Word32);
+
+   procedure Post_On
+     (Link     : in     DP_Link;
+      Success  :    out Boolean);
+
+   pragma Warnings (GNATprove, Off, "unused variable ""Port""",
+                    Reason => "Needed for a common interface");
+   procedure Off (Port : Digital_Port);
+   pragma Warnings (GNATprove, On, "unused variable ""Port""");
+
+   procedure Pre_Training;
+
+end HW.GFX.GMA.Connectors.EDP;
diff --git a/common/ironlake/hw-gfx-gma-connectors-fdi.adb b/common/ironlake/hw-gfx-gma-connectors-fdi.adb
new file mode 100644
index 0000000..2d295f7
--- /dev/null
+++ b/common/ironlake/hw-gfx-gma-connectors-fdi.adb
@@ -0,0 +1,342 @@
+--
+-- Copyright (C) 2016 secunet Security Networks AG
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; version 2 of the License.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+
+with HW.Time;
+with HW.GFX.GMA.Config;
+with HW.GFX.GMA.PCH.FDI;
+with HW.GFX.GMA.Registers;
+
+with HW.Debug;
+with GNAT.Source_Info;
+
+package body HW.GFX.GMA.Connectors.FDI
+is
+
+   PCH_FDI_CHICKEN_B_AND_C             : constant :=      1 * 2 ** 12;
+
+   type TX_CTL_Regs is array (GPU_FDI_Port) of Registers.Registers_Index;
+   TX_CTL : constant TX_CTL_Regs :=
+     (DIGI_B => Registers.FDI_TX_CTL_A,
+      DIGI_C => Registers.FDI_TX_CTL_B,
+      DIGI_D => Registers.FDI_TX_CTL_C);
+
+   FDI_TX_CTL_FDI_TX_ENABLE            : constant :=      1 * 2 ** 31;
+   FDI_TX_CTL_VP_MASK                  : constant := 16#3f# * 2 ** 22;
+   FDI_TX_CTL_PORT_WIDTH_SEL_SHIFT     : constant :=               19;
+   FDI_TX_CTL_ENHANCED_FRAMING_ENABLE  : constant :=      1 * 2 ** 18;
+   FDI_TX_CTL_FDI_PLL_ENABLE           : constant :=      1 * 2 ** 14;
+   FDI_TX_CTL_COMPOSITE_SYNC_SELECT    : constant :=      1 * 2 ** 11;
+   FDI_TX_CTL_AUTO_TRAIN_ENABLE        : constant :=      1 * 2 ** 10;
+   FDI_TX_CTL_AUTO_TRAIN_DONE          : constant :=      1 * 2 **  1;
+
+   TP_SHIFT : constant := (if Config.CPU <= Sandybridge then 28 else 8);
+   FDI_TX_CTL_TRAINING_PATTERN_MASK    : constant := 3 * 2 ** TP_SHIFT;
+   FDI_TX_CTL_TRAINING_PATTERN_1       : constant := 0 * 2 ** TP_SHIFT;
+   FDI_TX_CTL_TRAINING_PATTERN_2       : constant := 1 * 2 ** TP_SHIFT;
+   FDI_TX_CTL_TRAINING_PATTERN_IDLE    : constant := 2 * 2 ** TP_SHIFT;
+   FDI_TX_CTL_TRAINING_PATTERN_NORMAL  : constant := 3 * 2 ** TP_SHIFT;
+
+   subtype FDI_TX_CTL_VP_T is Natural range 0 .. 3;
+   type Vswing_Preemph_Values is array (FDI_TX_CTL_VP_T) of Word32;
+   FDI_TX_CTL_VSWING_PREEMPH : constant Vswing_Preemph_Values :=
+     (0 => 16#00# * 2 ** 22,
+      1 => 16#3a# * 2 ** 22,
+      2 => 16#39# * 2 ** 22,
+      3 => 16#38# * 2 ** 22);
+
+   function FDI_TX_CTL_PORT_WIDTH_SEL (Lane_Count : DP_Lane_Count) return Word32
+   is
+   begin
+      return Shift_Left
+        (Word32 (Lane_Count_As_Integer (Lane_Count)) - 1,
+         FDI_TX_CTL_PORT_WIDTH_SEL_SHIFT);
+   end FDI_TX_CTL_PORT_WIDTH_SEL;
+
+   ----------------------------------------------------------------------------
+
+   --
+   -- This is usually used with Ivy Bridge.
+   --
+   procedure Auto_Training
+     (Port_Cfg : in     Port_Config;
+      Success  :    out Boolean)
+   with
+      Pre => Port_Cfg.Port in GPU_FDI_Port
+   is
+      PCH_FDI_Port : constant PCH.FDI_Port_Type := PCH_FDIs (Port_Cfg.Port);
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      -- try each preemph/voltage pair twice
+      for VP2 in Natural range 0 .. FDI_TX_CTL_VP_T'Last * 2 + 1
+      loop
+         Registers.Unset_And_Set_Mask
+           (Register    => TX_CTL (Port_Cfg.Port),
+            Mask_Unset  => FDI_TX_CTL_VP_MASK or
+                           FDI_TX_CTL_TRAINING_PATTERN_MASK,
+            Mask_Set    => FDI_TX_CTL_FDI_TX_ENABLE or
+                           FDI_TX_CTL_VSWING_PREEMPH (VP2 / 2) or
+                           FDI_TX_CTL_AUTO_TRAIN_ENABLE or
+                           FDI_TX_CTL_TRAINING_PATTERN_1);
+         Registers.Posting_Read (TX_CTL (Port_Cfg.Port));
+
+         PCH.FDI.Auto_Train (PCH_FDI_Port);
+
+         -- read at least twice
+         for I in 0 .. 3 loop
+            Registers.Is_Set_Mask
+              (Register => TX_CTL (Port_Cfg.Port),
+               Mask     => FDI_TX_CTL_AUTO_TRAIN_DONE,
+               Result   => Success);
+            exit when Success or I = 3;
+            Time.U_Delay (1);
+         end loop;
+         exit when Success;
+
+         Registers.Unset_And_Set_Mask
+           (Register    => TX_CTL (Port_Cfg.Port),
+            Mask_Unset  => FDI_TX_CTL_FDI_TX_ENABLE or
+                           FDI_TX_CTL_AUTO_TRAIN_ENABLE or
+                           FDI_TX_CTL_TRAINING_PATTERN_MASK,
+            Mask_Set    => FDI_TX_CTL_TRAINING_PATTERN_1);
+
+         PCH.FDI.Off (PCH_FDI_Port, PCH.FDI.Rx_Off);
+      end loop;
+
+      if Success then
+         PCH.FDI.Enable_EC (PCH_FDI_Port);
+      else
+         Registers.Unset_Mask
+           (Register => TX_CTL (Port_Cfg.Port),
+            Mask     => FDI_TX_CTL_FDI_PLL_ENABLE);
+
+         PCH.FDI.Off (PCH_FDI_Port, PCH.FDI.Clock_Off);
+      end if;
+   end Auto_Training;
+
+   ----------------------------------------------------------------------------
+
+   --
+   -- Used with Sandy Bridge (should work with Ivy Bridge too)
+   --
+   procedure Full_Training
+     (Port_Cfg : in     Port_Config;
+      Success  :    out Boolean)
+   with
+      Pre => Port_Cfg.Port in GPU_FDI_Port
+   is
+      PCH_FDI_Port : constant PCH.FDI_Port_Type := PCH_FDIs (Port_Cfg.Port);
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      -- try each preemph/voltage pair twice
+      for VP2 in Natural range 0 .. FDI_TX_CTL_VP_T'Last * 2 + 1
+      loop
+         Registers.Unset_And_Set_Mask
+           (Register    => TX_CTL (Port_Cfg.Port),
+            Mask_Unset  => FDI_TX_CTL_VP_MASK or
+                           FDI_TX_CTL_TRAINING_PATTERN_MASK,
+            Mask_Set    => FDI_TX_CTL_FDI_TX_ENABLE or
+                           FDI_TX_CTL_VSWING_PREEMPH (VP2 / 2) or
+                           FDI_TX_CTL_TRAINING_PATTERN_1);
+         Registers.Posting_Read (TX_CTL (Port_Cfg.Port));
+
+         PCH.FDI.Train (PCH_FDI_Port, PCH.FDI.TP_1, Success);
+
+         if Success then
+            Registers.Unset_And_Set_Mask
+              (Register    => TX_CTL (Port_Cfg.Port),
+               Mask_Unset  => FDI_TX_CTL_TRAINING_PATTERN_MASK,
+               Mask_Set    => FDI_TX_CTL_TRAINING_PATTERN_2);
+            Registers.Posting_Read (TX_CTL (Port_Cfg.Port));
+
+            PCH.FDI.Train (PCH_FDI_Port, PCH.FDI.TP_2, Success);
+         end if;
+         exit when Success;
+
+         Registers.Unset_And_Set_Mask
+           (Register    => TX_CTL (Port_Cfg.Port),
+            Mask_Unset  => FDI_TX_CTL_FDI_TX_ENABLE or
+                           FDI_TX_CTL_TRAINING_PATTERN_MASK,
+            Mask_Set    => FDI_TX_CTL_TRAINING_PATTERN_1);
+
+         PCH.FDI.Off (PCH_FDI_Port, PCH.FDI.Rx_Off);
+      end loop;
+
+      if Success then
+         Registers.Unset_And_Set_Mask
+           (Register    => TX_CTL (Port_Cfg.Port),
+            Mask_Unset  => FDI_TX_CTL_TRAINING_PATTERN_MASK,
+            Mask_Set    => FDI_TX_CTL_TRAINING_PATTERN_NORMAL);
+         Registers.Posting_Read (TX_CTL (Port_Cfg.Port));
+
+         PCH.FDI.Train (PCH_FDI_Port, PCH.FDI.TP_None, Success);
+      else
+         Registers.Unset_Mask
+           (Register => TX_CTL (Port_Cfg.Port),
+            Mask     => FDI_TX_CTL_FDI_PLL_ENABLE);
+
+         PCH.FDI.Off (PCH_FDI_Port, PCH.FDI.Clock_Off);
+      end if;
+   end Full_Training;
+
+   ----------------------------------------------------------------------------
+
+   --
+   -- Used with original Ironlake (Nehalem CPU)
+   --
+   -- This is close to what Linux' i915 does. A comment in i915_reg.h
+   -- states that it uses only the lowest voltage / pre-emphasis levels
+   -- which is why we leave them at zero here and don't try different
+   -- values.
+   --
+   -- It's actually not clear from i915's code if the values really are
+   -- at zero or if it's just reusing what the Video BIOS set. Some code
+   -- in coreboot sets them to zero explicitly.
+   --
+   procedure Simple_Training
+     (Port_Cfg : in     Port_Config;
+      Success  :    out Boolean)
+   with
+      Pre => Port_Cfg.Port in GPU_FDI_Port
+   is
+      PCH_FDI_Port : constant PCH.FDI_Port_Type := PCH_FDIs (Port_Cfg.Port);
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      Registers.Unset_And_Set_Mask
+        (Register    => TX_CTL (Port_Cfg.Port),
+         Mask_Unset  => FDI_TX_CTL_TRAINING_PATTERN_MASK,
+         Mask_Set    => FDI_TX_CTL_FDI_TX_ENABLE or
+                        FDI_TX_CTL_TRAINING_PATTERN_1);
+      Registers.Posting_Read (TX_CTL (Port_Cfg.Port));
+
+      PCH.FDI.Train (PCH_FDI_Port, PCH.FDI.TP_1, Success);
+
+      if Success then
+         Registers.Unset_And_Set_Mask
+           (Register    => TX_CTL (Port_Cfg.Port),
+            Mask_Unset  => FDI_TX_CTL_TRAINING_PATTERN_MASK,
+            Mask_Set    => FDI_TX_CTL_TRAINING_PATTERN_2);
+         Registers.Posting_Read (TX_CTL (Port_Cfg.Port));
+
+         PCH.FDI.Train (PCH_FDI_Port, PCH.FDI.TP_2, Success);
+      end if;
+
+      if Success then
+         Registers.Unset_And_Set_Mask
+           (Register    => TX_CTL (Port_Cfg.Port),
+            Mask_Unset  => FDI_TX_CTL_TRAINING_PATTERN_MASK,
+            Mask_Set    => FDI_TX_CTL_TRAINING_PATTERN_NORMAL);
+         Registers.Posting_Read (TX_CTL (Port_Cfg.Port));
+
+         PCH.FDI.Train (PCH_FDI_Port, PCH.FDI.TP_None, Success);
+      else
+         Registers.Unset_And_Set_Mask
+           (Register    => TX_CTL (Port_Cfg.Port),
+            Mask_Unset  => FDI_TX_CTL_FDI_TX_ENABLE or
+                           FDI_TX_CTL_TRAINING_PATTERN_MASK,
+            Mask_Set    => FDI_TX_CTL_TRAINING_PATTERN_1);
+         PCH.FDI.Off (PCH_FDI_Port, PCH.FDI.Rx_Off);
+
+         Registers.Unset_Mask
+           (Register => TX_CTL (Port_Cfg.Port),
+            Mask     => FDI_TX_CTL_FDI_PLL_ENABLE);
+         PCH.FDI.Off (PCH_FDI_Port, PCH.FDI.Clock_Off);
+      end if;
+   end Simple_Training;
+
+   ----------------------------------------------------------------------------
+
+   procedure Pre_On (Port_Cfg : Port_Config)
+   is
+      Composite_Sel : constant :=
+        (if Config.Has_FDI_Composite_Sel then
+            FDI_TX_CTL_COMPOSITE_SYNC_SELECT else 0);
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      -- The PCH_FDI_CHICKEN_B_AND_C bit may not be changed when any of
+      -- both ports is active. Bandwidth calculations before calling us
+      -- should ensure this.
+      if Config.Has_FDI_C then
+         if Port_Cfg.Port = DIGI_D or
+            (Port_Cfg.Port = DIGI_C and
+             Port_Cfg.FDI.Lane_Count <= DP_Lane_Count_2)
+         then
+            Registers.Set_Mask
+              (Register => Registers.PCH_FDI_CHICKEN_B_C,
+               Mask     => PCH_FDI_CHICKEN_B_AND_C);
+         elsif Port_Cfg.Port = DIGI_C then
+            Registers.Unset_Mask
+              (Register => Registers.PCH_FDI_CHICKEN_B_C,
+               Mask     => PCH_FDI_CHICKEN_B_AND_C);
+         end if;
+      end if;
+
+      PCH.FDI.Pre_Train (PCH_FDIs (Port_Cfg.Port), Port_Cfg);
+
+      Registers.Write
+        (Register => TX_CTL (Port_Cfg.Port),
+         Value    => FDI_TX_CTL_PORT_WIDTH_SEL (Port_Cfg.FDI.Lane_Count) or
+                     FDI_TX_CTL_ENHANCED_FRAMING_ENABLE or
+                     FDI_TX_CTL_FDI_PLL_ENABLE or
+                     Composite_Sel or
+                     FDI_TX_CTL_TRAINING_PATTERN_1);
+      Registers.Posting_Read (TX_CTL (Port_Cfg.Port));
+      Time.U_Delay (100);
+   end Pre_On;
+
+   ----------------------------------------------------------------------------
+
+   procedure Post_On
+     (Port_Cfg : in     Port_Config;
+      Success  :    out Boolean)
+   is
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      case Config.FDI_Training is
+         when GMA.Simple_Training   => Simple_Training (Port_Cfg, Success);
+         when GMA.Full_Training     => Full_Training (Port_Cfg, Success);
+         when GMA.Auto_Training     => Auto_Training (Port_Cfg, Success);
+      end case;
+   end Post_On;
+
+   ----------------------------------------------------------------------------
+
+   procedure Off (Port : GPU_FDI_Port; OT : Off_Type)
+   is
+      PCH_FDI_Port : constant PCH.FDI_Port_Type := PCH_FDIs (Port);
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      Registers.Unset_And_Set_Mask
+        (Register    => TX_CTL (Port),
+         Mask_Unset  => FDI_TX_CTL_FDI_TX_ENABLE or
+                        FDI_TX_CTL_AUTO_TRAIN_ENABLE or
+                        FDI_TX_CTL_TRAINING_PATTERN_MASK,
+         Mask_Set    => FDI_TX_CTL_TRAINING_PATTERN_1);
+
+      PCH.FDI.Off (PCH_FDI_Port, PCH.FDI.Rx_Off);
+
+      if OT >= Clock_Off then
+         Registers.Unset_Mask
+           (Register => TX_CTL (Port),
+            Mask     => FDI_TX_CTL_FDI_PLL_ENABLE);
+
+         PCH.FDI.Off (PCH_FDI_Port, PCH.FDI.Clock_Off);
+      end if;
+   end Off;
+
+end HW.GFX.GMA.Connectors.FDI;
diff --git a/common/ironlake/hw-gfx-gma-connectors-fdi.ads b/common/ironlake/hw-gfx-gma-connectors-fdi.ads
new file mode 100644
index 0000000..9f0cf08
--- /dev/null
+++ b/common/ironlake/hw-gfx-gma-connectors-fdi.ads
@@ -0,0 +1,43 @@
+--
+-- Copyright (C) 2016 secunet Security Networks AG
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; version 2 of the License.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA.PCH;
+
+private package HW.GFX.GMA.Connectors.FDI
+is
+
+   subtype GPU_FDI_Port is GPU_Port range DIGI_B .. DIGI_D;
+
+   type PCH_FDI_Mapping is array (GPU_FDI_Port) of PCH.FDI_Port_Type;
+   PCH_FDIs : constant PCH_FDI_Mapping :=
+     (DIGI_B => PCH.FDI_A,
+      DIGI_C => PCH.FDI_B,
+      DIGI_D => PCH.FDI_C);
+
+   type Off_Type is (Link_Off, Clock_Off);
+
+   ----------------------------------------------------------------------------
+
+   procedure Pre_On (Port_Cfg : Port_Config)
+   with
+      Pre => Port_Cfg.Port in GPU_FDI_Port;
+
+   procedure Post_On
+     (Port_Cfg : in     Port_Config;
+      Success  :    out Boolean)
+   with
+      Pre => Port_Cfg.Port in GPU_FDI_Port;
+
+   procedure Off (Port : GPU_FDI_Port; OT : Off_Type);
+
+end HW.GFX.GMA.Connectors.FDI;
diff --git a/common/ironlake/hw-gfx-gma-connectors.adb b/common/ironlake/hw-gfx-gma-connectors.adb
new file mode 100644
index 0000000..4e3ff53
--- /dev/null
+++ b/common/ironlake/hw-gfx-gma-connectors.adb
@@ -0,0 +1,184 @@
+--
+-- Copyright (C) 2015-2016 secunet Security Networks AG
+-- Copyright (C) 2016 Nico Huber <nico.h@gmx.de>
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; version 2 of the License.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA.Config;
+with HW.GFX.GMA.Panel;
+with HW.GFX.GMA.Connectors.EDP;
+with HW.GFX.GMA.Connectors.FDI;
+with HW.GFX.GMA.PCH.VGA;
+with HW.GFX.GMA.PCH.LVDS;
+with HW.GFX.GMA.PCH.HDMI;
+with HW.GFX.GMA.PCH.DP;
+with HW.GFX.GMA.PCH.Transcoder;
+
+with HW.Debug;
+with GNAT.Source_Info;
+
+package body HW.GFX.GMA.Connectors
+is
+
+   function Is_Internal (Port_Cfg : Port_Config) return Boolean
+   is
+   begin
+      return
+         Port_Cfg.Port = DIGI_A or
+         (Port_Cfg.Is_FDI and Port_Cfg.PCH_Port = PCH_LVDS);
+   end Is_Internal;
+
+   ----------------------------------------------------------------------------
+
+   procedure Pre_On
+     (Port_Cfg    : in     Port_Config;
+      PLL_Hint    : in     Word32;
+      Pipe_Hint   : in     Word32;
+      Success     :    out Boolean)
+   is
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      if Port_Cfg.Port = DIGI_A then
+         EDP.Pre_On (Port_Cfg, Pipe_Hint);
+      elsif Port_Cfg.Port in FDI.GPU_FDI_Port then
+         FDI.Pre_On (Port_Cfg);
+      end if;
+      Success := True;
+   end Pre_On;
+
+   procedure Post_On
+     (Port_Cfg : in     Port_Config;
+      PLL_Hint : in     Word32;
+      Success  :    out Boolean)
+   is
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      if Port_Cfg.Port = DIGI_A then
+         EDP.Pre_Training;
+         Success := True;
+      elsif Port_Cfg.Port in FDI.GPU_FDI_Port then
+         declare
+            FDI_Port : constant PCH.FDI_Port_Type :=
+               FDI.PCH_FDIs (Port_Cfg.Port);
+         begin
+            FDI.Post_On (Port_Cfg, Success);
+
+            if Success then
+               PCH.Transcoder.On (Port_Cfg, FDI_Port, PLL_Hint);
+               if Port_Cfg.PCH_Port = PCH_DAC then
+                  PCH.VGA.On (FDI_Port, Port_Cfg.Mode);
+               elsif Port_Cfg.PCH_Port = PCH_LVDS then
+                  PCH.LVDS.On (Port_Cfg, FDI_Port);
+               elsif Port_Cfg.PCH_Port in PCH_HDMI_Port then
+                  PCH.HDMI.On (Port_Cfg, FDI_Port);
+               elsif Port_Cfg.PCH_Port in PCH_DP_Port then
+                  PCH.DP.On (Port_Cfg, Success);
+               end if;
+            end if;
+         end;
+      else
+         Success := False;
+      end if;
+
+      if Success and Is_Internal (Port_Cfg) then
+         Panel.On;
+      end if;
+
+      if Port_Cfg.Port = DIGI_A then
+         EDP.Post_On (Port_Cfg.DP, Success);
+      end if;
+
+      if Success and Is_Internal (Port_Cfg) then
+         Panel.Backlight_On;
+      end if;
+   end Post_On;
+
+   ----------------------------------------------------------------------------
+
+   procedure Pre_Off (Port_Cfg : Port_Config)
+   is
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      if Is_Internal (Port_Cfg) then
+         Panel.Backlight_Off;
+         Panel.Off;
+      end if;
+   end Pre_Off;
+
+   procedure Post_Off (Port_Cfg : Port_Config)
+   is
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      if Port_Cfg.Port = DIGI_A then
+         EDP.Off (Port_Cfg.Port);
+      elsif Port_Cfg.Port in FDI.GPU_FDI_Port then
+         declare
+            FDI_Port : constant PCH.FDI_Port_Type :=
+               FDI.PCH_FDIs (Port_Cfg.Port);
+         begin
+            if Port_Cfg.PCH_Port in PCH_DP_Port then
+               PCH.DP.Off (Port_Cfg.PCH_Port);
+            end if;
+
+            FDI.Off (Port_Cfg.Port, FDI.Link_Off);
+
+            if Port_Cfg.PCH_Port = PCH_DAC then
+               PCH.VGA.Off;
+            elsif Port_Cfg.PCH_Port = PCH_LVDS then
+               PCH.LVDS.Off;
+            elsif Port_Cfg.PCH_Port in PCH_HDMI_Port then
+               PCH.HDMI.Off (Port_Cfg.PCH_Port);
+            end if;
+            PCH.Transcoder.Off (FDI_Port);
+
+            FDI.Off (Port_Cfg.Port, FDI.Clock_Off);
+         end;
+      end if;
+   end Post_Off;
+
+   ----------------------------------------------------------------------------
+
+   procedure Pre_All_Off
+   is
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      Panel.Backlight_Off;
+      Panel.Off;
+   end Pre_All_Off;
+
+   procedure Post_All_Off
+   is
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      EDP.Off (DIGI_A);
+
+      for Port in FDI.GPU_FDI_Port loop
+         FDI.Off (Port, FDI.Link_Off);
+      end loop;
+      PCH.VGA.Off;
+      PCH.LVDS.Off;
+      PCH.HDMI.All_Off;
+      PCH.DP.All_Off;
+      for Port in PCH.FDI_Port_Type loop
+         PCH.Transcoder.Off (Port);
+      end loop;
+      for Port in FDI.GPU_FDI_Port loop
+         FDI.Off (Port, FDI.Clock_Off);
+      end loop;
+   end Post_All_Off;
+
+end HW.GFX.GMA.Connectors;
diff --git a/common/ironlake/hw-gfx-gma-pch-dp.adb b/common/ironlake/hw-gfx-gma-pch-dp.adb
new file mode 100644
index 0000000..1fb3578
--- /dev/null
+++ b/common/ironlake/hw-gfx-gma-pch-dp.adb
@@ -0,0 +1,205 @@
+--
+-- Copyright (C) 2016 Nico Huber <nico.h@gmx.de>
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; version 2 of the License.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.DP_Training;
+with HW.GFX.GMA.DP_Aux_Ch;
+with HW.GFX.GMA.DP_Info;
+with HW.GFX.GMA.Registers;
+
+with HW.Debug;
+with GNAT.Source_Info;
+
+package body HW.GFX.GMA.PCH.DP is
+
+   type DP_Array is array (PCH_DP_Port) of Registers.Registers_Index;
+   DP_CTL : constant DP_Array :=
+     (PCH_DP_B => Registers.PCH_DP_B,
+      PCH_DP_C => Registers.PCH_DP_C,
+      PCH_DP_D => Registers.PCH_DP_D);
+
+   DP_CTL_DISPLAY_PORT_ENABLE          : constant := 1 * 2 ** 31;
+   DP_CTL_VSWING_LEVEL_SET_SHIFT       : constant :=          25;
+   DP_CTL_VSWING_LEVEL_SET_MASK        : constant := 7 * 2 ** 25;
+   DP_CTL_PREEMPH_LEVEL_SET_SHIFT      : constant :=          22;
+   DP_CTL_PREEMPH_LEVEL_SET_MASK       : constant := 7 * 2 ** 22;
+   DP_CTL_PORT_WIDTH_SHIFT             : constant :=          19;
+   DP_CTL_PORT_REVERSAL                : constant := 1 * 2 ** 15;
+   DP_CTL_LINK_TRAIN_MASK              : constant := 7 * 2 **  8;
+   DP_CTL_LINK_TRAIN_PAT1              : constant := 0 * 2 **  8;
+   DP_CTL_LINK_TRAIN_PAT2              : constant := 1 * 2 **  8;
+   DP_CTL_LINK_TRAIN_IDLE              : constant := 2 * 2 **  8;
+   DP_CTL_LINK_TRAIN_NORMAL            : constant := 3 * 2 **  8;
+   DP_CTL_AUDIO_OUTPUT_ENABLE          : constant := 1 * 2 **  6;
+   DP_CTL_PORT_DETECT                  : constant := 1 * 2 **  2;
+
+   function DP_CTL_VSWING_LEVEL_SET
+     (VS : DP_Info.DP_Voltage_Swing)
+      return Word32
+   is
+   begin
+      return Shift_Left
+        (Word32 (DP_Info.DP_Voltage_Swing'Pos (VS)),
+         DP_CTL_VSWING_LEVEL_SET_SHIFT);
+   end DP_CTL_VSWING_LEVEL_SET;
+
+   function DP_CTL_PREEMPH_LEVEL_SET (PE : DP_Info.DP_Pre_Emph) return Word32
+   is
+   begin
+      return Shift_Left
+        (Word32 (DP_Info.DP_Pre_Emph'Pos (PE)), DP_CTL_PREEMPH_LEVEL_SET_SHIFT);
+   end DP_CTL_PREEMPH_LEVEL_SET;
+
+   function DP_CTL_PORT_WIDTH (Lane_Count : DP_Lane_Count) return Word32
+   is
+   begin
+      return Shift_Left
+        (Word32 (Lane_Count_As_Integer (Lane_Count)) - 1,
+         DP_CTL_PORT_WIDTH_SHIFT);
+   end DP_CTL_PORT_WIDTH;
+
+   type DP_CTL_LINK_TRAIN_Array is array (DP_Info.Training_Pattern) of Word32;
+   DP_CTL_LINK_TRAIN : constant DP_CTL_LINK_TRAIN_Array :=
+     (DP_Info.TP_1      => DP_CTL_LINK_TRAIN_PAT1,
+      DP_Info.TP_2      => DP_CTL_LINK_TRAIN_PAT2,
+      DP_Info.TP_3      => DP_CTL_LINK_TRAIN_PAT2,
+      DP_Info.TP_Idle   => DP_CTL_LINK_TRAIN_IDLE,
+      DP_Info.TP_None   => DP_CTL_LINK_TRAIN_NORMAL);
+
+   ----------------------------------------------------------------------------
+
+   pragma Warnings (GNATprove, Off, "unused variable ""Port""",
+                    Reason => "Needed for a common interface");
+   function Max_V_Swing
+     (Port : PCH_DP_Port)
+      return DP_Info.DP_Voltage_Swing
+   is
+   begin
+      return DP_Info.VS_Level_3;
+   end Max_V_Swing;
+
+   function Max_Pre_Emph
+     (Port        : PCH_DP_Port;
+      Train_Set   : DP_Info.Train_Set)
+      return DP_Info.DP_Pre_Emph
+   is
+   begin
+      return
+        (case Train_Set.Voltage_Swing is
+            when DP_Info.VS_Level_0 => DP_Info.Emph_Level_3,
+            when DP_Info.VS_Level_1 => DP_Info.Emph_Level_2,
+            when DP_Info.VS_Level_2 => DP_Info.Emph_Level_1,
+            when DP_Info.VS_Level_3 => DP_Info.Emph_Level_0);
+   end Max_Pre_Emph;
+
+   ----------------------------------------------------------------------------
+
+   pragma Warnings (GNATprove, Off, "unused variable ""Link""",
+                    Reason => "Needed for a common interface");
+   procedure Set_Training_Pattern
+     (Port     : PCH_DP_Port;
+      Link     : DP_Link;
+      Pattern  : DP_Info.Training_Pattern)
+   is
+   begin
+      Registers.Unset_And_Set_Mask
+        (Register    => DP_CTL (Port),
+         Mask_Unset  => DP_CTL_LINK_TRAIN_MASK,
+         Mask_Set    => DP_CTL_LINK_TRAIN (Pattern));
+   end Set_Training_Pattern;
+
+   procedure Set_Signal_Levels
+     (Port        : PCH_DP_Port;
+      Link        : DP_Link;
+      Train_Set   : DP_Info.Train_Set)
+   is
+   begin
+      Registers.Unset_And_Set_Mask
+        (Register    => DP_CTL (Port),
+         Mask_Unset  => DP_CTL_VSWING_LEVEL_SET_MASK or
+                        DP_CTL_PREEMPH_LEVEL_SET_MASK,
+         Mask_Set    => DP_CTL_VSWING_LEVEL_SET (Train_Set.Voltage_Swing) or
+                        DP_CTL_PREEMPH_LEVEL_SET (Train_Set.Pre_Emph));
+   end Set_Signal_Levels;
+
+   procedure Off (Port : PCH_DP_Port)
+   is
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      Registers.Unset_And_Set_Mask
+        (Register    => DP_CTL (Port),
+         Mask_Unset  => DP_CTL_LINK_TRAIN_MASK,
+         Mask_Set    => DP_CTL_LINK_TRAIN_IDLE);
+      Registers.Posting_Read (DP_CTL (Port));
+
+      Registers.Write (DP_CTL (Port), 0);
+      Registers.Posting_Read (DP_CTL (Port));
+   end Off;
+   pragma Warnings (GNATprove, On, "unused variable ""Port""");
+   pragma Warnings (GNATprove, On, "unused variable ""Link""");
+
+   ----------------------------------------------------------------------------
+
+   procedure On
+     (Port_Cfg : in     Port_Config;
+      Success  :    out Boolean)
+   is
+      function To_DP (Port : PCH_DP_Port) return DP_Port
+      is
+      begin
+         return
+           (case Port is
+               when PCH_DP_B => DP_B,
+               when PCH_DP_C => DP_C,
+               when PCH_DP_D => DP_D);
+      end To_DP;
+      package Training is new DP_Training
+        (TPS3_Supported    => False,
+         T                 => PCH_DP_Port,
+         Aux_T             => DP_Port,
+         Aux_Ch            => DP_Aux_Ch,
+         DP_Info           => DP_Info,
+         To_Aux            => To_DP,
+         Max_V_Swing       => Max_V_Swing,
+         Max_Pre_Emph      => Max_Pre_Emph,
+         Set_Pattern       => Set_Training_Pattern,
+         Set_Signal_Levels => Set_Signal_Levels,
+         Off               => Off);
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      Registers.Write
+        (Register => DP_CTL (Port_Cfg.PCH_Port),
+         Value    => DP_CTL_DISPLAY_PORT_ENABLE or
+                     DP_CTL_PORT_WIDTH (Port_Cfg.DP.Lane_Count) or
+                     DP_CTL_LINK_TRAIN_PAT1);
+
+      Training.Train_DP
+        (Port     => Port_Cfg.PCH_Port,
+         Link     => Port_Cfg.DP,
+         Success  => Success);
+   end On;
+
+   ----------------------------------------------------------------------------
+
+   procedure All_Off
+   is
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      for Port in PCH_DP_Port loop
+         Off (Port);
+      end loop;
+   end All_Off;
+
+end HW.GFX.GMA.PCH.DP;
diff --git a/common/ironlake/hw-gfx-gma-pch-dp.ads b/common/ironlake/hw-gfx-gma-pch-dp.ads
new file mode 100644
index 0000000..ee77e30
--- /dev/null
+++ b/common/ironlake/hw-gfx-gma-pch-dp.ads
@@ -0,0 +1,26 @@
+--
+-- Copyright (C) 2016 secunet Security Networks AG
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; version 2 of the License.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+
+package HW.GFX.GMA.PCH.DP
+is
+
+   procedure On
+     (Port_Cfg : in     Port_Config;
+      Success  :    out Boolean)
+   with
+      Pre => Port_Cfg.PCH_Port in PCH_DP_Port;
+
+   procedure Off (Port : PCH_DP_Port);
+   procedure All_Off;
+
+end HW.GFX.GMA.PCH.DP;
diff --git a/common/ironlake/hw-gfx-gma-pch-hdmi.adb b/common/ironlake/hw-gfx-gma-pch-hdmi.adb
new file mode 100644
index 0000000..8bf99db
--- /dev/null
+++ b/common/ironlake/hw-gfx-gma-pch-hdmi.adb
@@ -0,0 +1,94 @@
+--
+-- Copyright (C) 2015-2016 secunet Security Networks AG
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; version 2 of the License.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA.Registers;
+
+with HW.Debug;
+with GNAT.Source_Info;
+
+package body HW.GFX.GMA.PCH.HDMI
+is
+
+   PCH_HDMI_ENABLE               : constant := 1 * 2 ** 31;
+   PCH_HDMI_COLOR_FORMAT_8BPC    : constant := 0 * 2 ** 26;
+   PCH_HDMI_COLOR_FORMAT_12BPC   : constant := 3 * 2 ** 26;
+   PCH_HDMI_COLOR_FORMAT_MASK    : constant := 7 * 2 ** 26;
+   PCH_HDMI_SDVO_ENCODING_SDVO   : constant := 0 * 2 ** 10;
+   PCH_HDMI_SDVO_ENCODING_HDMI   : constant := 2 * 2 ** 10;
+   PCH_HDMI_SDVO_ENCODING_MASK   : constant := 3 * 2 ** 10;
+   PCH_HDMI_VSYNC_ACTIVE_HIGH    : constant := 1 * 2 **  4;
+   PCH_HDMI_HSYNC_ACTIVE_HIGH    : constant := 1 * 2 **  3;
+   PCH_HDMI_PORT_DETECT          : constant := 1 * 2 **  2;
+
+   PCH_HDMI_MASK : constant Word32 :=
+      PCH_TRANSCODER_SELECT_MASK or
+      PCH_HDMI_ENABLE or
+      PCH_HDMI_COLOR_FORMAT_MASK or
+      PCH_HDMI_SDVO_ENCODING_MASK or
+      PCH_HDMI_HSYNC_ACTIVE_HIGH or
+      PCH_HDMI_VSYNC_ACTIVE_HIGH;
+
+   type PCH_HDMI_Array is array (PCH_HDMI_Port) of Registers.Registers_Index;
+   PCH_HDMI : constant PCH_HDMI_Array := PCH_HDMI_Array'
+     (PCH_HDMI_B => Registers.PCH_HDMIB,
+      PCH_HDMI_C => Registers.PCH_HDMIC,
+      PCH_HDMI_D => Registers.PCH_HDMID);
+
+   ----------------------------------------------------------------------------
+
+   procedure On (Port_Cfg : Port_Config; FDI_Port : FDI_Port_Type)
+   is
+      Polarity : constant Word32 :=
+        (if Port_Cfg.Mode.H_Sync_Active_High then
+            PCH_HDMI_HSYNC_ACTIVE_HIGH else 0) or
+        (if Port_Cfg.Mode.V_Sync_Active_High then
+            PCH_HDMI_VSYNC_ACTIVE_HIGH else 0);
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      -- registers are just sufficient for setup with DVI adaptor
+
+      Registers.Unset_And_Set_Mask
+         (Register   => PCH_HDMI (Port_Cfg.PCH_Port),
+          Mask_Unset => PCH_HDMI_MASK,
+          Mask_Set   => PCH_HDMI_ENABLE or
+                        PCH_TRANSCODER_SELECT (FDI_Port) or
+                        PCH_HDMI_SDVO_ENCODING_HDMI or
+                        Polarity);
+   end On;
+
+   ----------------------------------------------------------------------------
+
+   procedure Off (Port : PCH_HDMI_Port)
+   is
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      Registers.Unset_And_Set_Mask
+         (Register   => PCH_HDMI (Port),
+          Mask_Unset => PCH_HDMI_MASK,
+          Mask_Set   => PCH_HDMI_HSYNC_ACTIVE_HIGH or
+                        PCH_HDMI_VSYNC_ACTIVE_HIGH);
+   end Off;
+
+   procedure All_Off
+   is
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      for Port in PCH_HDMI_Port loop
+         Off (Port);
+      end loop;
+   end All_Off;
+
+end HW.GFX.GMA.PCH.HDMI;
diff --git a/common/ironlake/hw-gfx-gma-pch-hdmi.ads b/common/ironlake/hw-gfx-gma-pch-hdmi.ads
new file mode 100644
index 0000000..9853610
--- /dev/null
+++ b/common/ironlake/hw-gfx-gma-pch-hdmi.ads
@@ -0,0 +1,24 @@
+--
+-- Copyright (C) 2016 secunet Security Networks AG
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; version 2 of the License.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+
+package HW.GFX.GMA.PCH.HDMI
+is
+
+   procedure On (Port_Cfg : Port_Config; FDI_Port : FDI_Port_Type)
+   with
+      Pre => Port_Cfg.PCH_Port in PCH_HDMI_Port;
+
+   procedure Off (Port : PCH_HDMI_Port);
+   procedure All_Off;
+
+end HW.GFX.GMA.PCH.HDMI;
diff --git a/common/ironlake/hw-gfx-gma-pch-lvds.adb b/common/ironlake/hw-gfx-gma-pch-lvds.adb
new file mode 100644
index 0000000..6ad334e
--- /dev/null
+++ b/common/ironlake/hw-gfx-gma-pch-lvds.adb
@@ -0,0 +1,58 @@
+--
+-- Copyright (C) 2015-2016 secunet Security Networks AG
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; version 2 of the License.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA.Config;
+with HW.GFX.GMA.Registers;
+
+with HW.Debug;
+with GNAT.Source_Info;
+
+package body HW.GFX.GMA.PCH.LVDS is
+
+   PCH_LVDS_ENABLE               : constant :=  1 * 2 ** 31;
+   PCH_LVDS_TWO_CHANNEL          : constant := 15 * 2 **  2;
+
+   PCH_LVDS_MASK : constant Word32 :=
+      PCH_TRANSCODER_SELECT_MASK or
+      PCH_LVDS_ENABLE or
+      PCH_LVDS_TWO_CHANNEL;
+
+   ----------------------------------------------------------------------------
+
+   procedure On (Port_Cfg : Port_Config; FDI_Port : FDI_Port_Type)
+   is
+      Two_Channel : constant Word32 :=
+        (if Port_Cfg.Mode.Dotclock >= Config.LVDS_Dual_Threshold then
+            PCH_LVDS_TWO_CHANNEL else 0);
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      Registers.Unset_And_Set_Mask
+         (Register   => Registers.PCH_LVDS,
+          Mask_Unset => PCH_LVDS_MASK,
+          Mask_Set   => PCH_LVDS_ENABLE or
+                        PCH_TRANSCODER_SELECT (FDI_Port) or
+                        Two_Channel);
+   end On;
+
+   ----------------------------------------------------------------------------
+
+   procedure Off
+   is
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      Registers.Unset_Mask (Registers.PCH_LVDS, PCH_LVDS_ENABLE);
+   end Off;
+
+end HW.GFX.GMA.PCH.LVDS;
diff --git a/common/ironlake/hw-gfx-gma-pch-lvds.ads b/common/ironlake/hw-gfx-gma-pch-lvds.ads
new file mode 100644
index 0000000..f4a5f26
--- /dev/null
+++ b/common/ironlake/hw-gfx-gma-pch-lvds.ads
@@ -0,0 +1,21 @@
+--
+-- Copyright (C) 2016 secunet Security Networks AG
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; version 2 of the License.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+
+package HW.GFX.GMA.PCH.LVDS
+is
+
+   procedure On (Port_Cfg : Port_Config; FDI_Port : FDI_Port_Type);
+
+   procedure Off;
+
+end HW.GFX.GMA.PCH.LVDS;
diff --git a/common/ironlake/hw-gfx-gma-plls.adb b/common/ironlake/hw-gfx-gma-plls.adb
new file mode 100644
index 0000000..7ecfb66
--- /dev/null
+++ b/common/ironlake/hw-gfx-gma-plls.adb
@@ -0,0 +1,570 @@
+--
+-- Copyright (C) 2015-2016 secunet Security Networks AG
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; version 2 of the License.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+
+with HW.Time;
+with HW.GFX.GMA.Config;
+with HW.GFX.GMA.Registers;
+
+with HW.Debug;
+with GNAT.Source_Info;
+
+package body HW.GFX.GMA.PLLs
+with
+   Refined_State => (State => PLLs)
+is
+
+   Debug_Clocks : constant Boolean := False;
+
+   type Count_Range is new Natural range 0 .. 2;
+
+   type PLL_State is record
+      Use_Count   : Count_Range;
+      Used_For_DP : Boolean;
+      Link_Rate   : DP_Bandwidth;
+      Mode        : Mode_Type;
+   end record;
+
+   type PLL_State_Array is array (DPLLs) of PLL_State;
+
+   PLLs : PLL_State_Array;
+
+   ----------------------------------------------------------------------------
+
+   subtype N_Range     is Int64 range          3 ..          8;
+   subtype M_Range     is Int64 range         79 ..        128;
+   subtype M1_Range    is Int64 range         14 ..         25;
+   subtype M2_Range    is Int64 range          7 ..         12;
+   subtype P_Range     is Int64 range          5 ..        112;
+   subtype P1_Range    is Int64 range          1 ..          8;
+   subtype P2_Range    is Int64 range          5 ..         14;
+   subtype VCO_Range   is Int64 range 1760000000 .. 3510000000;
+   subtype Clock_Range is HW.GFX.Frequency_Type;
+
+   type Clock_Type is
+      record
+         N               : N_Range;
+         M1              : M1_Range;
+         M2              : M2_Range;
+         P1              : P1_Range;
+         P2              : P2_Range;
+         M               : M_Range;
+         P               : P_Range;
+         VCO             : VCO_Range;
+         Reference_Clock : Clock_Range;
+         Dotclock        : Clock_Range;
+      end record;
+
+   Invalid_Clock : constant Clock_Type := Clock_Type'
+      (N               => N_Range'Last,
+       M1              => M1_Range'Last,
+       M2              => M2_Range'Last,
+       P1              => P1_Range'Last,
+       P2              => P2_Range'Last,
+       Reference_Clock => Clock_Range'Last,
+       M               => M_Range'Last,
+       P               => P_Range'Last,
+       VCO             => VCO_Range'Last,
+       Dotclock        => Clock_Range'Last);
+
+   type Limits_Type is
+      record
+         N_Lower      : N_Range;
+         N_Upper      : N_Range;
+         M_Lower      : M_Range;
+         M_Upper      : M_Range;
+         M1_Lower     : M1_Range;
+         M1_Upper     : M1_Range;
+         M2_Lower     : M2_Range;
+         M2_Upper     : M2_Range;
+         P_Lower      : P_Range;
+         P_Upper      : P_Range;
+         P1_Lower     : P1_Range;
+         P1_Upper     : P1_Range;
+         P2_Fast      : P2_Range;
+         P2_Slow      : P2_Range;
+         P2_Threshold : Clock_Range;
+         VCO_Lower    : VCO_Range;
+         VCO_Upper    : VCO_Range;
+      end record;
+
+   LVDS_Single_Limits : constant Limits_Type := Limits_Type'
+     (N_Lower      =>   3,           N_Upper   =>   5,
+      M_Lower      =>  79,           M_Upper   => 118,
+      M1_Lower     =>  14,           M1_Upper  =>  22, -- this is capped by M_Upper >= 5 * M1 + M2_Lower
+      M2_Lower     =>   7,           M2_Upper  =>  11,
+      P_Lower      =>  28,           P_Upper   => 112,
+      P1_Lower     =>   2,           P1_Upper  =>   8,
+      P2_Fast      =>  14,           P2_Slow   =>  14,
+      P2_Threshold => Clock_Range'First,
+      VCO_Lower    => 1_760_000_000, VCO_Upper => 3_510_000_000);
+   LVDS_Dual_Limits : constant Limits_Type := Limits_Type'
+     (N_Lower      =>   3,           N_Upper   =>   5,
+      M_Lower      =>  79,           M_Upper   => 127,
+      M1_Lower     =>  14,           M1_Upper  =>  24,
+      M2_Lower     =>   7,           M2_Upper  =>  11,
+      P_Lower      =>  14,           P_Upper   =>  56,
+      P1_Lower     =>   2,           P1_Upper  =>   8,
+      P2_Fast      =>   7,           P2_Slow   =>   7,
+      P2_Threshold => Clock_Range'First,
+      VCO_Lower    => 1_760_000_000, VCO_Upper => 3_510_000_000);
+   All_Other_Limits : constant Limits_Type := Limits_Type'
+     (N_Lower      =>   3,           N_Upper   =>   7,
+      M_Lower      =>  79,           M_Upper   => 127,
+      M1_Lower     =>  14,           M1_Upper  =>  24,
+      M2_Lower     =>   7,           M2_Upper  =>  11,
+      P_Lower      =>   5,           P_Upper   =>  80,
+      P1_Lower     =>   1,           P1_Upper  =>   8,
+      -- use P2_Slow if Dotclock <= P2_Threshold, P2_Fast otherwise
+      P2_Fast      =>   5,           P2_Slow   =>  10,
+      P2_Threshold =>   225_000_000,
+      VCO_Lower    => 1_760_000_000, VCO_Upper => 3_510_000_000);
+
+   ----------------------------------------------------------------------------
+
+   type Regs is array (DPLLs) of Registers.Registers_Index;
+
+   DPLL : constant Regs := Regs'(Registers.PCH_DPLL_A, Registers.PCH_DPLL_B);
+   DPLL_VCO_ENABLE         : constant := 1 * 2 ** 31;
+   DPLL_P2_10_OR_14        : constant := 0 * 2 ** 24;
+   DPLL_P2_5_OR_7          : constant := 1 * 2 ** 24;
+   DPLL_P1_DIVIDER_SHIFT   : constant := 16;
+   DPLL_SDVOCLK            : constant := 2 * 2 ** 13;
+
+   DPLL_HIGH_SPEED : constant := 1 * 2 ** 30;
+   DPLL_MODE_LVDS  : constant := 2 * 2 ** 26;
+   DPLL_MODE_DAC   : constant := 1 * 2 ** 26;
+   DPLL_DREFCLK    : constant := 0 * 2 ** 13;
+   DPLL_SSC        : constant := 3 * 2 ** 13;
+
+   MODE_DPLL_DAC_HDMI : constant Word32 := Word32'
+      (DPLL_MODE_DAC or DPLL_DREFCLK or DPLL_HIGH_SPEED);
+
+   MODE_DPLL_LVDS : constant Word32 := Word32'
+      (DPLL_MODE_LVDS or DPLL_SSC);
+
+   MODE_DPLL_DP : constant Word32 := Word32'
+      (DPLL_MODE_DAC or DPLL_SSC or DPLL_HIGH_SPEED);
+
+   type DPLL_Mode_Array is array (Display_Type) of Word32;
+
+   DPLL_Mode : constant DPLL_Mode_Array := DPLL_Mode_Array'
+     (LVDS     => MODE_DPLL_LVDS,
+      DP       => MODE_DPLL_DP,
+      others   => MODE_DPLL_DAC_HDMI);
+
+   FP0 : constant Regs := Regs'(Registers.PCH_FPA0, Registers.PCH_FPB0);
+   FP1 : constant Regs := Regs'(Registers.PCH_FPA1, Registers.PCH_FPB1);
+   FP_DOUBLE_CLOCK       : constant := 1 * 2 ** 27;
+   FP_N_SHIFT            : constant := 16;
+   FP_M1_SHIFT           : constant := 8;
+   FP_M2_SHIFT           : constant := 0;
+
+   ----------------------------------------------------------------------------
+
+   procedure Verify_Parameters
+      (N               : in     N_Range;
+       M1              : in     M1_Range;
+       M2              : in     M2_Range;
+       P1              : in     P1_Range;
+       P2              : in     P2_Range;
+       Reference_Clock : in     Clock_Range;
+       Current_Limits  : in     Limits_Type;
+       Result          :    out Clock_Type;
+       Valid           :    out Boolean)
+   with
+      Global => null,
+      Pre => True,
+      Post => True
+   is
+      M        : Int64;
+      P        : Int64;
+      VCO      : Int64;
+      Dotclock : Int64;
+   begin
+      pragma Debug (Debug_Clocks, Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      M        := 5 * M1 + M2;
+      P        := P1 * P2;
+      VCO      := (Int64 (Reference_Clock) * M) / N;
+      Dotclock := VCO / P;
+
+      pragma Debug (Debug_Clocks and not (Current_Limits.P1_Lower  <= P1  and P1  <= Current_Limits.P1_Upper ), Debug.Put_Line ("P1 out of range."));
+      pragma Debug (Debug_Clocks and     (Current_Limits.P2_Fast   /= P2  and P2  /= Current_Limits.P2_Slow  ), Debug.Put_Line ("P2 out of range."));
+      pragma Debug (Debug_Clocks and not (Current_Limits.P_Lower   <= P   and P   <= Current_Limits.P_Upper  ), Debug.Put_Line ("P out of range."));
+      pragma Debug (Debug_Clocks and not (Current_Limits.M1_Lower  <= M1  and M1  <= Current_Limits.M1_Upper ), Debug.Put_Line ("M1 out of range."));
+      pragma Debug (Debug_Clocks and not (Current_Limits.M2_Lower  <= M2  and M2  <= Current_Limits.M2_Upper ), Debug.Put_Line ("M2 out of range."));
+      -- pragma Debug (Debug_Clocks and not (M2 <= M1                                           ), Debug.Put_Line ("M1 greater thant M2."));
+      pragma Debug (Debug_Clocks and not (Current_Limits.N_Lower   <= N   and N   <= Current_Limits.N_Upper  ), Debug.Put_Line ("N out of range."));
+      pragma Debug (Debug_Clocks and not (Current_Limits.M_Lower   <= M   and M   <= Current_Limits.M_Upper  ), Debug.Put_Line ("M out of range."));
+      pragma Debug (Debug_Clocks and not (Current_Limits.VCO_Lower <= VCO and VCO <= Current_Limits.VCO_Upper), Debug.Put_Line ("VCO out of range."));
+
+      pragma Debug (Debug_Clocks and not (Int64 (Clock_Range'First) <= Dotclock),       Debug.Put_Line ("Dotclock too low."));
+      pragma Debug (Debug_Clocks and not (Int64 (Clock_Range'First) <= Dotclock),       Debug.Put_Int64 (Dotclock));
+      pragma Debug (Debug_Clocks and not (Int64 (Clock_Range'First) <= Dotclock),       Debug.New_Line);
+
+      pragma Debug (Debug_Clocks and not (Dotclock <= Int64 (Clock_Range'Last)),        Debug.Put_Line ("Dotclock too high."));
+      pragma Debug (Debug_Clocks and not (Dotclock <= Int64 (Clock_Range'Last)),        Debug.Put_Int64 (Dotclock));
+      pragma Debug (Debug_Clocks and not (Dotclock <= Int64 (Clock_Range'Last)),        Debug.New_Line);
+
+      Valid :=
+         Current_Limits.P1_Lower  <= P1  and P1  <= Current_Limits.P1_Upper  and
+         (Current_Limits.P2_Fast   = P2   or P2   = Current_Limits.P2_Slow)  and
+         Current_Limits.P_Lower   <= P   and P   <= Current_Limits.P_Upper   and
+         Current_Limits.M1_Lower  <= M1  and M1  <= Current_Limits.M1_Upper  and
+         Current_Limits.M2_Lower  <= M2  and M2  <= Current_Limits.M2_Upper  and
+         -- M2 <= M1                                                            and
+         Current_Limits.N_Lower   <= N   and N   <= Current_Limits.N_Upper   and
+         Current_Limits.M_Lower   <= M   and M   <= Current_Limits.M_Upper   and
+         Current_Limits.VCO_Lower <= VCO and VCO <= Current_Limits.VCO_Upper and
+         Int64 (Clock_Range'First) <= Dotclock                               and
+         Dotclock <= Int64 (Clock_Range'Last);
+
+      if Valid
+      then
+         Result := Clock_Type'
+            (N               => N,
+             M1              => M1,
+             M2              => M2,
+             P1              => P1,
+             P2              => P2,
+             Reference_Clock => Reference_Clock,
+             M               => M,
+             P               => P,
+             VCO             => VCO,
+             Dotclock        => Clock_Range (Dotclock));
+      else
+         Result := Invalid_Clock;
+      end if;
+
+   end Verify_Parameters;
+
+   procedure Calculate_Clock_Parameters
+      (Display         : in     Display_Type;
+       Target_Dotclock : in     Clock_Range;
+       Reference_Clock : in     Clock_Range;
+       Best_Clock      :    out Clock_Type;
+       Valid           :    out Boolean)
+   with
+      Global => null,
+      Pre => True,
+      Post => True
+   is
+      Limits : constant Limits_Type :=
+        (if Display = LVDS then
+           (if Target_Dotclock >= Config.LVDS_Dual_Threshold then
+               LVDS_Dual_Limits
+            else
+               LVDS_Single_Limits)
+         else
+            All_Other_Limits);
+
+      P2               : P2_Range;
+      Best_Delta       : Int64 := Int64'Last;
+      Current_Delta    : Int64;
+      Current_Clock    : Clock_Type;
+      Registers_Valid  : Boolean;
+   begin
+      pragma Debug (Debug_Clocks, Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      Valid      := False;
+      Best_Clock := Invalid_Clock;
+
+      if Target_Dotclock <= Limits.P2_Threshold then
+         P2 := Limits.P2_Slow;
+      else
+         P2 := Limits.P2_Fast;
+      end if;
+
+      for N in N_Range range Limits.N_Lower .. Limits.N_Upper
+      loop
+         -- reverse loops as hardware prefers higher values
+         for M1 in reverse M1_Range range Limits.M1_Lower .. Limits.M1_Upper
+         loop
+            for M2 in reverse M2_Range range Limits.M2_Lower .. Limits.M2_Upper
+            loop
+               for P1 in reverse P1_Range range Limits.P1_Lower .. Limits.P1_Upper
+               loop
+                  Verify_Parameters
+                     (N               => N,
+                      M1              => M1,
+                      M2              => M2,
+                      P1              => P1,
+                      P2              => P2,
+                      Reference_Clock => Reference_Clock,
+                      Current_Limits  => Limits,
+                      Result          => Current_Clock,
+                      Valid           => Registers_Valid);
+
+                  if Registers_Valid
+                  then
+                     if Current_Clock.Dotclock > Target_Dotclock
+                     then
+                        Current_Delta := Current_Clock.Dotclock - Target_Dotclock;
+                     else
+                        Current_Delta := Target_Dotclock - Current_Clock.Dotclock;
+                     end if;
+
+                     if Current_Delta < Best_Delta
+                     then
+                        Best_Delta := Current_Delta;
+                        Best_Clock := Current_Clock;
+                        Valid      := True;
+                     end if;
+
+                     pragma Debug (Debug_Clocks, Debug.Put ("Current/Target/Best_Delta: "));
+                     pragma Debug (Debug_Clocks, Debug.Put_Int64 (Current_Clock.Dotclock));
+                     pragma Debug (Debug_Clocks, Debug.Put ("/"));
+                     pragma Debug (Debug_Clocks, Debug.Put_Int64 (Target_Dotclock));
+                     pragma Debug (Debug_Clocks, Debug.Put ("/"));
+                     pragma Debug (Debug_Clocks, Debug.Put_Int64 (Best_Delta));
+                     pragma Debug (Debug_Clocks, Debug.Put_Line ("."));
+
+                  end if;
+               end loop;
+            end loop;
+         end loop;
+      end loop;
+
+      pragma Debug (Valid,     Debug.Put_Line ("Valid clock found."));
+      pragma Debug (Valid,     Debug.Put ("Best/Target/Delta: "));
+      pragma Debug (Valid,     Debug.Put_Int64 (Best_Clock.Dotclock));
+      pragma Debug (Valid,     Debug.Put ("/"));
+      pragma Debug (Valid,     Debug.Put_Int64 (Target_Dotclock));
+      pragma Debug (Valid,     Debug.Put ("/"));
+      pragma Debug (Valid,     Debug.Put_Int64 (Best_Delta));
+      pragma Debug (Valid,     Debug.Put_Line ("."));
+      pragma Debug (not Valid, Debug.Put_Line ("No valid clock found."));
+
+   end Calculate_Clock_Parameters;
+
+   procedure Program_DPLL
+     (PLL      : DPLLs;
+      Display  : Display_Type;
+      Clk      : Clock_Type)
+   with
+      Global => (In_Out => Registers.Register_State),
+      Pre => True,
+      Post => True
+   is
+      FP, Encoded_P1, Encoded_P2 : Word32;
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      FP :=
+         Shift_Left (Word32 (Clk.N - 2), FP_N_SHIFT)     or
+         Shift_Left (Word32 (Clk.M1 - 2), FP_M1_SHIFT)   or
+         Shift_Left (Word32 (Clk.M2 - 2), FP_M2_SHIFT);
+
+      Registers.Write (FP0 (PLL), FP);
+      Registers.Write (FP1 (PLL), FP);
+
+      Encoded_P1 := Shift_Left (1, Natural (Clk.P1) - 1);
+
+      if Clk.P2 = 5 or Clk.P2 = 7
+      then
+         Encoded_P2 := DPLL_P2_5_OR_7;
+      else
+         Encoded_P2 := DPLL_P2_10_OR_14;
+      end if;
+
+      Registers.Write
+         (Register => DPLL (PLL),
+          Value    => DPLL_Mode (Display)                            or
+                      Encoded_P2                                     or
+                      Shift_Left (Encoded_P1, DPLL_P1_DIVIDER_SHIFT) or
+                      Encoded_P1);
+   end Program_DPLL;
+
+   procedure On
+     (PLL      : in     T;
+      Port_Cfg : in     Port_Config;
+      Success  :    out Boolean)
+   is
+      Target_Clock : constant Frequency_Type :=
+        (if Port_Cfg.Display = DP then
+            DP_Symbol_Rate (Port_Cfg.DP.Bandwidth)
+         else
+            Port_Cfg.Mode.Dotclock);
+      Clk : Clock_Type;
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      Success := PLL in DPLLs;
+      Clk := Invalid_Clock;
+
+      if Success then
+         if Port_Cfg.Display = DP then
+            Success := True;
+            -- we use static values for DP
+            case Port_Cfg.DP.Bandwidth is
+               when DP_Bandwidth_1_62 =>
+                  Clk.N    :=  3;
+                  Clk.M1   := 14;
+                  Clk.M2   := 11;
+                  Clk.P1   :=  2;
+                  Clk.P2   := 10;
+               when DP_Bandwidth_2_7 =>
+                  Clk.N    :=  4;
+                  Clk.M1   := 16;
+                  Clk.M2   := 10;
+                  Clk.P1   :=  1;
+                  Clk.P2   := 10;
+               when others =>
+                  Success := False;
+            end case;
+         elsif Target_Clock <= 340_000_000 then
+            Calculate_Clock_Parameters
+              (Display           => Port_Cfg.Display,
+               Target_Dotclock   => Target_Clock,
+               -- should be, but doesn't has to be always the same:
+               Reference_Clock   => 120_000_000,
+               Best_Clock        => Clk,
+               Valid             => Success);
+         else
+            Success := False;
+            pragma Debug (Debug.Put ("WARNING: Targeted clock too high: "));
+            pragma Debug (Debug.Put_Int64 (Target_Clock));
+            pragma Debug (Debug.Put (" > "));
+            pragma Debug (Debug.Put_Int32 (340_000_000));
+            pragma Debug (Debug.New_Line);
+            pragma Debug (Debug.New_Line);
+         end if;
+      end if;
+
+      if Success then
+         Program_DPLL (PLL, Port_Cfg.Display, Clk);
+
+         Registers.Set_Mask (DPLL (PLL), DPLL_VCO_ENABLE);
+         Registers.Posting_Read (DPLL (PLL));
+         Time.U_Delay (150);
+      end if;
+   end On;
+
+   procedure Off (PLL : T)
+   is
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      if PLL in DPLLs then
+         Registers.Unset_Mask (DPLL (PLL), DPLL_VCO_ENABLE);
+      end if;
+   end Off;
+
+   ----------------------------------------------------------------------------
+
+   procedure Initialize
+   is
+   begin
+      PLLs :=
+        (DPLLs =>
+           (Use_Count   => 0,
+            Used_For_DP => False,
+            Link_Rate   => DP_Bandwidth'First,
+            Mode        => Invalid_Mode));
+   end Initialize;
+
+   procedure Alloc_Configurable
+     (Port_Cfg : in     Port_Config;
+      PLL      :    out T;
+      Success  :    out Boolean)
+   with
+      Pre => True
+   is
+      function Config_Matches (PE : PLL_State) return Boolean
+      is
+      begin
+         return
+            PE.Used_For_DP = (Port_Cfg.Display = DP) and
+            ((PE.Used_For_DP and PE.Link_Rate = Port_Cfg.DP.Bandwidth) or
+             (not PE.Used_For_DP and PE.Mode = Port_Cfg.Mode));
+      end Config_Matches;
+   begin
+      -- try to find shareable PLL
+      for P in DPLLs loop
+         Success := PLLs (P).Use_Count /= 0 and
+                     PLLs (P).Use_Count /= Count_Range'Last and
+                     Config_Matches (PLLs (P));
+         if Success then
+            PLL := P;
+            PLLs (PLL).Use_Count := PLLs (PLL).Use_Count + 1;
+            return;
+         end if;
+      end loop;
+
+      -- try to find free PLL
+      for P in DPLLs loop
+         if PLLs (P).Use_Count = 0 then
+            PLL := P;
+            On (PLL, Port_Cfg, Success);
+            if Success then
+               PLLs (PLL) :=
+                 (Use_Count   => 1,
+                  Used_For_DP => Port_Cfg.Display = DP,
+                  Link_Rate   => Port_Cfg.DP.Bandwidth,
+                  Mode        => Port_Cfg.Mode);
+            end if;
+            return;
+         end if;
+      end loop;
+
+      PLL := Invalid;
+   end Alloc_Configurable;
+
+   procedure Alloc
+     (Port_Cfg : in     Port_Config;
+      PLL      :    out T;
+      Success  :    out Boolean)
+   is
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      if Port_Cfg.Port = DIGI_A then
+         PLL := Invalid;
+         Success := True;
+      else
+         Alloc_Configurable (Port_Cfg, PLL, Success);
+      end if;
+   end Alloc;
+
+   procedure Free (PLL : T)
+   is
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      if PLL in DPLLs then
+         if PLLs (PLL).Use_Count /= 0 then
+            PLLs (PLL).Use_Count := PLLs (PLL).Use_Count - 1;
+            if PLLs (PLL).Use_Count = 0 then
+               Off (PLL);
+            end if;
+         end if;
+      end if;
+   end Free;
+
+   procedure All_Off
+   is
+   begin
+      pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+      for PLL in DPLLs loop
+         Off (PLL);
+      end loop;
+   end All_Off;
+
+   function Register_Value (PLL : T) return Word32
+   is
+   begin
+      return (if PLL = DPLL_B then 1 else 0);
+   end Register_Value;
+
+end HW.GFX.GMA.PLLs;
diff --git a/common/ironlake/hw-gfx-gma-plls.ads b/common/ironlake/hw-gfx-gma-plls.ads
new file mode 100644
index 0000000..8e7325e
--- /dev/null
+++ b/common/ironlake/hw-gfx-gma-plls.ads
@@ -0,0 +1,39 @@
+--
+-- Copyright (C) 2015-2016 secunet Security Networks AG
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; version 2 of the License.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+
+private package HW.GFX.GMA.PLLs
+with
+   Abstract_State => (State with Part_Of => GMA.State)
+is
+
+   -- XXX: Types should be private (but that triggers a bug in SPARK GPL 2016)
+   type T is (Invalid_PLL, DPLL_A, DPLL_B);
+   subtype DPLLs is T range DPLL_A .. DPLL_B;
+   Invalid : constant T := Invalid_PLL;
+
+   procedure Initialize
+   with
+      Global => (Output => State);
+
+   procedure Alloc
+     (Port_Cfg : in     Port_Config;
+      PLL      :    out T;
+      Success  :    out Boolean);
+
+   procedure Free (PLL : T);
+
+   procedure All_Off;
+
+   function Register_Value (PLL : T) return Word32;
+
+end HW.GFX.GMA.PLLs;
diff --git a/common/ironlake/hw-gfx-gma-port_detect.adb b/common/ironlake/hw-gfx-gma-port_detect.adb
new file mode 100644
index 0000000..4e26100
--- /dev/null
+++ b/common/ironlake/hw-gfx-gma-port_detect.adb
@@ -0,0 +1,160 @@
+--
+-- Copyright (C) 2016 secunet Security Networks AG
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; version 2 of the License.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA.Config;
+with HW.GFX.GMA.Registers;
+
+package body HW.GFX.GMA.Port_Detect
+is
+
+   PCH_ADPA_CRT_HPD_CHANNEL_MASK       : constant := 3 * 2 ** 24;
+   PCH_ADPA_CRT_HPD_ENABLE             : constant := 1 * 2 ** 23;
+
+   DP_PORT_DETECTED                    : constant := 1 * 2 **  2;
+   PCH_DIGI_PORT_DETECTED              : constant := 1 * 2 **  2;
+   PCH_LVDS_PORT_DETECTED              : constant := 1 * 2 **  1;
+
+   SHOTPLUG_CTL_DETECT_MASK            : constant := 16#0003_0303#;
+
+   type PCH_Digital_Port_Value is array (PCH_HDMI_Port) of Word32;
+   SHOTPLUG_CTL_HPD_INPUT_ENABLE : constant PCH_Digital_Port_Value :=
+     (PCH_HDMI_B => 1 * 2 **  4,
+      PCH_HDMI_C => 1 * 2 ** 12,
+      PCH_HDMI_D => 1 * 2 ** 20);
+   SHOTPLUG_CTL_SHORT_PULSE_MASK : constant PCH_Digital_Port_Value :=
+     (PCH_HDMI_B => 3 * 2 **  2,
+      PCH_HDMI_C => 3 * 2 ** 10,
+      PCH_HDMI_D => 3 * 2 ** 18);
+   SHOTPLUG_CTL_HPD_STATUS : constant PCH_Digital_Port_Value :=
+     (PCH_HDMI_B => 3 * 2 **  0,
+      PCH_HDMI_C => 3 * 2 **  8,
+      PCH_HDMI_D => 3 * 2 ** 16);
+   SHOTPLUG_CTL_LONG_DETECT : constant PCH_Digital_Port_Value :=
+     (PCH_HDMI_B => 1 * 2 **  1,
+      PCH_HDMI_C => 1 * 2 **  9,
+      PCH_HDMI_D => 1 * 2 ** 17);
+
+   type PCH_Digital_Regs is array (PCH_HDMI_Port) of Registers.Registers_Index;
+   PCH_HDMI : constant PCH_Digital_Regs :=
+     (PCH_HDMI_B => Registers.PCH_HDMIB,
+      PCH_HDMI_C => Registers.PCH_HDMIC,
+      PCH_HDMI_D => Registers.PCH_HDMID);
+   PCH_DP : constant PCH_Digital_Regs :=
+     (PCH_HDMI_B => Registers.PCH_DP_B,
+      PCH_HDMI_C => Registers.PCH_DP_C,
+      PCH_HDMI_D => Registers.PCH_DP_D);
+
+   procedure Initialize
+   is
+      Internal_Detected,
+      HDMI_Detected,
+      DP_Detected : Boolean;
+
+      type PCH_Port_To_GMA_Port is array (PCH_HDMI_Port) of Port_Type;
+      To_Digital_Port : constant PCH_Port_To_GMA_Port :=
+        (PCH_HDMI_B => Digital1,
+         PCH_HDMI_C => Digital2,
+         PCH_HDMI_D => Digital3);
+      To_DP_Port : constant PCH_Port_To_GMA_Port :=
+        (PCH_HDMI_B => DP1,
+         PCH_HDMI_C => DP2,
+         PCH_HDMI_D => DP3);
+   begin
+      -- PCH_DAC (_A)
+      Registers.Set_Mask
+        (Register => Registers.PCH_ADPA,
+         Mask     => PCH_ADPA_CRT_HPD_CHANNEL_MASK or   -- clear status
+                     PCH_ADPA_CRT_HPD_ENABLE);
+
+      case Config.Internal_Display is
+         when LVDS =>
+            -- PCH_LVDS
+            Registers.Is_Set_Mask
+              (Register => Registers.PCH_LVDS,
+               Mask     => PCH_LVDS_PORT_DETECTED,
+               Result   => Internal_Detected);
+         when DP =>
+            -- eDP
+            Registers.Is_Set_Mask
+              (Register => Registers.DP_CTL_A,
+               Mask     => DP_PORT_DETECTED,
+               Result   => Internal_Detected);
+         when None =>
+            Internal_Detected := False;
+      end case;
+      Config.Valid_Port (Internal) := Internal_Detected;
+
+      -- PCH_HDMI_[BCD], PCH_DP_[BCD] share hotplug registers
+      for PCH_Port in PCH_HDMI_Port loop
+         Registers.Is_Set_Mask
+           (Register => PCH_HDMI (PCH_Port),
+            Mask     => PCH_DIGI_PORT_DETECTED,
+            Result   => HDMI_Detected);
+         Config.Valid_Port (To_Digital_Port (PCH_Port)) := HDMI_Detected;
+
+         Registers.Is_Set_Mask
+           (Register => PCH_DP (PCH_Port),
+            Mask     => PCH_DIGI_PORT_DETECTED,
+            Result   => DP_Detected);
+         Config.Valid_Port (To_DP_Port (PCH_Port)) := DP_Detected;
+
+         if HDMI_Detected or DP_Detected then
+            Registers.Unset_And_Set_Mask
+              (Register    => Registers.SHOTPLUG_CTL,
+               Mask_Unset  => SHOTPLUG_CTL_DETECT_MASK or
+                              SHOTPLUG_CTL_SHORT_PULSE_MASK (PCH_Port),
+               Mask_Set    => SHOTPLUG_CTL_HPD_INPUT_ENABLE (PCH_Port) or
+                              SHOTPLUG_CTL_HPD_STATUS (PCH_Port));   -- clear
+         else
+            Registers.Unset_Mask
+              (Register => Registers.SHOTPLUG_CTL,
+               Mask     => SHOTPLUG_CTL_DETECT_MASK or
+                           SHOTPLUG_CTL_HPD_INPUT_ENABLE (PCH_Port));
+         end if;
+      end loop;
+   end Initialize;
+
+   procedure Hotplug_Detect (Port_Cfg : in Port_Config; Detected : out Boolean)
+   is
+      Ctl32 : Word32;
+      PCH_Port : constant GMA.PCH_Port :=
+        (case Port_Cfg.PCH_Port is
+            when PCH_DP_B  => PCH_HDMI_B,
+            when PCH_DP_C  => PCH_HDMI_C,
+            when PCH_DP_D  => PCH_HDMI_D,
+            when others    => Port_Cfg.PCH_Port);
+   begin
+      case PCH_Port is
+         when PCH_DAC =>
+            Registers.Read (Registers.PCH_ADPA, Ctl32, Verbose => False);
+            Ctl32 := Ctl32 and PCH_ADPA_CRT_HPD_CHANNEL_MASK;
+            Detected := Ctl32 = PCH_ADPA_CRT_HPD_CHANNEL_MASK;
+            if Ctl32 /= 0 then
+               Registers.Set_Mask (Registers.PCH_ADPA, Ctl32);
+            end if;
+         when PCH_HDMI_B .. PCH_HDMI_D =>
+            Registers.Read (Registers.SHOTPLUG_CTL, Ctl32, Verbose => False);
+            Detected := (Ctl32 and SHOTPLUG_CTL_LONG_DETECT (PCH_Port)) /= 0;
+
+            if (Ctl32 and SHOTPLUG_CTL_HPD_STATUS (PCH_Port)) /= 0 then
+               Registers.Unset_And_Set_Mask
+                 (Register    => Registers.SHOTPLUG_CTL,
+                  Mask_Unset  => SHOTPLUG_CTL_DETECT_MASK,
+                  Mask_Set    => SHOTPLUG_CTL_HPD_STATUS (PCH_Port));
+            end if;
+         when others =>
+            Detected := False;
+      end case;
+   end Hotplug_Detect;
+
+end HW.GFX.GMA.Port_Detect;
diff --git a/common/ironlake/hw-gfx-gma-power_and_clocks.ads b/common/ironlake/hw-gfx-gma-power_and_clocks.ads
new file mode 100644
index 0000000..644c0c7
--- /dev/null
+++ b/common/ironlake/hw-gfx-gma-power_and_clocks.ads
@@ -0,0 +1,17 @@
+--
+-- Copyright (C) 2016 secunet Security Networks AG
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; version 2 of the License.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA.Power_And_Clocks_Ironlake;
+
+private package HW.GFX.GMA.Power_And_Clocks
+   renames HW.GFX.GMA.Power_And_Clocks_Ironlake;
diff --git a/common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.adb b/common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.adb
new file mode 100644
index 0000000..e6fa3aa
--- /dev/null
+++ b/common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.adb
@@ -0,0 +1,54 @@
+--
+-- Copyright (C) 2016 secunet Security Networks AG
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; version 2 of the License.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+
+with HW.Time;
+with HW.GFX.GMA.Config;
+with HW.GFX.GMA.Registers;
+
+package body HW.GFX.GMA.Power_And_Clocks_Ironlake is
+
+   PCH_DREF_CONTROL_120MHZ_CPU_OUTPUT_MASK      : constant := 3 * 2 ** 13;
+   PCH_DREF_CONTROL_120MHZ_CPU_OUTPUT_SSC       : constant := 2 * 2 ** 13;
+   PCH_DREF_CONTROL_120MHZ_CPU_OUTPUT_NONSSC    : constant := 3 * 2 ** 13;
+   PCH_DREF_CONTROL_120MHZ_SSC_EN_MASK          : constant := 3 * 2 ** 11;
+   PCH_DREF_CONTROL_120MHZ_SSC_EN               : constant := 2 * 2 ** 11;
+   PCH_DREF_CONTROL_120MHZ_NONSSC_EN_MASK       : constant := 3 * 2 **  9;
+   PCH_DREF_CONTROL_120MHZ_NONSSC_EN            : constant := 2 * 2 **  9;
+   PCH_DREF_CONTROL_120MHZ_SSC4_EN_MASK         : constant := 3 * 2 **  7;
+   PCH_DREF_CONTROL_120MHZ_SSC4_EN              : constant := 2 * 2 **  7;
+   PCH_DREF_CONTROL_120MHZ_SSC4_DOWNSPREAD      : constant := 0 * 2 **  6;
+   PCH_DREF_CONTROL_120MHZ_SSC4_CENTERSPREAD    : constant := 1 * 2 **  6;
+   PCH_DREF_CONTROL_120MHZ_SSC_MODULATION_EN    : constant := 1 * 2 **  1;
+   PCH_DREF_CONTROL_120MHZ_SSC4_MODULATION_EN   : constant := 1 * 2 **  0;
+
+   procedure Initialize is
+   begin
+      -- ILK: enable non-spread spectrum clock, enable spread spectrum clock
+      Registers.Write
+        (Register => Registers.PCH_DREF_CONTROL,
+         Value    => PCH_DREF_CONTROL_120MHZ_SSC_EN or
+                     PCH_DREF_CONTROL_120MHZ_NONSSC_EN or
+                     PCH_DREF_CONTROL_120MHZ_SSC_MODULATION_EN);
+      Registers.Posting_Read (Registers.PCH_DREF_CONTROL);
+      Time.U_Delay (1);
+      if Config.Internal_Is_EDP then   -- TODO: check for presence
+         -- always use spread spectrum clock for CPU output
+         Registers.Set_Mask
+           (Register => Registers.PCH_DREF_CONTROL,
+            Mask     => PCH_DREF_CONTROL_120MHZ_CPU_OUTPUT_SSC);
+         Registers.Posting_Read (Registers.PCH_DREF_CONTROL);
+         Time.U_Delay (20);   -- DMI latency
+      end if;
+   end Initialize;
+
+end HW.GFX.GMA.Power_And_Clocks_Ironlake;
diff --git a/common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.ads b/common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.ads
new file mode 100644
index 0000000..f50388c
--- /dev/null
+++ b/common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.ads
@@ -0,0 +1,29 @@
+--
+-- Copyright (C) 2016 secunet Security Networks AG
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; version 2 of the License.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+
+private package HW.GFX.GMA.Power_And_Clocks_Ironlake is
+
+   procedure Initialize;
+
+   procedure Pre_All_Off is null;
+
+   procedure Post_All_Off is null;
+
+   procedure Power_Set_To (Configs : Configs_Type) is null;
+
+   procedure Power_Up (Old_Configs, New_Configs : Configs_Type) is null;
+
+   procedure Power_Down (Old_Configs, Tmp_Configs, New_Configs : Configs_Type)
+   is null;
+
+end HW.GFX.GMA.Power_And_Clocks_Ironlake;