tree d9ec6d4f4ef41a61a5c1716f3cc3d5a4eaeb1957
parent ab7088683624200265e67b40ac3d27d186ad4108
author Nico Huber <nico.h@gmx.de> 1779909010 +0200
committer Nico Huber <nico.h@gmx.de> 1785406342 +0000

gma adl: Add missing Alder Lake power & clock bits

Most notable changes are:
* ADL-P has different default CDClk frequency choices.
* There are new divisors for CDClk:
  + 3 (resulting in an odd `/ 1.5` for CDClk x2)
  + and 8.
* There are four DBUF slices now and we need to enable all of
  them (probably related to their position and distance to the
  display pipelines on the MBus).
* Programming of MBus ABOX credits is not needed anymore
  (Has_Mbus_Abox_Credits).
* The MBus configuration allows joining of DBUF slices. We
  enable this for our simple buffer allocation (Has_Mbus_Joining)
  (this could use a deeper investigation if we wanted to conserve
  power).

This is based on work by several authors that was originally
squashed into another commit:
https://review.coreboot.org/c/libgfxinit/+/67801/

Change-Id: I6402b9cdcc3571128d76026aa5c7c1bb48f8df33
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/510
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: Ada SPARK <gnatbot@sourcearcade.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>