)]}'
{
  "commit": "7769b52d61f14ce2f6a2953dc40d0ec07ab6fea2",
  "tree": "113f7bf9eb7088053b969a7f7af732db9ca6d222",
  "parents": [
    "f47ec05acb5d6eaf542a03856de2cf2af14b5846"
  ],
  "author": {
    "name": "Angel Pons",
    "email": "th3fanbus@gmail.com",
    "time": "Thu Sep 08 17:55:20 2022 +0200"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Sat Oct 01 13:53:04 2022 +0000"
  },
  "message": "hw-gfx-dp_info.adb: Fix reading `Aux_RD_Interval`\n\nStarting with DP v1.4, the definition of DPCD address 0xe was updated\nto include a new field. Bit 7 now indicates whether a DP receiver has\nan Extended Receiver Capability field, so `Aux_RD_Interval` is now in\nbits 6:0. This change is backwards compatible with older hardware, as\nthe defined values for `Aux_RD_Interval` range from 0 to 4, and bit 7\nis always zero.\n\nHowever, libgfxinit does not make sure the value is valid before using\nit in calculations, so the `EQ_Delay` function may return an extremely\nlarge value if bit 7 is set. To avoid this, add some masks to properly\nobtain the value for `Aux_RD_Interval`.\n\nChange-Id: If22d8dbc0517daeaa043ede30bf69e7a65ab154b\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/libgfxinit/+/67445\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Tim Wawrzynczak \u003cinforichland@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "bf099337f5fe5dddc3ff66d4ae106e66302958cf",
      "old_mode": 33188,
      "old_path": "common/hw-gfx-dp_info.adb",
      "new_id": "392fee13d291878d36604436ae87f638bf027b17",
      "new_mode": 33188,
      "new_path": "common/hw-gfx-dp_info.adb"
    }
  ]
}