commit 73ea03245445527a80b70e41cf4a910371014ca0
author Arthur Heymans <arthur@aheymans.xyz> Wed Mar 28 17:17:07 2018 +0200
committer Nico Huber <nico.h@gmx.de> Sun Jun 03 20:33:18 2018 +0000
tree 210fafb8ff5631b2946bdd4511271293b2f8a27c
parent d5198445517c361b30f4521e52b953d2a7928a70

gma: Add G45 support

The following ports are implemented: HDMI/DVI, VGA, LVDS and DP.

Tested with gfx_test and coreboot on a Thinkpad X200 (GM45).

Change-Id: Ifc05a1516329a61772af84558e5bfceb4d4ca277
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21295
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: Nico Huber <nico.h@gmx.de>

common/hw-gfx-gma.adb

diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb
index 809881a..c3b2238 100644
--- a/common/hw-gfx-gma.adb
+++ b/common/hw-gfx-gma.adb
@@ -334,6 +334,8 @@
          Audio_VID_DID : Word32;
       begin
          case Config.CPU is
+            when G45 =>
+               Registers.Read (Registers.G4X_AUD_VID_DID, Audio_VID_DID);
             when Haswell .. Skylake =>
                Registers.Read (Registers.AUD_VID_DID, Audio_VID_DID);
             when Ironlake .. Ivybridge =>
@@ -348,7 +350,10 @@
                when Ivybridge |
                     Sandybridge  => Audio_VID_DID = 16#8086_2806# or
                                     Audio_VID_DID = 16#8086_2805#,
-               when Ironlake     => Audio_VID_DID = 16#0000_0000#);
+               when Ironlake     => Audio_VID_DID = 16#0000_0000#,
+               when G45          => Audio_VID_DID = 16#8086_2801# or
+                                    Audio_VID_DID = 16#8086_2802# or
+                                    Audio_VID_DID = 16#8086_2803#);
       end Check_Platform;
 
       procedure Check_Platform_PCI (Success : out Boolean)
@@ -600,13 +605,13 @@
    is
       GGC_Reg : constant :=
         (case Config.CPU is
-            when Ironlake                 => 16#52#,
+            when G45 | Ironlake           => 16#52#,
             when Sandybridge .. Skylake   => 16#50#);
       GGC : Word16;
    begin
       Dev.Read16 (GGC, GGC_Reg);
       case Config.CPU is
-         when Ironlake =>
+         when G45 | Ironlake =>
             GTT_Size    := GTT_Size_Gen4 (GGC);
             Stolen_Size := Stolen_Size_Gen4 (GGC);
          when Sandybridge .. Haswell =>