)]}'
{
  "commit": "6dc7843082cf50e71001c9b24850bfbc86c3a39e",
  "tree": "95cf2104a7df44ca0ab46b8b4a0c3be9ccded8f4",
  "parents": [
    "3d7c33f5d24b27b1b140d91af89628ea3caa86ac"
  ],
  "author": {
    "name": "Arthur Heymans",
    "email": "arthur@aheymans.xyz",
    "time": "Thu Jun 18 09:34:50 2026 +0200"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Fri Jul 17 18:19:31 2026 +0000"
  },
  "message": "gma i945: Add Pineview support\n\nAdd Pineview desktop and mobile variants to the existing i945/Gen3\ncode path. Pineview is close to i945, but Linux\u0027 i915 treats a few\npieces differently and those differences need explicit handling:\n\n- add Pineview/Pineview_M CPU types and PCI IDs 0xa001/0xa011\n- detect Pineview-M as a mobile Gen3 platform so LVDS is exposed\n- decode Pineview GCFGC display clock selections for 133/167/200/\n  267/333/444 MHz CDClk\n- use the mobile/Pineview CLKCFG FSB encoding for HRAW clock\n- keep the separate BAR3 Gen3 GTT layout, but use the i965/G33 style\n  PTE encoding for Pineview\u0027s 36-bit DMA addresses\n- add a separate Pineview DPLL calculation/programming path instead of\n  widening the i945 PLL ranges; Pineview has a one-hot N encoding in\n  the frequency-parameter (FP) register, no M1 divider, M \u003d M2 + 2,\n  and P1 at bit 15\n\nThe i945 PLL type ranges and calculation path remain unchanged.\n\nTested with:\n  make clean \u0026\u0026 make DEBUG\u003d1 cnf\u003dconfigs/ironlake\n  make clean \u0026\u0026 make DEBUG\u003d1 cnf\u003dconfigs/ironlake_edp\n  make clean \u0026\u0026 make DEBUG\u003d1 cnf\u003dconfigs/i945\n\nTested with coreboot on Foxconn D41S.\n\nChange-Id: I8bda5d27e1c071bd59bd9a8751dc1ea31b25614f\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/515\nTested-by: Ada SPARK \u003cgnatbot@sourcearcade.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n",
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