gma i945: Add Pineview support
Add Pineview desktop and mobile variants to the existing i945/Gen3
code path. Pineview is close to i945, but Linux' i915 treats a few
pieces differently and those differences need explicit handling:
- add Pineview/Pineview_M CPU types and PCI IDs 0xa001/0xa011
- detect Pineview-M as a mobile Gen3 platform so LVDS is exposed
- decode Pineview GCFGC display clock selections for 133/167/200/
267/333/444 MHz CDClk
- use the mobile/Pineview CLKCFG FSB encoding for HRAW clock
- keep the separate BAR3 Gen3 GTT layout, but use the i965/G33 style
PTE encoding for Pineview's 36-bit DMA addresses
- add a separate Pineview DPLL calculation/programming path instead of
widening the i945 PLL ranges; Pineview has a one-hot N encoding in
the frequency-parameter (FP) register, no M1 divider, M = M2 + 2,
and P1 at bit 15
The i945 PLL type ranges and calculation path remain unchanged.
Tested with:
make clean && make DEBUG=1 cnf=configs/ironlake
make clean && make DEBUG=1 cnf=configs/ironlake_edp
make clean && make DEBUG=1 cnf=configs/i945
Tested with coreboot on Foxconn D41S.
Change-Id: I8bda5d27e1c071bd59bd9a8751dc1ea31b25614f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/515
Tested-by: Ada SPARK <gnatbot@sourcearcade.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template
index 0fd40c3..b784038 100644
--- a/common/hw-gfx-gma-config.ads.template
+++ b/common/hw-gfx-gma-config.ads.template
@@ -29,7 +29,7 @@
when Tigerlake => Tigerlake);
CPU_Last : constant CPU_Type :=
(case Gen is
- when I945 => I945GM,
+ when I945 => Pineview_M,
when G45 => GM45,
when Ironlake => Ivybridge,
when Haswell => Broadwell,
@@ -164,6 +164,10 @@
GMCH_I945GM : <i945bool> := Gen_I945 and then CPU = I945GM;
GMCH_GM965 : <g45bool> := Gen_G45 and then CPU = GM965;
+ CPU_Pineview : <i945bool> := Gen_I945 and then CPU = Pineview;
+ CPU_Pineview_M : <i945bool> := Gen_I945 and then CPU = Pineview_M;
+ CPU_Any_Pineview : <i945bool> := CPU_Pineview or CPU_Pineview_M;
+ GMCH_Gen3_Mobile : <i945bool> := GMCH_I945GM or CPU_Pineview_M;
GMCH_GM45 : <g45bool> := Gen_G45 and then CPU = GM45;
CPU_Ironlake : <ilkbool> := Gen_Ironlake and then CPU = Ironlake;
CPU_Sandybridge : <ilkbool> := Gen_Ironlake and then CPU = Sandybridge;
@@ -275,9 +279,9 @@
Has_GMCH_RawClk : <genbool> := Up_To_G45;
Has_GMCH_Mobile_VCO : <g45bool> := GMCH_GM45 or GMCH_GM965;
- ---------- I945-specific: ----
+ ---------- Gen3/i945-specific: ----
Has_I945_GTT_BAR : <genbool> := Gen_I945;
- Has_I945_Simple_GTT_PTE : <genbool> := Gen_I945;
+ Has_I945_Simple_GTT_PTE : <i945bool> := Gen_I945 and then not CPU_Any_Pineview;
Has_Gen3_Fences : <genbool> := Gen_I945;
-- Pre-i965: LVDS encoder can only source from Pipe B (Secondary)
LVDS_Needs_Pipe_B : <genbool> := Gen_I945;
@@ -628,6 +632,8 @@
when I945G => Device_Id = 16#2772#,
when GM965 => (Device_Id and 16#ffef#) = 16#2a02#,
when I945GM => Device_Id = 16#27a2# or Device_Id = 16#27ae#,
+ when Pineview => Device_Id = 16#a001#,
+ when Pineview_M => Device_Id = 16#a011#,
when G45 => (Device_Id and 16#ff02#) = 16#2e02#,
when GM45 => (Device_Id and 16#fffe#) = 16#2a42#,
when Ironlake => (Device_Id and 16#fff3#) = 16#0042#,