)]}'
{
  "commit": "6d971afd9b82fa79698f11f1f664db7347928d24",
  "tree": "4af44476b1e10532535acc0c38c6552efc112bd8",
  "parents": [
    "3f37cce66ef8b36932db08a1fb5e6486647da308"
  ],
  "author": {
    "name": "Matt DeVillier",
    "email": "matt.devillier@gmail.com",
    "time": "Mon Jul 06 11:04:54 2026 -0500"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Wed Jul 08 11:22:09 2026 +0000"
  },
  "message": "gma/Ironlake: Read eDP presence from hardware before ref clock setup\n\nCommit 1b99185ac327 (\"gma: Do detection and connectors init after\n`All_Off\u0027\") moved Port_Detect.Initialize after\nPower_And_Clocks.Initialize for all platforms. On Ironlake,\nPower_And_Clocks.Initialize gates eDP ref clock setup on\nValid_Port(eDP) from port detect, so the reorder skipped that setup\nand broke eDP on all boards using the Ironlake profile (including\nIvyBridge).\n\nFix this by reading DP_CTL_A bit 2 directly, as Port_Detect does,\ninstead of calling Valid_Port(eDP).\n\nTested google/link (IVB), verify display init working.\n\nChange-Id: Ie02afdbf3348566edb5ba3eb5e1717e09e47765a\nSigned-off-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/557\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b95f7ffe86d8e96504d13ec5cf2cbf97258b2225",
      "old_mode": 33188,
      "old_path": "common/ironlake/hw-gfx-gma-power_and_clocks.adb",
      "new_id": "f92379857f7a0f1d2b198d59e1c3842378228b70",
      "new_mode": 33188,
      "new_path": "common/ironlake/hw-gfx-gma-power_and_clocks.adb"
    }
  ]
}