gma/Ironlake: Read eDP presence from hardware before ref clock setup
Commit 1b99185ac327 ("gma: Do detection and connectors init after
`All_Off'") moved Port_Detect.Initialize after
Power_And_Clocks.Initialize for all platforms. On Ironlake,
Power_And_Clocks.Initialize gates eDP ref clock setup on
Valid_Port(eDP) from port detect, so the reorder skipped that setup
and broke eDP on all boards using the Ironlake profile (including
IvyBridge).
Fix this by reading DP_CTL_A bit 2 directly, as Port_Detect does,
instead of calling Valid_Port(eDP).
Tested google/link (IVB), verify display init working.
Change-Id: Ie02afdbf3348566edb5ba3eb5e1717e09e47765a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/557
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: Nico Huber <nico.h@gmx.de>
diff --git a/common/ironlake/hw-gfx-gma-power_and_clocks.adb b/common/ironlake/hw-gfx-gma-power_and_clocks.adb
index b95f7ff..f923798 100644
--- a/common/ironlake/hw-gfx-gma-power_and_clocks.adb
+++ b/common/ironlake/hw-gfx-gma-power_and_clocks.adb
@@ -32,7 +32,11 @@
PCH_DREF_CONTROL_120MHZ_SSC_MODULATION_EN : constant := 1 * 2 ** 1;
PCH_DREF_CONTROL_120MHZ_SSC4_MODULATION_EN : constant := 1 * 2 ** 0;
+ -- Same as Port_Detect.Initialize (DP_CTL_A, bit 2).
+ DP_PORT_DETECTED : constant := 1 * 2 ** 2;
+
procedure Initialize is
+ eDP_Detected : Boolean;
begin
-- ILK: enable non-spread spectrum clock, enable spread spectrum clock
Registers.Write
@@ -42,7 +46,12 @@
PCH_DREF_CONTROL_120MHZ_SSC_MODULATION_EN);
Registers.Posting_Read (Registers.PCH_DREF_CONTROL);
Time.U_Delay (1);
- if Config.Valid_Port (eDP) then
+
+ Registers.Is_Set_Mask
+ (Register => Registers.DP_CTL_A,
+ Mask => DP_PORT_DETECTED,
+ Result => eDP_Detected);
+ if eDP_Detected then
-- always use spread spectrum clock for CPU output
Registers.Set_Mask
(Register => Registers.PCH_DREF_CONTROL,