tree ec1de6dfe94c929ce1941db6bb9fef0d4f8b8470
parent d920d2597727183d3a0c2921f275c615bf610a28
author Nico Huber <nico.huber@secunet.com> 1711015788 +0000
committer Nico Huber <nico.h@gmx.de> 1783945678 +0000

gma broxton: Avoid invalid state of PWM HW counter

This implements display workaround #0854 [1]. The original descrip-
tion only mentions that the PWM might stop in a logical high state.
Which shouldn't be a problem, as long as there is a separate signal
toggling the on/off state of the backlight.

However, it turns out that with the clock gating, the PWM counter is
also not reset when the frequency divider in BLC_PWM_FREQ is updated.
This can result in a counter value out of range, effectively leaving
the PWM signal low until a 32-bit overflow at 19.2 MHz (almost 4min).

[1] https://cdrdv2-public.intel.com/685505/intel-gfx-prm-osrc-bxt-vol08-workarounds_7.pdf
    May 2017, Revision 1.0

Change-Id: I38b51c5afb072fb3c7b87caca028adba557aeebf
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/539
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>