)]}'
{
  "commit": "5603337c2606f3734287004c0c6780da223953c4",
  "tree": "ec1de6dfe94c929ce1941db6bb9fef0d4f8b8470",
  "parents": [
    "d920d2597727183d3a0c2921f275c615bf610a28"
  ],
  "author": {
    "name": "Nico Huber",
    "email": "nico.huber@secunet.com",
    "time": "Thu Mar 21 10:09:48 2024 +0000"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Mon Jul 13 12:27:58 2026 +0000"
  },
  "message": "gma broxton: Avoid invalid state of PWM HW counter\n\nThis implements display workaround #0854 [1]. The original descrip-\ntion only mentions that the PWM might stop in a logical high state.\nWhich shouldn\u0027t be a problem, as long as there is a separate signal\ntoggling the on/off state of the backlight.\n\nHowever, it turns out that with the clock gating, the PWM counter is\nalso not reset when the frequency divider in BLC_PWM_FREQ is updated.\nThis can result in a counter value out of range, effectively leaving\nthe PWM signal low until a 32-bit overflow at 19.2 MHz (almost 4min).\n\n[1] https://cdrdv2-public.intel.com/685505/intel-gfx-prm-osrc-bxt-vol08-workarounds_7.pdf\n    May 2017, Revision 1.0\n\nChange-Id: I38b51c5afb072fb3c7b87caca028adba557aeebf\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/539\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "279071a1134102109e98de47683c53d311195fca",
      "old_mode": 33188,
      "old_path": "common/broxton/hw-gfx-gma-power_and_clocks.adb",
      "new_id": "73192ff65b315e5e5fcbe2732337320e272d8728",
      "new_mode": 33188,
      "new_path": "common/broxton/hw-gfx-gma-power_and_clocks.adb"
    }
  ]
}