commit 4be2e75658602356cfa2fab5cdb1157ab27f1b3a
author Tim Wawrzynczak <twawrzynczak@chromium.org> Fri Sep 09 10:37:06 2022 -0600
committer Nico Huber <nico.h@gmx.de> Thu Feb 29 15:11:40 2024 +0000
tree 8a81a8454444ea2328254ecb25f84523f4541b47
parent 87469f2ec0028f26ea54021ad02a94f9b1ee7759

gma: Update transcoder setup for TGL

Tiger Lake requires configuration (but not enablement) of the
transcoder during the modeset sequence itself, so this patch adds a
new Config option to accommodate that and refactors the transcoder
setup into two new procedures.  There should be no functional
differences for other generations.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I4d7e2a24c54fcd9994f44bb0b10924dce48068e5
Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/67493
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>

common/hw-gfx-gma-transcoder.ads

diff --git a/common/hw-gfx-gma-transcoder.ads b/common/hw-gfx-gma-transcoder.ads
index 4a24996..c89ee57 100644
--- a/common/hw-gfx-gma-transcoder.ads
+++ b/common/hw-gfx-gma-transcoder.ads
@@ -18,6 +18,8 @@
 private package HW.GFX.GMA.Transcoder
 is
 
+   procedure Enable_Pipe_Clock (Pipe : Pipe_Index; Port_Cfg : Port_Config);
+   procedure Configure (Pipe : Pipe_Index; Port_Cfg : Port_Config; Scale : Boolean);
    procedure Setup (Pipe : Pipe_Index; Port_Cfg : Port_Config);
    procedure On
      (Pipe     : Pipe_Index;
@@ -52,6 +54,7 @@
          DDI_FUNC_CTL   : Registers.Registers_Index;
          MSA_MISC       : Registers.Registers_Index;
          CLK_SEL        : Registers.Registers_Invalid_Index;
+         PIPE_ARB_CTL   : Registers.Registers_Invalid_Index;
       end record;
 
    type Transcoder_Array is array (Transcoder_Index) of Transcoder_Regs;
@@ -100,7 +103,8 @@
          LINK_N1        => Registers.PIPE_EDP_LINK_N1,
          DDI_FUNC_CTL   => Registers.PIPE_EDP_DDI_FUNC_CTL,
          MSA_MISC       => Registers.PIPE_EDP_MSA_MISC,
-         CLK_SEL        => Registers.Invalid_Register),
+         CLK_SEL        => Registers.Invalid_Register,
+         PIPE_ARB_CTL   => Registers.Invalid_Register),
       Trans_A =>
         (HTOTAL         => Registers.HTOTAL_A,
          HBLANK         => Registers.HBLANK_A,
@@ -115,7 +119,8 @@
          LINK_N1        => PIPE_LINK_N1 (0),
          DDI_FUNC_CTL   => Registers.PIPEA_DDI_FUNC_CTL,
          MSA_MISC       => Registers.PIPEA_MSA_MISC,
-         CLK_SEL        => Registers.TRANSA_CLK_SEL),
+         CLK_SEL        => Registers.TRANSA_CLK_SEL,
+         PIPE_ARB_CTL   => Registers.PIPEA_ARB_CTL),
       Trans_B =>
         (HTOTAL         => Registers.HTOTAL_B,
          HBLANK         => Registers.HBLANK_B,
@@ -130,7 +135,8 @@
          LINK_N1        => PIPE_LINK_N1 (1),
          DDI_FUNC_CTL   => Registers.PIPEB_DDI_FUNC_CTL,
          MSA_MISC       => Registers.PIPEB_MSA_MISC,
-         CLK_SEL        => Registers.TRANSB_CLK_SEL),
+         CLK_SEL        => Registers.TRANSB_CLK_SEL,
+         PIPE_ARB_CTL   => Registers.PIPEB_ARB_CTL),
       Trans_C =>
         (HTOTAL         => Registers.HTOTAL_C,
          HBLANK         => Registers.HBLANK_C,
@@ -145,6 +151,7 @@
          LINK_N1        => Registers.PIPEC_LINK_N1,
          DDI_FUNC_CTL   => Registers.PIPEC_DDI_FUNC_CTL,
          MSA_MISC       => Registers.PIPEC_MSA_MISC,
-         CLK_SEL        => Registers.TRANSC_CLK_SEL));
+         CLK_SEL        => Registers.TRANSC_CLK_SEL,
+         PIPE_ARB_CTL   => Registers.PIPEC_ARB_CTL));
 
 end HW.GFX.GMA.Transcoder;