gma: Update transcoder setup for TGL
Tiger Lake requires configuration (but not enablement) of the
transcoder during the modeset sequence itself, so this patch adds a
new Config option to accommodate that and refactors the transcoder
setup into two new procedures. There should be no functional
differences for other generations.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I4d7e2a24c54fcd9994f44bb0b10924dce48068e5
Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/67493
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template
index 0bc7d80..dd6c2f8 100644
--- a/common/hw-gfx-gma-config.ads.template
+++ b/common/hw-gfx-gma-config.ads.template
@@ -196,7 +196,7 @@
Has_Tertiary_Pipe : <ilkbool> := Ivybridge_On;
Disable_Trickle_Feed : <genbool> := not Gen_Haswell;
Pipe_Enabled_Workaround : <hswbool> := CPU_Broadwell;
- Has_EDP_Transcoder : <genbool> := Haswell_On;
+ Has_EDP_Transcoder : <genbool> := Haswell_On and not Tigerlake_On;
Use_PDW_For_EDP_Scaling : <hswbool> := CPU_Haswell;
Has_Pipe_DDI_Func : <genbool> := Haswell_On;
Has_Trans_Clk_Sel : <genbool> := Haswell_On;
@@ -212,6 +212,9 @@
Has_GMCH_VGACNTRL : <genbool> := Gen_G45;
Has_GMCH_PFIT_CONTROL : <genbool> := Gen_G45;
+ ----------- Transcoder -------
+ Need_Early_Transcoder_Setup : <genbool> := Tigerlake_On;
+
--------- Panel power: -------
Has_PP_Write_Protection : <genbool> := Up_To_Ironlake;
Has_PP_Port_Select : <genbool> := Up_To_Ironlake;
@@ -263,6 +266,8 @@
-- might be disabled by x4 eDP:
Has_DDI_E : <hswsklbool> := Has_DDI_D;
+ Has_TGL_DDI_Select : <genbool> := Tigerlake_On;
+
Has_DDI_Buffer_Trans : <genbool> := Haswell_On and not Has_DDI_PHYs;
Has_Low_Voltage_Swing : <genbool> := Broxton_On;
Has_Iboost_Config : <genbool> := Skylake_On;