gma: Make PCI config access mandatory
We always have access to the PCI device now. So we can drop the old
`Check_Platform ()` that relied on the MMIO space only. Some paths
also get simplified, as we don't need the `PCI_Usable` flag anymore.
Change-Id: I29f2d79484eae2f84b8547e52869d8f6246024a0
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/537
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/common/g45/hw-gfx-gma-power_and_clocks.adb b/common/g45/hw-gfx-gma-power_and_clocks.adb
index e082a6d..3c73dcc 100644
--- a/common/g45/hw-gfx-gma-power_and_clocks.adb
+++ b/common/g45/hw-gfx-gma-power_and_clocks.adb
@@ -102,7 +102,7 @@
is
use type HW.Word16;
- Tmp_Clk : Int64 := 0;
+ Tmp_Clk : Int64;
VCO : Int64;
Divisors : Div_Array;
@@ -110,23 +110,21 @@
GCFGC : Word16;
CDClk_Sel : Natural range 0 .. 7;
begin
- if PCI_Usable then
- Get_VCO (VCO, Divisors);
- PCI_Read16 (GCFGC, 16#f0#);
- if Config.GMCH_GM965 then
- -- Linux i965gm_get_cdclk: cdclk_sel = ((tmp >> 8) & 0x1f) - 1
- if (Shift_Right (GCFGC, 8) and 16#1f#) in 1 .. 3 then
- CDClk_Sel := Natural (Shift_Right (GCFGC, 8) and 16#1f#) - 1;
- else
- CDClk_Sel := Div_Array'Last;
- end if;
- elsif Config.Has_GMCH_Mobile_VCO then
- CDClk_Sel := Natural (Shift_Right (GCFGC, 12) and 1);
+ Get_VCO (VCO, Divisors);
+ PCI_Read16 (GCFGC, 16#f0#);
+ if Config.GMCH_GM965 then
+ -- Linux i965gm_get_cdclk: cdclk_sel = ((tmp >> 8) & 0x1f) - 1
+ if (Shift_Right (GCFGC, 8) and 16#1f#) in 1 .. 3 then
+ CDClk_Sel := Natural (Shift_Right (GCFGC, 8) and 16#1f#) - 1;
else
- CDClk_Sel := Natural (Shift_Right (GCFGC, 4) and 7);
+ CDClk_Sel := Div_Array'Last;
end if;
- Tmp_Clk := VCO / Divisors (CDClk_Sel);
+ elsif Config.Has_GMCH_Mobile_VCO then
+ CDClk_Sel := Natural (Shift_Right (GCFGC, 12) and 1);
+ else
+ CDClk_Sel := Natural (Shift_Right (GCFGC, 4) and 7);
end if;
+ Tmp_Clk := VCO / Divisors (CDClk_Sel);
if Tmp_Clk in Config.CDClk_Range then
CDClk := Tmp_Clk;
diff --git a/common/hw-gfx-gma-registers.adb b/common/hw-gfx-gma-registers.adb
index 41aae0a..d54949b 100644
--- a/common/hw-gfx-gma-registers.adb
+++ b/common/hw-gfx-gma-registers.adb
@@ -353,14 +353,6 @@
pragma Debug (Verbose, Debug.Put_Line (Registers_Index'Image (Register)));
end Read;
- procedure Read_AUD_VID_DID (Value : out Word32)
- is
- begin
- Regs.Read
- (Value,
- Registers_Range (Config.AUD_VID_DID_Offset / Register_Width));
- end Read_AUD_VID_DID;
-
----------------------------------------------------------------------------
-- Read a specific register to post a previous write
diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads
index 1245c9f..df9f11f 100644
--- a/common/hw-gfx-gma-registers.ads
+++ b/common/hw-gfx-gma-registers.ads
@@ -2311,13 +2311,6 @@
Pre => True,
Post => True;
- procedure Read_AUD_VID_DID (Value : out Word32)
- with
- Global => (In_Out => Register_State),
- Depends => ((Value, Register_State) => Register_State),
- Pre => True,
- Post => True;
-
procedure Write
(Register : Registers_Index;
Value : Word32;
diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb
index fc8005f..449f7b3 100644
--- a/common/hw-gfx-gma.adb
+++ b/common/hw-gfx-gma.adb
@@ -38,7 +38,6 @@
with Refined_State =>
(State =>
(Config.Variable,
- PCI_Usable,
Dev.Address_State,
Registers.Address_State,
PCode.Mailbox_Ready,
@@ -495,8 +494,7 @@
(Dev.PCI_State, Port_IO.State,
Registers.Register_State, Registers.GTT_State),
Output =>
- (PCI_Usable,
- Config.Variable,
+ (Config.Variable,
Dev.Address_State,
Registers.Address_State,
PCode.Mailbox_Ready,
@@ -514,32 +512,6 @@
Now : constant Time.T := Time.Now;
- procedure Check_Platform (Success : out Boolean)
- is
- Audio_VID_DID : Word32;
- begin
- if Config.Gen_I945 or Config.GMCH_GM965 then
- -- i945 and GM965 have no integrated audio DID to verify.
- Success := True;
- return;
- end if;
- Registers.Read_AUD_VID_DID (Audio_VID_DID);
- Success :=
- ((Config.Gen_Broxton and Audio_VID_DID = 16#8086_280a#) or
- (Config.CPU_Kabylake and Audio_VID_DID = 16#8086_280b#) or
- (Config.CPU_Skylake and Audio_VID_DID = 16#8086_2809#) or
- (Config.CPU_Broadwell and Audio_VID_DID = 16#8086_2808#) or
- (Config.CPU_Haswell and Audio_VID_DID = 16#8086_2807#) or
- ((Config.CPU_Ivybridge or
- Config.CPU_Sandybridge) and (Audio_VID_DID = 16#8086_2806# or
- Audio_VID_DID = 16#8086_2805#)) or
- (Config.CPU_Ironlake and Audio_VID_DID = 16#0000_0000#) or
- (Config.Gen_G45 and (Audio_VID_DID = 16#8086_2801# or
- Audio_VID_DID = 16#8086_2802# or
- Audio_VID_DID = 16#8086_2803#)) or
- (Config.CPU_Tigerlake and (Audio_VID_DID = 16#8086_2812#)));
- end Check_Platform;
-
procedure Check_Platform_PCI (Success : out Boolean)
is
use type HW.Word16;
@@ -556,7 +528,6 @@
pragma Debug (Debug.Set_Register_Write_Delay (Write_Delay));
- PCI_Usable := False;
Linear_FB_Base := 0;
PCode.Mailbox_Ready := False;
Wait_For_HPD := HPD_Type'(others => False);
@@ -575,10 +546,15 @@
PLLs.Initialize;
Dev.Initialize (Success);
+ pragma Debug (not Success, Debug.Put_Line ("ERROR: Couldn't initialize PCI dev."));
if Success then
Check_Platform_PCI (Success);
- if Success then
+ pragma Debug (not Success, Debug.Put_Line ("ERROR: Incompatible GPU."));
+ end if;
+
+ if Success then
+ if HW.Config.Dynamic_MMIO then
if Config.Has_I945_GTT_BAR then
-- i945: MMIO is on BAR0, GTT is on separate BAR3
Dev.Map (PCI_MMIO_Base, PCI.Res0);
@@ -589,30 +565,22 @@
Dev.Map
(PCI_GTT_Base, PCI.Res0, Offset => Config.MMIO_GTT_Offset);
end if;
+
if PCI_MMIO_Base /= 0 and PCI_GTT_Base /= 0 then
Registers.Set_Register_Base (PCI_MMIO_Base, PCI_GTT_Base);
- PCI_Usable := True;
else
- pragma Debug (Debug.Put_Line
- ("ERROR: Couldn't map resource0."));
- Success := Config.Default_MMIO_Base_Set;
+ pragma Debug (Debug.Put_Line ("ERROR: Couldn't map resource0."));
+ Success := False;
end if;
- end if;
- else
- pragma Debug (Debug.Put_Line
- ("WARNING: Couldn't initialize PCI dev."));
- Success := Config.Default_MMIO_Base_Set;
-
- if Success then
- Check_Platform (Success);
+ else
+ Success := Config.Default_MMIO_Base_Set;
+ pragma Debug (not Success, Debug.Put_Line ("ERROR: MMIO base not set."));
end if;
end if;
Panel.Static_Init; -- early for flow analysis
if not Success then
- pragma Debug (Debug.Put_Line ("ERROR: Incompatible CPU or PCH."));
-
Initialized := False;
return;
end if;
diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads
index 76424d6..c33c513 100644
--- a/common/hw-gfx-gma.ads
+++ b/common/hw-gfx-gma.ads
@@ -276,11 +276,10 @@
private
- PCI_Usable : Boolean with Part_Of => State;
use type HW.PCI.Index;
procedure PCI_Read16 (Value : out Word16; Offset : HW.PCI.Index)
with
- Pre => PCI_Usable and Offset mod 2 = 0;
+ Pre => Offset mod 2 = 0;
----------------------------------------------------------------------------
diff --git a/common/i945/hw-gfx-gma-power_and_clocks.adb b/common/i945/hw-gfx-gma-power_and_clocks.adb
index 23d5476..2f6404a 100644
--- a/common/i945/hw-gfx-gma-power_and_clocks.adb
+++ b/common/i945/hw-gfx-gma-power_and_clocks.adb
@@ -49,28 +49,19 @@
GC_DISPLAY_CLOCK_320_MHZ : constant Word16 := 4 * 2 ** 4;
GCFGC : Word16;
- Tmp_Clk : Frequency_Type := 200_000_000;
begin
if Config.GMCH_I945GM then
- if PCI_Usable then
- PCI_Read16 (GCFGC, 16#f0#);
- if (GCFGC and GC_LOW_FREQUENCY_ENABLE) /= 0 then
- Tmp_Clk := 133_333_333;
- elsif (GCFGC and GC_DISPLAY_CLOCK_MASK) = GC_DISPLAY_CLOCK_320_MHZ then
- Tmp_Clk := 320_000_000;
- else
- Tmp_Clk := 200_000_000;
- end if;
+ PCI_Read16 (GCFGC, 16#f0#);
+ if (GCFGC and GC_LOW_FREQUENCY_ENABLE) /= 0 then
+ CDClk := 133_333_333;
+ elsif (GCFGC and GC_DISPLAY_CLOCK_MASK) = GC_DISPLAY_CLOCK_320_MHZ then
+ CDClk := 320_000_000;
+ else
+ CDClk := 200_000_000;
end if;
else
-- i945G desktop: fixed 400 MHz
- Tmp_Clk := 400_000_000;
- end if;
-
- if Tmp_Clk in Config.CDClk_Range then
- CDClk := Tmp_Clk;
- else
- CDClk := 200_000_000;
+ CDClk := 400_000_000;
end if;
end Get_CDClk;