haswell: Make VGA on FDI work
Attempting to light up a 1920x1080 monitor through VGA with libgfxinit
on Haswell would either hang the system or show garbage on the monitor.
This was due to two different problems around FDI initialization code.
The system would only hang if libgfxinit was the first program to light
up a monitor on VGA. This is because no one had performed the required
FDI mPHY initialization that is described on the Haswell graphics PRMs.
Add it to libgfxinit alongside some code to disable bending CLKOUT_DP.
Even with the FDI mPHY initialization in place, the garbage would still
be present on the VGA monitor. Digital interfaces were not affected.
By carefully dumping and comparing the display registers of a good and
a bad case, it was determinted that the fault was due to a mismatched
link width for FDI. The FDI link between the iGPU and the Lynxpoint PCH
can operate in either x1 or x2 width, depending on the bandwidth needs
of the monitor on the PCH's VGA port. To drive a 1920x1080 VGA monitor,
it is necessary to use both FDI lanes. Moreover, both ends of the link
need to be configured to use the same link width. However, the wrong
link width was assumed when configuring the display pipe, because
`DP.Lane_Count` was used unconditionally instead of `FDI.Lane_Count`.
After fixing both issues, gfx_test is able to light up a 1920x1080 VGA
monitor on the Asrock B85M Pro4 successfully, even after a S3 resume.
Change-Id: Ieabe3b7f947be2ef488ddb57bfeae85fa055d360
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/41343
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/common/haswell/hw-gfx-gma-power_and_clocks_haswell.adb b/common/haswell/hw-gfx-gma-power_and_clocks_haswell.adb
index e261ace..fa52899 100644
--- a/common/haswell/hw-gfx-gma-power_and_clocks_haswell.adb
+++ b/common/haswell/hw-gfx-gma-power_and_clocks_haswell.adb
@@ -21,6 +21,7 @@
with HW.GFX.GMA.PCode;
with HW.GFX.GMA.Registers;
with HW.GFX.GMA.Transcoder;
+with HW.GFX.GMA.PCH.Lynxpoint;
package body HW.GFX.GMA.Power_And_Clocks_Haswell is
@@ -275,6 +276,13 @@
Config.CDClk := CDClk;
end Set_CDClk;
+ procedure Post_All_Off is
+ begin
+ -- Reset CLKOUT_DP to disabled state
+ PCH.Lynxpoint.Disable_Clkout_DP;
+ PCH.Lynxpoint.Unbend_Clkout_DP;
+ end Post_All_Off;
+
procedure Initialize
is
CDClk : Config.CDClk_Range;
@@ -289,6 +297,11 @@
Set_CDClk (Config.Default_CDClk_Freq);
Config.Raw_Clock := Config.Default_RawClk_Freq;
+
+ -- Configure CLKOUT_DP for FDI
+ if Config.Has_DDI_E then
+ PCH.Lynxpoint.Enable_Clkout_DP_And_FDI_mPHY;
+ end if;
end Initialize;
procedure Limit_Dotclocks