gma broxton: Start off with power domains and CDClk
It's close to the respective code for Skylake but still different
enough for a separate implementation. We start with a default CDClk
of 288MHz which is enough for resolutions up to 2560x1600.
Change-Id: I44364191236f421b2b89c9a019a50713f7c20525
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18243
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/common/broxton/Makefile.inc b/common/broxton/Makefile.inc
index 247fca1..c4360ec 100644
--- a/common/broxton/Makefile.inc
+++ b/common/broxton/Makefile.inc
@@ -1,4 +1,6 @@
+gfxinit-y += hw-gfx-gma-ddi_phy.ads
gfxinit-y += hw-gfx-gma-plls.adb
gfxinit-y += hw-gfx-gma-plls.ads
+gfxinit-y += hw-gfx-gma-power_and_clocks.adb
gfxinit-y += hw-gfx-gma-power_and_clocks.ads
gfxinit-y += hw-gfx-gma-spll.ads