gma g45: Add support for Intel GM965 (Crestline)
Add GM965 as a new CPU type under the G45 generation. GM965 shares
the GMCH display architecture with G45/GM45 (no PCH, same connector
registers) but differs in PLL limits, VCO/CDClk tables, and register
field encoding.
Key differences from G45/GM45:
- PLL limits: Uses i9xx limits (VCO 1.4-2.8 GHz) instead of g4x
limits. Add I9XX_LVDS_Limits; refactor Calculate_Clock_Parameters
to take Limits as a parameter, with a new Select_Limits function.
- VCO: Uses Crestline (CL) VCO tables with different frequencies
and divisors than GM45's Cantiga (CTG) tables.
- CDClk: GCFGC register decoding uses bits 12:8 minus 1 (3 possible
divisor selections), unlike GM45's single bit 12.
- No native DisplayPort (SDVO B/C only).
- No HD Audio (G4X_AUD_VID_DID reads as 0).
- Has integrated LVDS transmitter (mobile platform).
- PCI IDs: 0x2a02 (I965_GM), 0x2a12 (I965_GME).
All implementation details cross-referenced against the Linux kernel
i915 driver (intel_dpll.c, intel_cdclk.c, intel_display_device.c).
Change-Id: I0d5d698cc1c2aa84778f0fc6c2752cb5ce4f1cb2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/499
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: Nico Huber <nico.h@gmx.de>
diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template
index 93e7ca4..a041e2c 100644
--- a/common/hw-gfx-gma-config.ads.template
+++ b/common/hw-gfx-gma-config.ads.template
@@ -19,7 +19,7 @@
CPU_First : constant CPU_Type :=
(case Gen is
when I945 => I945G,
- when G45 => G45,
+ when G45 => GM965,
when Ironlake => Ironlake,
when Haswell => Haswell,
when Broxton => Broxton,
@@ -159,6 +159,7 @@
Tigerlake_On : <genbool> := Gen >= Tigerlake;
GMCH_I945GM : <i945bool> := Gen_I945 and then CPU = I945GM;
+ GMCH_GM965 : <g45bool> := Gen_G45 and then CPU = GM965;
GMCH_GM45 : <g45bool> := Gen_G45 and then CPU = GM45;
CPU_Ironlake : <ilkbool> := Gen_Ironlake and then CPU = Ironlake;
CPU_Sandybridge : <ilkbool> := Gen_Ironlake and then CPU = Sandybridge;
@@ -268,7 +269,7 @@
---------- Clocks: -----------
Has_GMCH_RawClk : <genbool> := Up_To_G45;
- Has_GMCH_Mobile_VCO : <g45bool> := GMCH_GM45;
+ Has_GMCH_Mobile_VCO : <g45bool> := GMCH_GM45 or GMCH_GM965;
---------- I945-specific: ----
Has_I945_GTT_BAR : <genbool> := Gen_I945;
@@ -454,6 +455,19 @@
GMA_Base_Is_64bit : constant Boolean := Config.Tigerlake_On;
+ AUD_VID_DID_Offset : <ilkhswvar> Natural :=
+ (if Gen_G45 then 16#06_2020#
+ elsif Gen_Ironlake then 16#0e_5020#
+ else 16#06_5020#);
+
+ -- Default 32-bit GTT offset for static MMIO instantiation.
+ Default_MMIO_GTT_32_Offset : constant Natural :=
+ (if Has_I945_GTT_BAR then 16#00_0000# else 16#20_0000#);
+ MMIO_GTT_32_Offset : <g45var> Natural :=
+ (if GMCH_GM965 then 16#0008_0000# else Default_MMIO_GTT_32_Offset);
+ MMIO_GTT_64_Offset : constant Natural := 16#80_0000#;
+ MMIO_GTT_Offset : <g45hswvar> Natural :=
+ (if Has_64bit_GTT then MMIO_GTT_64_Offset else MMIO_GTT_32_Offset);
GTT_PTE_Size : <hswvar> Natural := (if Has_64bit_GTT then 8 else 4);
Fence_Base : <i945ilkvar> Natural :=
@@ -607,6 +621,7 @@
return Boolean is
(case CPU is
when I945G => Device_Id = 16#2772#,
+ when GM965 => (Device_Id and 16#ffef#) = 16#2a02#,
when I945GM => Device_Id = 16#27a2# or Device_Id = 16#27ae#,
when G45 => (Device_Id and 16#ff02#) = 16#2e02#,
when GM45 => (Device_Id and 16#fffe#) = 16#2a42#,