gma: Add support for ULX variants
On Haswell and Broadwell, the ULX variants differ only in the available
CD clock frequencies and, on Haswell, the maximum DP link rate. On newer
generations (Skylake+), they differ only in output buffer tuning.
Also update the PCI IDs from Haswell to Skylake.
Still untested, which was the original reason to skip ULX.
Change-Id: I08e6689ff8c0f2d58b51363886d4cab956f44e03
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/31452
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/common/haswell/hw-gfx-gma-plls.adb b/common/haswell/hw-gfx-gma-plls.adb
index 3a91bdd..526a90a 100644
--- a/common/haswell/hw-gfx-gma-plls.adb
+++ b/common/haswell/hw-gfx-gma-plls.adb
@@ -1,5 +1,5 @@
--
--- Copyright (C) 2015-2016 secunet Security Networks AG
+-- Copyright (C) 2015-2016, 2019 secunet Security Networks AG
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
@@ -12,6 +12,7 @@
-- GNU General Public License for more details.
--
+with HW.GFX.GMA.Config;
with HW.GFX.GMA.PLLs.LCPLL;
with HW.GFX.GMA.PLLs.WRPLL;
@@ -87,8 +88,15 @@
PLL := Invalid;
Success := True;
elsif Port_Cfg.Display = DP then
- PLL := LCPLL.Fixed_LCPLLs (Port_Cfg.DP.Bandwidth);
- Success := True;
+ if Config.DP_Max_2_7_GHz and then
+ Port_Cfg.DP.Bandwidth > DP_Bandwidth_2_7
+ then
+ PLL := Invalid;
+ Success := False;
+ else
+ PLL := LCPLL.Fixed_LCPLLs (Port_Cfg.DP.Bandwidth);
+ Success := True;
+ end if;
else
Alloc_Configurable (Port_Cfg.Mode, PLL, Success);
end if;