diff --git a/common/hw-gfx-gma-registers.adb b/common/hw-gfx-gma-registers.adb
index 9e52c78..4a22564 100644
--- a/common/hw-gfx-gma-registers.adb
+++ b/common/hw-gfx-gma-registers.adb
@@ -61,6 +61,21 @@
 
    ----------------------------------------------------------------------------
 
+   procedure Clear_Fences
+   is
+      Fence_Regs_Base : constant :=
+        (case Config.CPU is
+            when Ironlake                 => 16#00_3000#,
+            when Sandybridge .. Skylake   => 16#10_0000#);
+      subtype Fence_Range is Registers_Range range 0 .. 63;
+   begin
+      for Idx in Fence_Range loop
+         Regs.Write (Fence_Regs_Base / Register_Width + Idx, 0);
+      end loop;
+   end Clear_Fences;
+
+   ----------------------------------------------------------------------------
+
    procedure Write_GTT
      (GTT_Page       : GTT_Range;
       Device_Address : GTT_Address_Type;
diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads
index 63df8be..2a01aab 100644
--- a/common/hw-gfx-gma-registers.ads
+++ b/common/hw-gfx-gma-registers.ads
@@ -1529,6 +1529,8 @@
        Mask_Unset : Word32;
        Mask_Set   : Word32);
 
+   procedure Clear_Fences;
+
    pragma Warnings (Off, "declaration of ""Write_GTT"" hides one at *");
    procedure Write_GTT
      (GTT_Page       : GTT_Range;
diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb
index 387d6bd..94f3ceb 100644
--- a/common/hw-gfx-gma.adb
+++ b/common/hw-gfx-gma.adb
@@ -401,6 +401,7 @@
          Connectors.Post_All_Off;
          PLLs.All_Off;
          Power_And_Clocks.Post_All_Off;
+         Registers.Clear_Fences;
       else
          -- According to PRMs, VGA plane is the only thing
          -- that's enabled by default after reset.