commit 0da761a02127cef9dbf78a8ac270aa9e5b5de61d
author Tim Wawrzynczak <twawrzynczak@chromium.org> Fri Sep 09 10:42:36 2022 -0600
committer Nico Huber <nico.h@gmx.de> Sat Jun 06 10:28:13 2026 +0000
tree eda6294bfa545e4e5fa9f4e803b2d46f3e08642f
parent 8b381fc278d7ce59d30f9f0d09b795f0e0ca4899

gma pipe_setup: Update for TGL & ADL

Tiger Lake requires some differences in plane programming over prior
generations, including new chicken bits, wider watermarks, MBUS DBOX
programming and a few bits moved around. Alder Lake brings some more
chicken bits and requires arb-slot programming.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I93329c0a012da83abc379d6782fabe257dc180f3
Reviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/458
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: Nico Huber <nico.h@gmx.de>

common/hw-gfx-gma-transcoder.adb

diff --git a/common/hw-gfx-gma-transcoder.adb b/common/hw-gfx-gma-transcoder.adb
index 6eea451..213af3b 100644
--- a/common/hw-gfx-gma-transcoder.adb
+++ b/common/hw-gfx-gma-transcoder.adb
@@ -328,8 +328,10 @@
       Dither   : Boolean;
       Scale    : Boolean)
    is
+      use type HW.GFX.GMA.Registers.Registers_Invalid_Index;
       Trans : Transcoder_Regs renames
                Transcoders (Get_Idx (Pipe, Port_Cfg.Port));
+      PIPE_ARB_USE_PROG_SLOTS : constant := 1 * 2 ** 13;
    begin
       pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
       if not Config.Need_Early_Transcoder_Setup then
@@ -342,6 +344,14 @@
             Mask     => DDI_FUNC_CTL_ENABLE);
       end if;
 
+      if Config.Need_Pipe_Arb_Slots and then
+         Trans.PIPE_ARB_CTL /= Registers.Invalid_Register
+      then
+         Registers.Set_Mask
+           (Register => Trans.PIPE_ARB_CTL,
+            Mask     => PIPE_ARB_USE_PROG_SLOTS);
+      end if;
+
       Registers.Write
         (Register => Trans.CONF,
          Value    => TRANS_CONF_ENABLE or