diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template
index c6af93a..e34e89d 100644
--- a/common/hw-gfx-gma-config.ads.template
+++ b/common/hw-gfx-gma-config.ads.template
@@ -133,7 +133,7 @@
    Has_Per_Pipe_SRD        : constant Boolean := CPU >= Broadwell;
 
    ----- GTT: -------------
-   Fold_39Bit_GTT_PTE      : constant Boolean := CPU <= Haswell;
+   Has_64bit_GTT           : constant Boolean := CPU >= Broadwell;
 
    ----------------------------------------------------------------------------
 
@@ -250,19 +250,7 @@
 
    ----------------------------------------------------------------------------
 
-   GTT_Offset  : constant := (case CPU is
-                                 when G45 .. Haswell   => 16#0020_0000#,
-                                 when Broadwell .. Skylake  => 16#0080_0000#);
-
-   GTT_Size    : constant := (case CPU is
-                                 when G45 .. Haswell   => 16#0020_0000#,
-                                 -- Limit Broadwell to 4MiB to have a stable
-                                 -- interface (i.e. same number of entries):
-                                 when Broadwell .. Skylake  => 16#0040_0000#);
-
-   GTT_PTE_Size   : constant := (case CPU is
-                                    when G45 .. Haswell       => 4,
-                                    when Broadwell .. Skylake => 8);
+   GTT_PTE_Size : constant := (if Has_64bit_GTT then 8 else 4);
 
    Fence_Base : constant := (case CPU is
                               when G45 .. Ironlake          => 16#0000_3000#,
diff --git a/common/hw-gfx-gma-registers.adb b/common/hw-gfx-gma-registers.adb
index d7e02d9..9b14a3b 100644
--- a/common/hw-gfx-gma-registers.adb
+++ b/common/hw-gfx-gma-registers.adb
@@ -26,9 +26,10 @@
 package body HW.GFX.GMA.Registers
 with
    Refined_State =>
-     (Address_State  => (Regs.Base_Address, GTT.Base_Address),
+     (Address_State  =>
+        (Regs.Base_Address, GTT_32.Base_Address, GTT_64.Base_Address),
       Register_State => Regs.State,
-      GTT_State      => GTT.State)
+      GTT_State      => (GTT_32.State, GTT_64.State))
 is
    pragma Disable_Atomic_Synchronization;
 
@@ -46,16 +47,27 @@
 
    ----------------------------------------------------------------------------
 
-   type GTT_PTE_Type is mod 2 ** (Config.GTT_PTE_Size * 8);
-   type GTT_Registers_Type is array (GTT_Range) of GTT_PTE_Type
+   type GTT_PTE_32 is mod 2 ** 32;
+   type GTT_Registers_32 is array (GTT_Range) of GTT_PTE_32
    with
       Volatile_Components,
-      Size => Config.GTT_Size * 8;
-   package GTT is new MMIO_Range
-     (Base_Addr   => Config.Default_MMIO_Base + Config.GTT_Offset,
-      Element_T   => GTT_PTE_Type,
+      Size => MMIO_GTT_32_Size * 8;
+   package GTT_32 is new MMIO_Range
+     (Base_Addr   => Config.Default_MMIO_Base + MMIO_GTT_32_Offset,
+      Element_T   => GTT_PTE_32,
       Index_T     => GTT_Range,
-      Array_T     => GTT_Registers_Type);
+      Array_T     => GTT_Registers_32);
+
+   type GTT_PTE_64 is mod 2 ** 64;
+   type GTT_Registers_64 is array (GTT_Range) of GTT_PTE_64
+   with
+      Volatile_Components,
+      Size => MMIO_GTT_64_Size * 8;
+   package GTT_64 is new MMIO_Range
+     (Base_Addr   => Config.Default_MMIO_Base + MMIO_GTT_64_Offset,
+      Element_T   => GTT_PTE_64,
+      Index_T     => GTT_Range,
+      Array_T     => GTT_Registers_64);
 
    GTT_PTE_Valid : constant Word32 := 1;
 
@@ -147,17 +159,17 @@
       Valid          : Boolean)
    is
    begin
-      if Config.Fold_39Bit_GTT_PTE then
-         GTT.Write
+      if not Config.Has_64bit_GTT then
+         GTT_32.Write
            (Index => GTT_Page,
-            Value => GTT_PTE_Type (Device_Address and 16#ffff_f000#) or
-                     GTT_PTE_Type (Shift_Right (Word64 (Device_Address), 32 - 4)
+            Value => GTT_PTE_32 (Device_Address and 16#ffff_f000#) or
+                     GTT_PTE_32 (Shift_Right (Word64 (Device_Address), 32 - 4)
                                    and 16#0000_07f0#) or
                      Boolean'Pos (Valid));
       else
-         GTT.Write
+         GTT_64.Write
            (Index => GTT_Page,
-            Value => GTT_PTE_Type (Device_Address and 16#7f_ffff_f000#) or
+            Value => GTT_PTE_64 (Device_Address and 16#7f_ffff_f000#) or
                      Boolean'Pos (Valid));
       end if;
    end Write_GTT;
@@ -375,9 +387,11 @@
    begin
       Regs.Set_Base_Address (Base);
       if GTT_Base = 0 then
-         GTT.Set_Base_Address (Base + Config.GTT_Offset);
+         GTT_32.Set_Base_Address (Base + MMIO_GTT_32_Offset);
+         GTT_64.Set_Base_Address (Base + MMIO_GTT_64_Offset);
       else
-         GTT.Set_Base_Address (GTT_Base);
+         GTT_32.Set_Base_Address (GTT_Base);
+         GTT_64.Set_Base_Address (GTT_Base);
       end if;
    end Set_Register_Base;
 
diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads
index 1220d1a..99efba9 100644
--- a/common/hw-gfx-gma-registers.ads
+++ b/common/hw-gfx-gma-registers.ads
@@ -23,6 +23,15 @@
      (GTT_State      with External, Part_Of => GMA.Device_State)),
    Initializes => Address_State
 is
+
+   MMIO_GTT_32_Size     : constant := 16#20_0000#;
+   MMIO_GTT_32_Offset   : constant := 16#20_0000#;
+
+   -- Limit Broadwell+ to 4MiB to have a stable
+   -- interface (i.e. same number of entries):
+   MMIO_GTT_64_Size     : constant := 16#40_0000#;
+   MMIO_GTT_64_Offset   : constant := 16#80_0000#;
+
    type Registers_Invalid_Index is
      (Invalid_Register, -- Allow a placeholder when access is not acceptable
 
diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb
index b3d9362..baa7e6c 100644
--- a/common/hw-gfx-gma.adb
+++ b/common/hw-gfx-gma.adb
@@ -386,6 +386,10 @@
    is
       use type HW.Word64;
 
+      function MMIO_GTT_Offset return Natural is
+        (if Config.Has_64bit_GTT
+         then Registers.MMIO_GTT_64_Offset
+         else Registers.MMIO_GTT_32_Offset);
       PCI_MMIO_Base, PCI_GTT_Base : Word64;
 
       Now : constant Time.T := Time.Now;
@@ -447,8 +451,8 @@
       Dev.Initialize (Success);
 
       if Success then
-         Dev.Map (PCI_MMIO_Base, PCI.Res0, Length => Config.GTT_Offset);
-         Dev.Map (PCI_GTT_Base, PCI.Res0, Offset => Config.GTT_Offset);
+         Dev.Map (PCI_MMIO_Base, PCI.Res0, Length => MMIO_GTT_Offset);
+         Dev.Map (PCI_GTT_Base, PCI.Res0, Offset => MMIO_GTT_Offset);
          if PCI_MMIO_Base /= 0 and PCI_GTT_Base /= 0 then
             Registers.Set_Register_Base (PCI_MMIO_Base, PCI_GTT_Base);
          else