gma registers: Separate 32- and 64-bit GTT access
With Broadwell the GTT layout changed significantly. Before, we had a
2MiB GTT with 32-bit entries. Now, it's a 8MiB GTT with 64-bit entries.
We used to abstract over that with configuration constants but that's
infeasible if we want to support Haswell and Broadwell with a single
binary (boards that support both processors exist).
Therefore, declare both GTT variants and decide based on the CPU which
one to use.
Change-Id: Ib6f21b71c434a9cbdd5cdfa3697da2b2e86750f4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/27056
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb
index b3d9362..baa7e6c 100644
--- a/common/hw-gfx-gma.adb
+++ b/common/hw-gfx-gma.adb
@@ -386,6 +386,10 @@
is
use type HW.Word64;
+ function MMIO_GTT_Offset return Natural is
+ (if Config.Has_64bit_GTT
+ then Registers.MMIO_GTT_64_Offset
+ else Registers.MMIO_GTT_32_Offset);
PCI_MMIO_Base, PCI_GTT_Base : Word64;
Now : constant Time.T := Time.Now;
@@ -447,8 +451,8 @@
Dev.Initialize (Success);
if Success then
- Dev.Map (PCI_MMIO_Base, PCI.Res0, Length => Config.GTT_Offset);
- Dev.Map (PCI_GTT_Base, PCI.Res0, Offset => Config.GTT_Offset);
+ Dev.Map (PCI_MMIO_Base, PCI.Res0, Length => MMIO_GTT_Offset);
+ Dev.Map (PCI_GTT_Base, PCI.Res0, Offset => MMIO_GTT_Offset);
if PCI_MMIO_Base /= 0 and PCI_GTT_Base /= 0 then
Registers.Set_Register_Base (PCI_MMIO_Base, PCI_GTT_Base);
else