gma registers: Separate 32- and 64-bit GTT access
With Broadwell the GTT layout changed significantly. Before, we had a
2MiB GTT with 32-bit entries. Now, it's a 8MiB GTT with 64-bit entries.
We used to abstract over that with configuration constants but that's
infeasible if we want to support Haswell and Broadwell with a single
binary (boards that support both processors exist).
Therefore, declare both GTT variants and decide based on the CPU which
one to use.
Change-Id: Ib6f21b71c434a9cbdd5cdfa3697da2b2e86750f4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/27056
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template
index c6af93a..e34e89d 100644
--- a/common/hw-gfx-gma-config.ads.template
+++ b/common/hw-gfx-gma-config.ads.template
@@ -133,7 +133,7 @@
Has_Per_Pipe_SRD : constant Boolean := CPU >= Broadwell;
----- GTT: -------------
- Fold_39Bit_GTT_PTE : constant Boolean := CPU <= Haswell;
+ Has_64bit_GTT : constant Boolean := CPU >= Broadwell;
----------------------------------------------------------------------------
@@ -250,19 +250,7 @@
----------------------------------------------------------------------------
- GTT_Offset : constant := (case CPU is
- when G45 .. Haswell => 16#0020_0000#,
- when Broadwell .. Skylake => 16#0080_0000#);
-
- GTT_Size : constant := (case CPU is
- when G45 .. Haswell => 16#0020_0000#,
- -- Limit Broadwell to 4MiB to have a stable
- -- interface (i.e. same number of entries):
- when Broadwell .. Skylake => 16#0040_0000#);
-
- GTT_PTE_Size : constant := (case CPU is
- when G45 .. Haswell => 4,
- when Broadwell .. Skylake => 8);
+ GTT_PTE_Size : constant := (if Has_64bit_GTT then 8 else 4);
Fence_Base : constant := (case CPU is
when G45 .. Ironlake => 16#0000_3000#,