diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template
index 987e315..5801bfe 100644
--- a/common/hw-gfx-gma-config.ads.template
+++ b/common/hw-gfx-gma-config.ads.template
@@ -244,6 +244,7 @@
 
    ----------- Transcoder -------
    Need_Early_Transcoder_Setup   : <genbool> := Tigerlake_On;
+   Continuous_Port_Select        : <genbool> := AlderlakeP_On;
    Need_Pipe_Arb_Slots           : <genbool> := AlderlakeP_On;
 
    ----------- Planes -----------
diff --git a/common/hw-gfx-gma-transcoder.adb b/common/hw-gfx-gma-transcoder.adb
index 2452b44..40dcaaf 100644
--- a/common/hw-gfx-gma-transcoder.adb
+++ b/common/hw-gfx-gma-transcoder.adb
@@ -50,18 +50,32 @@
       DIGI_D => 4 * 2 ** 29,
       DIGI_E => 5 * 2 ** 29);
 
-   function TGL_TRANS_CLK_SEL_PORT (Port : TGL_Digital_Port) return Word32 is
-   (case Port is
-      when DIGI_A  => 1 * 2 ** 28,
-      when DIGI_B  => 2 * 2 ** 28,
-      when DIGI_C  => 3 * 2 ** 28,
-      when DDI_TC1 => 4 * 2 ** 28,
-      when DDI_TC2 => 5 * 2 ** 28,
-      when DDI_TC3 => 6 * 2 ** 28,
-      when DDI_TC4 => 7 * 2 ** 28,
-      when DDI_TC5 => 8 * 2 ** 28,
-      when DDI_TC6 => 9 * 2 ** 28,
-      when others  => 0);
+   function TGL_TRANS_CLK_SEL_PORT (Port : TGL_Digital_Port) return Word32
+   is
+     (case Port is
+         when DIGI_A  => 1 * 2 ** 28,
+         when DIGI_B  => 2 * 2 ** 28,
+         when DIGI_C  => 3 * 2 ** 28,
+         when DDI_TC1 => 4 * 2 ** 28,
+         when DDI_TC2 => 5 * 2 ** 28,
+         when DDI_TC3 => 6 * 2 ** 28,
+         when DDI_TC4 => 7 * 2 ** 28,
+         when DDI_TC5 => 8 * 2 ** 28,
+         when DDI_TC6 => 9 * 2 ** 28,
+         when others  => 0);
+
+   function XELPD_TRANS_CLK_SEL_PORT (Port : XELPD_Digital_Port) return Word32
+   is
+     (case Port is
+         when DIGI_A  => 1 * 2 ** 28,
+         when DIGI_B  => 2 * 2 ** 28,
+         when DIGI_C  => 3 * 2 ** 28,
+         when DIGI_D  => 4 * 2 ** 28,
+         when DIGI_E  => 5 * 2 ** 28,
+         when DDI_TC1 => 6 * 2 ** 28,
+         when DDI_TC2 => 7 * 2 ** 28,
+         when DDI_TC3 => 8 * 2 ** 28,
+         when DDI_TC4 => 9 * 2 ** 28);
 
    TRANS_CONF_ENABLE          : constant := 1 * 2 ** 31;
    TRANS_CONF_ENABLED_STATUS  : constant := 1 * 2 ** 30;
@@ -100,20 +114,20 @@
       DIGI_D => 3 * 2 ** 28,
       DIGI_E => 4 * 2 ** 28);
 
-   function TGL_DDI_FUNC_CTL_DDI_SELECT (Port : TGL_Digital_Port)
-      return Word32
+   function TGL_DDI_FUNC_CTL_DDI_SELECT (Port : DDI_Port) return Word32
    is
      (case Port is
-      when DIGI_A  => 1 * 2 ** 27,
-      when DIGI_B  => 2 * 2 ** 27,
-      when DIGI_C  => 3 * 2 ** 27,
-      when DDI_TC1 => 4 * 2 ** 27,
-      when DDI_TC2 => 5 * 2 ** 27,
-      when DDI_TC3 => 6 * 2 ** 27,
-      when DDI_TC4 => 7 * 2 ** 27,
-      when DDI_TC5 => 8 * 2 ** 27,
-      when DDI_TC6 => 9 * 2 ** 27,
-      when others  => 0);
+         when DIGI_A  => 1 * 2 ** 27,
+         when DIGI_B  => 2 * 2 ** 27,
+         when DIGI_C  => 3 * 2 ** 27,
+         when DIGI_D  => 8 * 2 ** 27,  -- n/a on TGL, repositioned since ADL-P
+         when DIGI_E  => 9 * 2 ** 27,  -- n/a on TGL, repositioned since ADL-P
+         when DDI_TC1 => 4 * 2 ** 27,
+         when DDI_TC2 => 5 * 2 ** 27,
+         when DDI_TC3 => 6 * 2 ** 27,
+         when DDI_TC4 => 7 * 2 ** 27,
+         when DDI_TC5 => 8 * 2 ** 27,
+         when DDI_TC6 => 9 * 2 ** 27);
 
    type DDI_Mode_Array is array (Display_Type) of Word32;
    DDI_FUNC_CTL_MODE_SELECT : constant DDI_Mode_Array :=
@@ -267,13 +281,23 @@
                Transcoders (Get_Idx (Pipe, Port_Cfg.Port));
    begin
       if Config.Need_Early_Transcoder_Setup and then
-         Trans.CLK_SEL /= Registers.Invalid_Register and then
-         Port_Cfg.Port in TGL_Digital_Port
+         Trans.CLK_SEL /= Registers.Invalid_Register
       then
-         Registers.Unset_And_Set_Mask
-           (Register   => Trans.CLK_SEL,
-            Mask_Unset => TRANS_CLK_SEL_MASK,
-            Mask_Set   => TGL_TRANS_CLK_SEL_PORT (Port_Cfg.Port));
+         if Config.Continuous_Port_Select then
+            if Port_Cfg.Port in XELPD_Digital_Port then
+               Registers.Unset_And_Set_Mask
+                 (Register   => Trans.CLK_SEL,
+                  Mask_Unset => TRANS_CLK_SEL_MASK,
+                  Mask_Set   => XELPD_TRANS_CLK_SEL_PORT (Port_Cfg.Port));
+            end if;
+         else
+            if Port_Cfg.Port in TGL_Digital_Port then
+               Registers.Unset_And_Set_Mask
+                 (Register   => Trans.CLK_SEL,
+                  Mask_Unset => TRANS_CLK_SEL_MASK,
+                  Mask_Set   => TGL_TRANS_CLK_SEL_PORT (Port_Cfg.Port));
+            end if;
+         end if;
       end if;
    end Enable_Pipe_Clock;
 
@@ -296,7 +320,7 @@
             else
                DDI_FUNC_CTL_EDP_SELECT (Pipe)));
       DDI_Select : constant Word32 :=
-        (if Config.Has_TGL_DDI_Select and Port_Cfg.Port in TGL_Digital_Port then
+        (if Config.Has_TGL_DDI_Select and then Port_Cfg.Port in DDI_Port then
             TGL_DDI_FUNC_CTL_DDI_SELECT (Port_Cfg.Port)
          else
             (if Port_Cfg.Port in Digital_Port
diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads
index 18ca5d4..3ee3d18 100644
--- a/common/hw-gfx-gma.ads
+++ b/common/hw-gfx-gma.ads
@@ -324,11 +324,13 @@
    subtype Digital_Port is GPU_Port range DIGI_A .. DIGI_E;
    subtype GMCH_DP_Port is GPU_Port range DIGI_B .. DIGI_D;
    subtype GMCH_HDMI_Port is GPU_Port range DIGI_B .. DIGI_C;
+   subtype DDI_Port is GPU_Port range DIGI_A .. DDI_TC6;
    subtype Combo_Port is GPU_Port range DIGI_A .. DIGI_C;
    subtype USBC_Port is GPU_Port range DDI_TC1 .. DDI_TC6;
    subtype TGL_Digital_Port is GPU_Port range DIGI_A .. DDI_TC6
    with
       Static_Predicate => (TGL_Digital_Port /= DIGI_D and TGL_Digital_Port /= DIGI_E);
+   subtype XELPD_Digital_Port is GPU_Port range DIGI_A .. DDI_TC4;
 
    function Is_Digital_Port (Port : GPU_Port) return Boolean is
       (Port in Digital_Port or Port in TGL_Digital_Port);