)]}' { "log": [ { "commit": "fb9c18a7aafb2f71b49f004f43800cf213ccb6cd", "tree": "823e26022ad7981d5ab6d4b36110cd8c3d97edf5", "parents": [ "bfe6484b3bb66fcbfc986ec9bc43155a8c8ea61b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 10 23:59:19 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:30 2022 +0100" }, "message": "manibuilder: Add service container with local Git access\n\nAdd a new target `local-git` that spawns a service container with a\nlocal Git daemon. The variable ${TEST_LOCAL} needs to point to the\ndirectory of a local git repository.\n\nChange-Id: I9e465551d3398fdb8d173a0a8fbd169561241a74\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70911\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "bfe6484b3bb66fcbfc986ec9bc43155a8c8ea61b", "tree": "8f4979e8d829f33dc37d368ba9dad39194b75881", "parents": [ "aa359a73420bf8c731f2f9733eb2f146f559825c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 10 23:54:24 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:30 2022 +0100" }, "message": "manibuilder: Automatically create `manibuilder` network bridge\n\nCreate a network bridge for all manibuilder containers. We\u0027ll add a\nservice container with access to a local Git repository later.\n\nChange-Id: Idb03c21dbd12bef59a2c683e169015e286c04d11\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70910\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "aa359a73420bf8c731f2f9733eb2f146f559825c", "tree": "2cd6f9600d25001f868b6c73f851e2cd8ed21603", "parents": [ "34846e46a08dd743e8419d9e9ade00e3d3da0c5f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 10 23:52:46 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:30 2022 +0100" }, "message": "manibuilder: Make Git remote overridable\n\nChange-Id: Idfc1272f5a7370d3a183835ddf4052db374d6a26\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70909\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "34846e46a08dd743e8419d9e9ade00e3d3da0c5f", "tree": "bf228bd4dd70b83e1101565f3e6ca338fe980a08", "parents": [ "f4a1b5d2e8c74f4ad24764aca8b7d3ad53c1e176" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 10 23:45:38 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:29 2022 +0100" }, "message": "manibuilder: Set $(TEST_REVISION) default in make\n\nChange-Id: I8320110a19c434b6d464d8036cc2a99fff41f63e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70908\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f4a1b5d2e8c74f4ad24764aca8b7d3ad53c1e176", "tree": "7dc5040c99ed99390ef540bdb4770ca673f72370", "parents": [ "c0b52db332ce95ca3227b35b3263c858882e0b5d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Sep 27 14:02:36 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:29 2022 +0100" }, "message": "manibuilder: Add list of 1.2.x targets\n\nWe didn\u0027t maintain a list at the 1.2 release. Maybe didn\u0027t even run\nmanibuilder. Let\u0027s start one with distributions available at the\n1.2 release and those available today.\n\nChange-Id: Ia6266ecfba5e9acb37acc41cc305f2f713de7a24\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70907\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "c0b52db332ce95ca3227b35b3263c858882e0b5d", "tree": "945d00d92a9a9056e1a5f9927fca4647cb0644b6", "parents": [ "7cb43957c5fe405cd82584f0a54428f2d2d286ff" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 15 12:42:32 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:29 2022 +0100" }, "message": "Import manibuilder from flashrom master\n\nReferences to the upstream repository have been changed to\n`flashrom-stable.git`. The directory `flashrom` is kept,\nthough, so existing containers can be used for both projects.\n\nChange-Id: I8ba148e30602e8e03e3858f7c1eb6789230654d6\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70906\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7cb43957c5fe405cd82584f0a54428f2d2d286ff", "tree": "9981905ba97c0509e8686782855d97cffe77d80e", "parents": [ "4cbc1cb32dec2a269a6c2fb8d391f36db174bb32" ], "author": { "name": "Subrata Banik", "email": "subratabanik@google.com", "time": "Wed Mar 16 20:40:42 2022 +0530" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Sun Oct 30 09:43:35 2022 +0000" }, "message": "ichspi: Unify timeouts across all SPI operations to 30s\n\nNote: This patch was backported from the master branch and it was\nmodified so that it can be applied on the 1.2.x branch.\n\n`ich_hwseq_wait_for_cycle_complete()` drops taking `timeout` as argument\nin favor of a fixed timeout of `30 seconds` for any given SPI operation\nas recommended by the SPI programming guide.\n\nDocument: Alder Lake-P Client Platform SPI Programming Guide\n Rev 1.30 (supporting document for multi-master accessing the\n SPI Flash device.)\n\nRefer to below section to understand the problem in more detail and SPI\noperation timeout recommendation from Intel in multi-master\nscenarios.\n\nOn Intel Chipsets that support multi-mastering access of the SPI flash\nmay run into a timeout failure when the operation initiated from a\nsingle master just follows the SPI operational timeout recommendation\nas per the vendor datasheet (example: winbond spiflash W25Q256JV-DTR\nspecification, table 9.7).\n\nIn the multi-master SPI accessing scenario using hardware sequencing\noperation, it\u0027s impossible to know the actual status of the SPI bus\nprior to individual master starting the operation (SPI Cycle In Progress\na.k.a SCIP bit represents the status of SPI operation on individual\nmaster).\n\nThus, any SPI operation triggered in multi-master environment might need\nto account a worst case scenario where the most time consuming operation\nmight have occupied the SPI bus from a master and an operation initiated\nby another master just timed out.\n\nHere is the timeout calculation for any hardware sequencing operation:\n Worst Case Operational Delay \u003d\n (Maximum Time consumed by a SPI operation + Any marginal\n\t adjustment)\n\n Timeout Recommendation for Hardware Sequencing Operation \u003d\n ((Worst Case Operational Delay) * (#No. Of SPI Master - 1) +\n Current Operational latency)\n\nAssume, on Intel platform with 6 SPI master like, Host CPU, CSE, EC,\nGbE and other reserved etc, hence, the Timeout Calculation for SPI\nerase Operation would look like as below:\n\n Maximum Time consumed by a SPI Operation \u003d 5 seconds\n\n Worst Case Operational Delay \u003d 5 seconds\n\n Timeout Recommendation for Hardware Seq Operation \u003d\n 5 seconds * (6 - 1) + 5 seconds \u003d 30 seconds\n\nBUG\u003db:223630977\nTEST\u003dAble to perform read/write/erase operation on PCH 600 series\nchipset (board name: Brya).\n\nOriginal-Signed-off-by: Subrata Banik \u003csubratabanik@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62867\nOriginal-Tested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nChange-Id: Ifa910dea794175d8ee2ad277549e5a0d69cba45b\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/68691\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Michael Niewöhner \u003cfoss@mniewoehner.de\u003e\n" }, { "commit": "4cbc1cb32dec2a269a6c2fb8d391f36db174bb32", "tree": "fbe81e1f039bd7813b2973db04fc2c3ac4f82b1a", "parents": [ "1900e1d5d39d91b762c9a02ef2445868b323ca87" ], "author": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Fri Jul 22 23:23:28 2022 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Oct 06 01:03:11 2022 +0000" }, "message": "Makefile: Fix dependencies for developerbox_spi\n\nNote: This patch was backported from the master branch and it was\nmodified so that it can be applied on the 1.2.x branch.\n\nThe developerbox_spi programmer depends on bitbang SPI support. Thus,\nfix that.\n\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nChange-Id: Ic0fe589ffdccede0fbf6360c2bebe58a36654f10\nReviewed-on: https://review.coreboot.org/c/flashrom/+/66096\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/68064\n" }, { "commit": "1900e1d5d39d91b762c9a02ef2445868b323ca87", "tree": "a95c01537af1a6a2a643f696c5e33df886471619", "parents": [ "87aa19314523d1cffdef57fbdf65d8328824026c" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Fri Jul 02 12:42:23 2021 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Oct 06 01:00:37 2022 +0000" }, "message": "Replace freenode references\n\nThe flashrom project no longer uses freenode. To avoid having outdated\nman pages in the future, the contact methods are now listed in the wiki.\n\nChange-Id: I75e8f43c50dc4c3feede0250334a877cdaac8103\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/56031\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/68063\n" }, { "commit": "87aa19314523d1cffdef57fbdf65d8328824026c", "tree": "bee9fc52eca9b27172ae3d060701a4cbcafc1d06", "parents": [ "89cc73bda5fd181e9fcab2eadf5f80759379c1b3" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Fri Jul 02 12:48:10 2021 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Oct 06 01:00:32 2022 +0000" }, "message": "print_wiki.c: Update mailing list reference\n\nChange-Id: I5c67b5b3be2f306132d8565539bbf10477222026\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/56030\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/68062\n" }, { "commit": "89cc73bda5fd181e9fcab2eadf5f80759379c1b3", "tree": "b1ddf34a7d13413887257ae0347109a336c54ce5", "parents": [ "380090faffcbe3cbdc20af9c75979fdafaa5a834" ], "author": { "name": "Pyry Kontio", "email": "pyry.kontio@drasa.eu", "time": "Mon Jul 06 12:57:35 2020 +0900" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:35:30 2022 +0000" }, "message": "Makefile: Fix building on AArch64 NixOS\n\nThe parsing of the output of archtest.c produced an unexpected\nvalue on AArch64 NixOS. For example, the make variable ARCH was set to:\n\n```\nbit outside of fd_set selected\narm\n```\n\nThis made the arch and OS checks fail.\n\nThis commit simplifies the parsing, making it more robust.\n\nThe C files archtest.c, endiantest.c and os.h used to set the\nTARGET_OS, ARCH and ENDIAN variables, respectively, output\nthe result of the test as the final line, so just extracting\nthe final line and removing double quoting is enough.\n\nThis commit also fixes a bug with debug_shell lacking escaping\nsingle quotes, which prevented using the single quote in the\ndebug_shell calls. It used to work by accident before this fix;\nthe line in the call happened to contain a balanced pair of double\nquotes and lacked other characters that needed escaping, which\ndidn\u0027t break the debug_shell, but this was accidental and very\nbrittle.\n\nSigned-off-by: Pyry Kontio \u003cpyry.kontio@drasa.eu\u003e\nChange-Id: Iaa4477a71e758cf9ecad2c22f3b77bc6508a3510\nReviewed-on: https://review.coreboot.org/c/flashrom/+/43140\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67902\nReviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\n" }, { "commit": "380090faffcbe3cbdc20af9c75979fdafaa5a834", "tree": "d6dac3cefcc91f4451b73b0bf8da60473ca6c34c", "parents": [ "298ac33bc495bba371629951dce8ea67e5e0ca78" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon May 23 01:45:11 2022 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:06:21 2022 +0000" }, "message": "pcidev: Always fetch ident info\n\nAs discovered earlier[1], the `vendor_id` and `device_id` fields are not\nalways automatically set. However, we use these fields throughout flash-\nrom. To not lose track when we actually fetched them, let\u0027s always call\npci_fill_info(PCI_FILL_IDENT) before returning a `pci_dev` handle.\n\n[1] Commit ca2e3bce0 (pcidev.c: populate IDs with pci_fill_info())\n\nBackported to older versions where pcidev handling was much more\nscattered.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: Iae2511178bec44343cbe902722fdca9eda036059\nTicket: https://ticket.coreboot.org/issues/367\nReviewed-on: https://review.coreboot.org/c/flashrom/+/64573\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67877\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "298ac33bc495bba371629951dce8ea67e5e0ca78", "tree": "9387c285a1af5bc95ca9c698b3d98f05f1f141df", "parents": [ "245e540ecbe8e0daa8db747dcc6d470fa6f79938" ], "author": { "name": "Daniel Verkamp", "email": "dverkamp@chromium.org", "time": "Mon Oct 12 12:55:56 2020 -0700" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:06:13 2022 +0000" }, "message": "pcidev.c: populate IDs with pci_fill_info()\n\nWith pciutils 3.7.0, flashrom is unable to match any PCI devices by\nvendor/device ID because the vendor_id and device_id fields of struct\npci_dev are not filled in.\n\nCall pci_fill_info() to request these identifiers before trying to match\nthem against the supported device list.\n\nThe pciutils ChangeLog for 3.7.0 mentions that the documentation and\nback-end behavior for pci_fill_info() was updated; it seems that a call\nto pci_fill_info() was always intended to be required, but some backends\n(such as the sysfs one used on Linux) would fill the identifier fields\neven when not requested by the user. The pci_fill_info() function and\nthe PCI_FILL_IDENT flag have been available for all versions of pciutils\nsince at least 2.0 from 1999, so it should be safe to add without any\nversion checks.\n\nWith this change, reading/writing a nicintel_spi boot ROM is successful.\n\nSigned-off-by: Daniel Verkamp \u003cdverkamp@chromium.org\u003e\nChange-Id: Ia011d4d801f8a54160e45a70b14b740e6dcc00ef\nReviewed-on: https://review.coreboot.org/c/flashrom/+/46310\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67876\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "245e540ecbe8e0daa8db747dcc6d470fa6f79938", "tree": "b8bfd72696a54c0adb7f3e3d06afaedcf9b36c48", "parents": [ "04fce478cb9aba339439d1955c3355a075445ec1" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 06 00:21:52 2022 +0100" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:06:09 2022 +0000" }, "message": "dmi: Correctly check for ERROR_PTR\n\nFor the physmap*() functions, NULL is considered valid return value.\nFixes a segmentation fault when DMI tables can\u0027t be mapped.\n\nTested on intel/eblake board with broken coreboot.\n\nChange-Id: Ic403c2940c2b91acbd113f0acfa3ce9ef6c6bb6c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/62611\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67875\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "04fce478cb9aba339439d1955c3355a075445ec1", "tree": "8c6342749297f623f282aea64c84082dbb8835e2", "parents": [ "96cc5d3ea84e7e7e3a6029cf728cef061ccae45f" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Tue Jan 11 18:26:48 2022 +1100" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:06:03 2022 +0000" }, "message": "linux_mtd: check ioctl() return value properly\n\nMake the linux_mtd driver treat any negative return value from the\nMEMERASE ioctl as an error. Previously it only treated -1 as an error.\n\nBUG\u003db:213561594,b:210973586,b:182223106\nBRANCH\u003dnone\nTEST\u003dbuilds\n\nChange-Id: I40cfbdee2ab608fbe6c17d9cac6ec53ff224d9a4\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/60996\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67874\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "96cc5d3ea84e7e7e3a6029cf728cef061ccae45f", "tree": "3072b945e3be60c09c945c47adf5fb47fcdacc7b", "parents": [ "a8c0b68199c5f76073a8b9c2ecf2d3694086591e" ], "author": { "name": "Michael Niewöhner", "email": "foss@mniewoehner.de", "time": "Tue Sep 21 17:37:32 2021 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:56 2022 +0000" }, "message": "flashrom.8: add missing entry for `--flash-contents`\n\nChange-Id: I64a8200a86329bd26a2069c5dc39430de9f8ba09\nSigned-off-by: Michael Niewöhner \u003cfoss@mniewoehner.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/57807\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67873\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "a8c0b68199c5f76073a8b9c2ecf2d3694086591e", "tree": "2e77e4b73a0b42227f08ad5879750498eb84aba4", "parents": [ "595c5d017402fb20bef14e4d2c399251470c95fe" ], "author": { "name": "Marc Schink", "email": "dev@zapb.de", "time": "Sat Aug 22 11:29:22 2020 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:49 2022 +0000" }, "message": "jlink_spi: Reduce transfer size\n\nThe maximum transfer size is too large for some devices and\nresults in an USB timeout.\n\nChange-Id: If2c00b1524ec56740bdfe290096c3546cf375d73\nSigned-off-by: Marc Schink \u003cdev@zapb.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/48379\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Miklós Márton \u003cmartonmiklosqdev@gmail.com\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67872\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "595c5d017402fb20bef14e4d2c399251470c95fe", "tree": "49b5163834504c40ffdb373be4360426ba99204e", "parents": [ "5feb8cdb6ff497e45cda73839dacafc240bf83bb" ], "author": { "name": "Douglas Anderson", "email": "dianders@chromium.org", "time": "Fri Jan 29 16:35:24 2021 -0800" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:43 2022 +0000" }, "message": "linux_mtd: Disable buffering on the mtd device\n\nWe open the device node for the MTD device with this:\n dev_fp \u003d fopen(dev_path, \"r+\")\n\nIn C fopen() is allowed to provide _buffered_ access to the file.\nThat means that the standard library is allowed to read ahead and/or\nreturn cached data. That\u0027s really not what we want for something like\nthis. Let\u0027s turn it off.\n\nThis fixes a problem where flashrom would sometimes fail to \"verify\"\nthat it erased the flash. The error message would look something like\nthis:\n\nErasing and writing flash chip... FAILED at 0x0000e220! Expected\u003d0xff, Found\u003d0xe9, failed byte count from 0x0000e200-0x0000e2ff: 0xdc\n failed byte count from 0x0000e000-0x0000efff: 0xffffffff\n ERASE_FAILED\nFAILED!\nUh oh. Erase/write failed. Checking if anything changed.\n\nAfter the failure I could read the flash device with a new invocation\nof flashrom and I would see that, indeed, the erase had worked.\n\nTracing in the kernel showed that when the failure happened we saw a\npattern that looked like this:\n* Read 0x0b00 bytes starting at 0x0000d000\n* Read 0x1000 bytes starting at 0x0000db00\n* Erase 0x1000 bytes starting at 0x0000e000\n\n...and then there was _not_ a read after the erase. It can be assumed\nthat, since userspace had already read 0xdb00 - 0xeaff that it was\nlooking at old buffered data after the erase.\n\nSigned-off-by: Douglas Anderson \u003cdianders@chromium.org\u003e\nChange-Id: I989afd83a33013b2756a0090d6b08245613215c6\nReviewed-on: https://review.coreboot.org/c/flashrom/+/50155\nReviewed-by: Hung-Te Lin \u003chungte@chromium.org\u003e\nReviewed-by: Patrick Rudolph \u003csiro@das-labor.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67871\nReviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "5feb8cdb6ff497e45cda73839dacafc240bf83bb", "tree": "fd3c99ccf093d56e957068e763d9c83d774ca2c7", "parents": [ "b822ce85aaed8c6dfa8f5e1e2354db5c9db50509" ], "author": { "name": "Xiang Wang", "email": "merle@hardenedlinux.org", "time": "Wed Jan 20 17:31:19 2021 +0800" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:38 2022 +0000" }, "message": "helpers.c: Fix undefined behavior in strndup()\n\nUsing strlen() or strdup() inside strndup() is problematic: if the\ninput string is not null-terminated, these functions can read past the\nend of the buffer, which triggers undefined behavior. Rewrite the\nfunction to never read past the provided `maxlen` bound.\n\nChange-Id: Id34127024085879228626fbad59af03268ec5255\nSigned-off-by: Xiang Wang \u003cmerle@hardenedliux.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/49741\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67870\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "b822ce85aaed8c6dfa8f5e1e2354db5c9db50509", "tree": "2c7f7e02cb143b306995128b1f52e5ee6b7a4f88", "parents": [ "2e3e10669d719545968ddec3b44b8a9363f4b432" ], "author": { "name": "Medicine Yeh", "email": "medicinehy@gmail.com", "time": "Thu Dec 17 15:40:42 2020 +0800" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:31 2022 +0000" }, "message": "dediprog: Fix segmentation fault on no device found\n\nlibusb_exit() call is done by dediprog_open() under the\nret \u003d\u003d 1 condition. Removing this line has no impact on\nany flow and side effect of the program.\n\nChange-Id: I38b3f3ee3f9d46845df1404791f4a4782320aa7c\nSigned-off-by: Medicine Yeh \u003cmedicinehy@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/48688\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67869\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "2e3e10669d719545968ddec3b44b8a9363f4b432", "tree": "95f7807b9ec68fdc9d21590fc7c174ee0f391fca", "parents": [ "eaf701dc68e1b6a38542c3c856b0c9a2fb5a826d" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Wed Dec 02 13:17:46 2020 +1100" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:24 2022 +0000" }, "message": "chipset_enable.c: Validate physmap() return rcrb value\n\nValidate the physical mapping in enable_flash_silvermont().\n\nChange-Id: Icc5a799a06b3f310d9a191fa5eb99b255b20d79d\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/48225\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Sam McNally \u003csammc@google.com\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67868\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "eaf701dc68e1b6a38542c3c856b0c9a2fb5a826d", "tree": "5541efefb64efc6611a315e12936608c37803c3c", "parents": [ "d92dd50bcac6b2d0dfffa9f983712f7400990f3d" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Thu Oct 15 19:19:05 2020 +1100" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:15 2022 +0000" }, "message": "chipset_enable.c: check return value from rphysmap() call\n\nPort from the ChromiumOS fork of flashrom.\n\nChange-Id: I8075fe5f80ac0da5280d2f0de6829ed3a2496476\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/46444\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Sam McNally \u003csammc@google.com\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67867\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "d92dd50bcac6b2d0dfffa9f983712f7400990f3d", "tree": "957fbc3c081425b31aeba3fb9c44451397323e94", "parents": [ "4af3609828a980bad9ecaf99365f99305d4180f8" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Mon Oct 19 14:20:36 2020 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:10 2022 +0000" }, "message": "it87spi.c: Prevent use-after-free bug\n\nThe memory for the `param` string is aliased by `dualbiosindex_suffix`.\nMoreover, `errno` could have been modified by the call to `free()`.\nTherefore, only free the former when there are no more uses of either.\n\nChange-Id: I79f18f6077c77c0cbb8bfa431e17f9b079f11c95\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/46551\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67866\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "4af3609828a980bad9ecaf99365f99305d4180f8", "tree": "2fca2548be1d41c2e48164e3c4f2683ac1862837", "parents": [ "355a1df1837e36075f2b6e59ec1f7db1db95f02a" ], "author": { "name": "Yuji Sasaki", "email": "sasakiy@chromium.org", "time": "Fri Mar 22 10:59:50 2019 -0700" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:05 2022 +0000" }, "message": "spi25: Debug flashrom crash when Write Protect is ON\n\nWhen hardware write protect is applied, flashrom crashed and\ngenerate coredump. spi_disable_blockprotect_generic() calls\nflash-\u003echip-\u003eprintlock() method when disable was failed,\nbut this method is optional, can be NULL depends on type of\nflashrom chip. NULL pointer check before call is added to\navoid crash.\n\nBRANCH\u003dnone\nBUG\u003db:129083894\nTEST\u003dRun on Mistral P2\n(On CR50 console, run \"wp disable\")\nflashrom --wp-range 0 0x400000\nflashrom --wp-enable\n(On CR50 console, run \"wp enable\")\nflashrom -r /tmp/test.bin\nVerify \"Block protection could not be disabled!\" is shown,\nbut flash read completes.\nSigned-off-by: Yuji Sasaki \u003csasakiy@chromium.org\u003e\n\nChange-Id: I81094ab5f16a85871fc9869a2e285eddbbbdec4e\nReviewed-on: https://chromium-review.googlesource.com/1535140\nCommit-Ready: ChromeOS CL Exonerator Bot \u003cchromiumos-cl-exonerator@appspot.gserviceaccount.com\u003e\nTested-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: Stefan Reinauer \u003creinauer@google.com\u003e\nReviewed-by: SANTHOSH JANARDHANA HASSAN \u003csahassan@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/40468\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67865\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "355a1df1837e36075f2b6e59ec1f7db1db95f02a", "tree": "c8293d39eff36cc6929242ffe642ba8f4e2a13bb", "parents": [ "399a4dd721a64a1d22e2f8028cc39d6496515ed6" ], "author": { "name": "Patrick Georgi", "email": "pgeorgi@google.com", "time": "Thu Apr 23 09:36:12 2020 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:00 2022 +0000" }, "message": "stlinkv3_spi: Avoid division by zero\n\nChange-Id: I08c0612f3fea59add9bde2fb3cc5c4b5c3756516\nFound-by: Coverity Scan #1412744\nSigned-off-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/40653\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67864\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "399a4dd721a64a1d22e2f8028cc39d6496515ed6", "tree": "6a40ff5ca048148294b209d8cb99ab9558fdc44f", "parents": [ "b57f48f77f367c43cd83878d92aa55de151c0798" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Wed Apr 15 12:59:42 2020 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:04:53 2022 +0000" }, "message": "chipset_enable.c: Disable SPI on ICH7 if booted from LPC\n\nCommit 92d6a86 (\"Refactor Intel Chipset Enables\") eliminated a check\nto disable SPI when ICH7 has booted from LPC, as the hardware does not\nsupport it. Therefore, when flashrom probes the SPI bus, it times out\nwaiting for the hardware to react, for each and every SPI flash chip.\nThis results in very long delays and countless instances of the error:\n\n Error: SCIP never cleared!\n\nTo prevent this, bring back part of the lost check. Probing for LPC and\nFWH when booted from SPI does not seem to cause any problems on desktop\nmainboards with ICH7, so don\u0027t disable LPC nor FWH if that is the case.\n\nTested on ECS 945G-M4 (ICH7, boots from LPC), works without errors.\n\nChange-Id: I5e59e66a2dd16b07f2dca410997fce38ab9c8fd1\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/40401\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67863\nReviewed-by: Elyes Haouas \u003cehaouas@noos.fr\u003e\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "b57f48f77f367c43cd83878d92aa55de151c0798", "tree": "d2b42aa861392afb20d841ec86a1c860abd90a05", "parents": [ "b428c319ed629bef50e7e154c472635f68ea8edc" ], "author": { "name": "Patrick Georgi", "email": "pgeorgi@google.com", "time": "Sat May 02 16:07:11 2020 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:04:47 2022 +0000" }, "message": "spi95: Check for success before using send_command\u0027s returned data\n\nIf the transfer failed, the data might be invalid.\n\nChange-Id: I3ad9daa00a54e2a3954983cec91b6685f1a98880\nFound-By: Coverity Scan #1405870\nSigned-off-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/40970\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67862\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "b428c319ed629bef50e7e154c472635f68ea8edc", "tree": "f0ef56e854f7f1a7e37a722ef5404724e03ab3e0", "parents": [ "5ac6a637b07ea05a363ede3643ff627913378a2a" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Wed May 27 12:15:51 2020 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:04:40 2022 +0000" }, "message": "libflashrom.c: Use casts on enum conversions\n\nThis allows flashrom to build with GCC 10.\n\nChange-Id: I2166cdf3681452631ef8e980face2924e9a6c81a\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/41775\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67861\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-by: Elyes Haouas \u003cehaouas@noos.fr\u003e\n" }, { "commit": "5ac6a637b07ea05a363ede3643ff627913378a2a", "tree": "814e336db7b38ecdf8a1fd6602203c75438a6a2a", "parents": [ "05c629be2964bcee368c03d805747da15281856d" ], "author": { "name": "Patrick Georgi", "email": "pgeorgi@google.com", "time": "Wed Oct 28 17:29:38 2020 +0100" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:04:34 2022 +0000" }, "message": "test_build.sh: Move build test procedure to repository\n\nInstead of hard coding the test procedure on qa.coreboot.org, allow\nrunning a script in the repo instead. The server is already adapted\nto do that, so once there\u0027s a test_build.sh file in the toplevel\ndirectory, it\u0027s run in place of the default operation.\n\nThe content of this change mirrors the default operation exactly so\nshould serve as a good starting point.\n\nThe script is executed in an encapsulate[0] context with the workspace,\n/tmp and $HOME/.ccache writable, everything else read-only and\nnetwork disabled.\n\nIt should return 0 on success, anything else on failure, as is normal\nfor UNIX processes.\n\n[0] https://review.coreboot.org/cgit/encapsulate.git\n\n(Backported minus the Meson support)\n\nChange-Id: I37a8e925d1b283c3b8f87cb3d0f1ed8920f2cf95\nSigned-off-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/46894\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/62617\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67860\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "05c629be2964bcee368c03d805747da15281856d", "tree": "ffe6f7df4ee0ba5a76e58f739200cc6b3e0383e2", "parents": [ "b5433b782ff7cbde14ebd91aeac27efaec83e9d0" ], "author": { "name": "Bernhard Urban-Forster", "email": "lewurm@gmail.com", "time": "Sun Feb 02 21:29:48 2020 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Feb 09 06:21:46 2020 +0000" }, "message": "flashchips: Add Spansion S25FL512S\n\nAs found on the Tesla AP2.5 board.\n\nBased on https://mail.coreboot.org/pipermail/flashrom/2013-June/011066.html\n\nTested with:\n flashrom -p linux_spi:dev\u003d/dev/spidev0.0,spispeed\u003d512 -r content.bin\n\nSigned-off-by: Bernhard Urban-Forster \u003clewurm@gmail.com\u003e\nChange-Id: Ifa9b7615951125b6bbc1f051370ef54896bf506c\nReviewed-on: https://review.coreboot.org/c/flashrom/+/38596\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "b5433b782ff7cbde14ebd91aeac27efaec83e9d0", "tree": "facd5500f80682ce09fe7135362df5f4e7a87609", "parents": [ "3eae69531936cc41f227a532efea4cc3598d0f68" ], "author": { "name": "Johanna Schander", "email": "git@mimoja.de", "time": "Sun Dec 29 15:16:14 2019 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Feb 09 06:00:51 2020 +0000" }, "message": "chipset_enable.c: Add Ice Lake U to known and tested systems\n\nIntel Ice Lake systems use an 495 Series Chipset\nthat behaves compatible to pch300 chips but chip names\nare undocumented at this point.\n\nThis change was tested in read/write/erase on the Razer\nBlade Stealth (late 2019) with intel 1065G7 CPU and\n\"Ice Lake U Premium PCH\".\n\nChange-Id: I6227d32f4476420cf1aeec37ebd4b7648e0b3d15\nSigned-off-by: Johanna Schander \u003cgit@mimoja.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/37987\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Christoph Pomaska \u003cgithub@slrie.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "3eae69531936cc41f227a532efea4cc3598d0f68", "tree": "ba6a15846f4d3776eb8806eb21971721adf7e25c", "parents": [ "3799a1cc1adda28bb8bd4464020a7bbadd3960f1" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Fri Jan 31 10:53:47 2020 +0100" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat Feb 01 17:36:22 2020 +0000" }, "message": "Fix building with meson, again\n\nChange-Id: Iea40da587729f3975a8901d3933e7567805242c5\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/38659\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Frans Hendriks \u003cfhendriks@eltan.com\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "3799a1cc1adda28bb8bd4464020a7bbadd3960f1", "tree": "d654267ccdf97429733da5e0c07560be27a9d6f1", "parents": [ "e4c2b48f39902c7ff49a6a9e29525bdd3092c412" ], "author": { "name": "Wim Vervoorn", "email": "wvervoorn@eltan.com", "time": "Mon Jan 20 15:01:54 2020 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jan 22 14:15:33 2020 +0000" }, "message": "chipset_enable: Add Kaby Lake U Prem. to known and tested systems\n\nIntel Kaby Lake U (with the 9d4e device id) support is available but\nmarked not tested.\n\nTested reading, writing and erasing both internal flash chips on the\nFacebook Monolith system with the Intel i3 7100U SoC. However, since all\nME-enabled chipsets are marked as DEP instead of OK, this one shall follow\nsuit as well.\n\nSigned-off-by: Wim Vervoorn \u003cwvervoorn@eltan.com\u003e\nChange-Id: Ie35cc896e29baffa63fe9e37c14770001b54e7ec\nReviewed-on: https://review.coreboot.org/c/flashrom/+/38481\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "e4c2b48f39902c7ff49a6a9e29525bdd3092c412", "tree": "58008ef76cc0d8540ab5bf4cce80973e9fa05a59", "parents": [ "67710afe4e34f63a6e7b28d5493753caa8e79a52" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Mon Jan 20 11:22:41 2020 +0100" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Mon Jan 20 13:02:48 2020 +0000" }, "message": "Fix typos\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nChange-Id: Ia5ed00c488b0719b2bdd6c8f304900511684f445\nReviewed-on: https://review.coreboot.org/c/flashrom/+/38477\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "67710afe4e34f63a6e7b28d5493753caa8e79a52", "tree": "0edfe8de4e07350a7e89115d1532a24f130f6072", "parents": [ "370a9f3eea20a575f32ebf6ecead7ccf7562a2c0" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jan 18 18:23:22 2020 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 19 23:48:48 2020 +0000" }, "message": "Revert \"pcidev.c: Factor out pcidev_validate() into pure fn\"\n\nThis reverts commit e28d75ed7204d7fac2c0fac13978098530b0574e.\n\nThis is broken in multiple ways, e.g. pcidev_init() can only return\nNULL.\n\nChange-Id: I06242147ba9d3a062d442f645eb0800ef51af19f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nReported-by: Michael Bishop \u003ccleverca22@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/38319\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "370a9f3eea20a575f32ebf6ecead7ccf7562a2c0", "tree": "859c8e755786dad4b6e08f4343a2129efad3f01b", "parents": [ "324929c3d725ce264b2390525dbc9070f6029cc4" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Dec 31 18:22:02 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 02 16:15:10 2020 +0000" }, "message": "stlinkv3_spi: Move a declaration out of for-loop head\n\nGCC 4.8 wants an explicit `-std\u003dc99` or something for this to work. It\nseems easier to keep the common declaration style.\n\nChange-Id: Ic0819f82169df4d66cc949494229b0749c06e8f6\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/38034\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Miklós Márton \u003cmartonmiklosqdev@gmail.com\u003e\n" }, { "commit": "324929c3d725ce264b2390525dbc9070f6029cc4", "tree": "73ee656c8bc1933329e4239214e4b0eaaadb36f8", "parents": [ "728062f7ff7c2dca31bc99fe45eb5cacd7cf2d53" ], "author": { "name": "Miklós Márton", "email": "martonmiklosqdev@gmail.com", "time": "Thu Aug 01 19:14:10 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Dec 31 17:25:41 2019 +0000" }, "message": "Add support for STLINK V3 debugger/programmer via its SPI bridge\n\nChange-Id: Icffab87ac8f2c570187ed753ec70f054541873a4\nSigned-off-by: Miklós Márton \u003cmartonmiklosqdev@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34661\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "728062f7ff7c2dca31bc99fe45eb5cacd7cf2d53", "tree": "8df82988b92b7b091358e72570671d908016a08a", "parents": [ "a9d6d1a817ce20e834fe7c354629976e3e5f1108" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Wed Dec 18 00:26:15 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 21 11:47:21 2019 +0000" }, "message": "chipset_enable.c: Mark Intel HM76 as DEP\n\nTested reading, writing and erasing the internal flash chip using a\nSamsung NP530U3C laptop with an Intel HM76 PCH. However, since all\nME-enabled chipsets are marked as DEP instead of OK, this one shall\nfollow suit as well.\n\nChange-Id: I1097c5fcf782e7ecf52f05c571ad188456307d00\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/37803\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "a9d6d1a817ce20e834fe7c354629976e3e5f1108", "tree": "657071019f73d3b3070be348a73949544e6312b4", "parents": [ "34d07f00b2990bec4a2ce12852acd42c08ddf217" ], "author": { "name": "David Hendricks", "email": "dhendrix@chromium.org", "time": "Tue Nov 19 19:29:26 2019 -0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 14 15:50:36 2019 +0000" }, "message": "mysteries_intel: Add a section about SMM_BWP\n\nSomething to point users to when SMM_BWP might be causing problems.\n\nChange-Id: I394c033e8d4ff96433162f86aefb428d8acf6349\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36986\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "34d07f00b2990bec4a2ce12852acd42c08ddf217", "tree": "17ca5823749ac67144dc8e50c3f4c9b2f982522a", "parents": [ "4139438943010c7aec6549d8b18865da5b70e978" ], "author": { "name": "Rosen Penev", "email": "rosenp@gmail.com", "time": "Tue Jul 02 00:14:01 2019 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 14 15:29:21 2019 +0000" }, "message": "flashrom: Add support for ARC platform\n\nSigned-off-by: Rosen Penev \u003crosenp@gmail.com\u003e\nChange-Id: I88cbe74b716d5fab16133fbf2ce9c35b74c25f32\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35831\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "4139438943010c7aec6549d8b18865da5b70e978", "tree": "0c517723249fe9a4065ee2b52603d34a385290a6", "parents": [ "89622674b29c09bb33cb5844520d9271ebef8ea0" ], "author": { "name": "darkarnium", "email": "peter.adkins@kernelpicnic.net", "time": "Mon Nov 04 20:06:48 2019 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 14 15:25:30 2019 +0000" }, "message": "flashchips: Add AT25SF321\n\nThis commit adds support for the Adesto AT25SF321 SPI flash chip. Probe\nand read operations have been tested via FT2232H interface, but writes\nhave not been verified.\n\nDatasheet is available at the following URL:\nhttps://www.adestotech.com/wp-content/uploads/DS-AT25SF321_047.pdf\n\nChange-Id: I7410815e063ffe154a97d7ea5881c8eb82025f56\nSigned-off-by: Peter Adkins \u003cpete@kernelpicnic.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36904\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "89622674b29c09bb33cb5844520d9271ebef8ea0", "tree": "76f3035d59461fc0e70fee40e00ef410ea011769", "parents": [ "5d068ddca4aa8c657bbf3e7df8cf94c8e3212ada" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 10 18:05:55 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Dec 10 16:38:50 2019 +0000" }, "message": "nicintel_eeprom: Reduce usage of is_i210()\n\nDon\u0027t entagle the code paths for the two NIC classes if it\u0027s not necessary.\n\nOnly compile tested.\n\nChange-Id: I59164ccf54afbbd64a0598282d13e80ff7fd6fa4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33637\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "5d068ddca4aa8c657bbf3e7df8cf94c8e3212ada", "tree": "b7b401c7dbdfa20aee86e70574cdcb77bda6f468", "parents": [ "7bd31a435b7c8f2b278b9e8233083ff2134abe2d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 17 13:39:46 2019 +0100" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Fri Dec 06 02:50:41 2019 +0000" }, "message": "Revert \"print.c: Dedup \u0027test_state_to_text()\u0027 logic\"\n\nThis reverts commit 61e16e549a52194ac80ef40504f2dc661d1ff99c.\n\nObviously throws alignment in the table off and changes output\nclass from `general` to `programmer` for no visible reason.\n\nChange-Id: I864044b9fac6af9cf6a89c053eccdcb36f17c7bd\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36909\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "7bd31a435b7c8f2b278b9e8233083ff2134abe2d", "tree": "a9f64423fa32bbb53adaa48eb08812d1274039b9", "parents": [ "e28d75ed7204d7fac2c0fac13978098530b0574e" ], "author": { "name": "Russ Dill", "email": "Russ.Dill@gmail.com", "time": "Wed Oct 30 00:40:43 2019 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Dec 01 22:23:08 2019 +0000" }, "message": "ft2232_spi: Add support for Tin Can Tools Flyswatter/Flyswatter 2\n\nThe Tin Can Tools Flyswatter and Flyswatter 2 have a FT2232H\nwith a JTAG interface wired to port A. The buffers that drive the\nJTAG pins need to be enabled with an nOE signal from the\nFT2232H ADBUS6 and ADBUS7 pins.\n\nFlyswatter has an ARM-14 JTAG interface and Flyswatter 2 has\nan ARM-20 JTAG interface.\n\nChange-Id: I56b1fb76dcda32bb02980cd54a2853506bfc9dfd\nSigned-off-by: Russ Dill \u003cRuss.Dill@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36896\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "e28d75ed7204d7fac2c0fac13978098530b0574e", "tree": "324401adc58b52b390684e05be4c96f79f51c236", "parents": [ "1d80d645875cde4aa1ea17bd1d166619bed09682" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Wed Nov 27 16:44:19 2019 +1100" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Thu Nov 28 14:00:52 2019 +0000" }, "message": "pcidev.c: Factor out pcidev_validate() into pure fn\n\nThis makes writing unit-tests easier.\n\nChange-Id: Ia2718f1f40851d3122741cd0e50b0c2b647b727a\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/37264\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "1d80d645875cde4aa1ea17bd1d166619bed09682", "tree": "f40bdbc0af4782ffc5c91fb0b7b986268d3bca2b", "parents": [ "4a55e6885816aa2a45314975686356ce282cae5c" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Nov 26 23:31:06 2019 +1100" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Thu Nov 28 10:00:21 2019 +0000" }, "message": "cbtable.c: Factor out lb_table_validation logic\n\nWrite a pure function for the table validation logic, it is\neasier to unit-test.\n\nChange-Id: I07b0f95ec0443fa6a8f54eb93f4a7ea1875cccad\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/37239\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n" }, { "commit": "4a55e6885816aa2a45314975686356ce282cae5c", "tree": "e689df39d5b23b188196c98fa5feb4ad5b85afee", "parents": [ "61e16e549a52194ac80ef40504f2dc661d1ff99c" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Nov 26 23:28:05 2019 +1100" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Thu Nov 28 10:00:11 2019 +0000" }, "message": "cbtable.c: Factor out lb_header_validation logic\n\nWrite a pure function for the header validation logic, it is\neasier to unit-test.\n\nChange-Id: Ia288bcbc5c371329952a6efba30ccf0e18965a3d\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/37238\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "61e16e549a52194ac80ef40504f2dc661d1ff99c", "tree": "7531df670485b94cd5d1337115eb133e013d0928", "parents": [ "301ae22b456a040d8944daa0268aa97aa93a517f" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Sun Nov 17 14:29:33 2019 +1100" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Sun Nov 17 11:32:46 2019 +0000" }, "message": "print.c: Dedup \u0027test_state_to_text()\u0027 logic\n\nChange-Id: I72164323d7ff98fc50cb0c47b69741a4f047e098\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36905\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "301ae22b456a040d8944daa0268aa97aa93a517f", "tree": "31fcd3538c0d36fa43c392a86fc4c6383809cf0a", "parents": [ "83c56b870bcf0d241993813b9f695c2118532f7a" ], "author": { "name": "Ryan O\u0027Leary", "email": "ryanoleary@google.com", "time": "Mon Jun 24 19:14:33 2019 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 15 09:29:37 2019 +0000" }, "message": "dediprog.c: Add id parameter to dediprog programmer\n\nWhen multiple dediprog programmers are connected, the \u0027id\u0027 parameter\nallows you to specify which one to use. The id is a string like SF012345\nor DP012345. The value is printed on a sticker on the back of the dediprog.\n\nThis is an improvement over the \u0027device\u0027 parameter which is based on\nenumeration order and changes when you plug/unplug devices or reboot the\nmachine.\n\nTo find the id without the sticker, run flashrom with the -V option.\nThis prints the ids as they are enumerated. Alternatively, with dpcmd,\nyou can use the --list-device-id and --fix-device commands to list and\nwrite device ids respectively.\n\nNote this only supports SF100 at the moment, but SF600 support is\npossible with more work.\n\nChange-Id: I4281213ab02131feb5d47bf66118a001cec0d219\nSigned-off-by: Ryan O\u0027Leary \u003cryanoleary@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34160\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "83c56b870bcf0d241993813b9f695c2118532f7a", "tree": "81af4dcd1d8c6b94343b8b230e18a6f802e47382", "parents": [ "93737bcaf5e9c54501eb411b84c3b32e2dff944a" ], "author": { "name": "Evgeny Zinoviev", "email": "me@ch1p.com", "time": "Tue Nov 05 17:47:43 2019 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Nov 14 22:47:32 2019 +0000" }, "message": "Fix building with GCC 4.9\n\nIt doesn\u0027t like empty initializers.\n\nChange-Id: If2988e60401155f87ee3369c77f00ccf9332012c\nSigned-off-by: Evgeny Zinoviev \u003cme@ch1p.io\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36629\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "93737bcaf5e9c54501eb411b84c3b32e2dff944a", "tree": "8accecfc9ff20ed5dd1fdab7c51ae0ef9e690a9e", "parents": [ "9355e6faf66653655cef5ab312c00e70582fe595" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Oct 29 18:30:01 2019 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Nov 14 22:42:37 2019 +0000" }, "message": "sb600spi.c: Generalise determin_generation() after Yangtze\n\nDrop dead USE_YANGTZE_HEURISTICS code and add Promontory support.\n\nChange-Id: I5aa7370025f5c1af56c6cb96194b6f3007d0ede7\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36426\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "9355e6faf66653655cef5ab312c00e70582fe595", "tree": "f270bcba5757d3efa66f841d697aa25956a3d485", "parents": [ "c0a27e1f1748650726d81f1c00c1ebd440f3ea38" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Oct 29 18:18:18 2019 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Nov 14 22:42:22 2019 +0000" }, "message": "sb600spi.c: Fold up debug logic into determine_generation()\n\nChange-Id: I6c722e29b321285bf20fb5ee30c912dcdd83411b\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36425\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "c0a27e1f1748650726d81f1c00c1ebd440f3ea38", "tree": "7c7b0f7a03e7deb33ce9df99ee9fff1cc9db78fc", "parents": [ "2d20d6db39547f013b66230f378ceb8e21fa36e3" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Oct 29 17:05:39 2019 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Nov 14 22:41:10 2019 +0000" }, "message": "sb600spi.c: Consolidate smbus dev revision derivation\n\nV.2: Rename \u0027find_smbus_dev()\u0027 -\u003e \u0027find_smbus_dev_rev()\u0027.\n\nChange-Id: I766b29cc1c7d01aa0bcf6cb9ff5ab73fa1995dcd\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36420\nReviewed-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "2d20d6db39547f013b66230f378ceb8e21fa36e3", "tree": "7816f91833c2540ec74f97fe5de4ad4dd81165e0", "parents": [ "1a119498b43a8ed934bcfa0a16465aa4d6d2c74d" ], "author": { "name": "Miklós Márton", "email": "martonmiklosqdev@gmail.com", "time": "Tue Jan 30 20:20:15 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Nov 14 22:40:21 2019 +0000" }, "message": "Add support for National Instruments USB-845x devices\n\nChange-Id: I9477b6f0193bfdf20bbe63421a7fb97b597ec549\nSigned-off-by: Miklós Márton \u003cmartonmiklosqdev@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/25683\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "1a119498b43a8ed934bcfa0a16465aa4d6d2c74d", "tree": "65860cc7d10787128bc90609af22e74ec1465f39", "parents": [ "80e8dc4df72b72170190a91c31cdc0a0b5e08358" ], "author": { "name": "Peichao Wang", "email": "peichao.wang@bitland.corp-partner.google.com", "time": "Mon Nov 11 15:26:41 2019 +0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Nov 13 12:32:11 2019 +0000" }, "message": "flashchips: Add W25Q128JW_DTR\n\nPort the code from chromeos flashrom\n\nBUG\u003db:144297264\nTEST\u003dTested using W25Q128JWDTR in SPI mode\n\nSigned-off-by: Peichao.Wang \u003cpeichao.wang@bitland.corp-partner.google.com\u003e\nChange-Id: Ifc28878b17dc10da2cfd8f82fffbd57adb22799e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36717\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "80e8dc4df72b72170190a91c31cdc0a0b5e08358", "tree": "c706ef2c5e7d1f2a69e70218b849f7c461e8b7ff", "parents": [ "2f6936bd926b6d4f21680e2cdc160fc580c3ecb3" ], "author": { "name": "Jacob Creedon", "email": "jcreedon@google.com", "time": "Mon Jul 22 12:35:30 2019 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Mon Nov 11 02:53:01 2019 +0000" }, "message": "flashchips: Add missing N25Q/MT25Q variants\n\nThis adds missing voltage and capacity variants for N25Q and MT25Q\nseries devices. This also fixes a typo in some model numbers where the\nlast letter should have been a G instead of an E. Added devices include:\n\nN25Q256..1E\nN25Q512..1G\nN25Q00A..1G\nN25Q00A..3G\nMT25QU128\nMT25QL128\nMT25QU256\nMT25QU512 tested by Jacob Creedon \u003cjcreedon@google.com\u003e\nMT25QL01G tested by Konstantin Grudnev \u003cgrudnevkv@gmail.com\u003e\nMT25QU01G\nMT25QL02G\nMT25QU02G\n\nTwo have been tested as indicated, all other variants added are marked\nuntested.\n\nSigned-off-by: Jacob Creedon \u003cjcreedon@google.com\u003e\nChange-Id: I85630e4f6c0aa3b261f9871b7d363dad278b997e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34491\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "2f6936bd926b6d4f21680e2cdc160fc580c3ecb3", "tree": "b58cac0e2009b908f72907c7b098c2de4065c768", "parents": [ "b863127a6f6e538c60fb66716db6aaa44d8726ff" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Sep 24 18:31:38 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Nov 06 08:46:07 2019 +0000" }, "message": "util/getversion,meson: Add script to allow version info with Meson\n\nAdd `util/getversion.sh` that retrieves version information from a\n`versioninfo.inc` (what we use for releases) if present or uses\n`util/getrevision.sh` if not.\n\nLet Meson use it for flashrom\u0027s version. It seems Meson doesn\u0027t\ngenerate the manual page at all, so the `--man-date` command is\ncurrently unused.\n\nChange-Id: I401e5638509c4a573bc0cb17ebc5fa76df9700b5\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35561\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Mario Limonciello \u003csuperm1@gmail.com\u003e\nReviewed-by: Richard Hughes \u003chughsient@gmail.com\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "b863127a6f6e538c60fb66716db6aaa44d8726ff", "tree": "e4615225e92210e624e96c9396d797933102ea09", "parents": [ "8b60fc7a5bac409f8a4e0648f1fba51aa3497afb" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Oct 22 10:46:04 2019 +1100" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Oct 22 23:24:16 2019 +0000" }, "message": "usbdev.c: Add missing \u003cinttypes.h\u003e include\n\nChange-Id: Ie23612226a48d6732750f51547642da0a6257dd8\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36219\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "8b60fc7a5bac409f8a4e0648f1fba51aa3497afb", "tree": "8ce22803fb0e3410725e5719bae4f36de162045f", "parents": [ "16ec45c0fc9ad172b66f07a94c64a3a17c111ca0" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Thu Sep 26 11:17:20 2019 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 17 08:29:35 2019 +0000" }, "message": "cli_classic: Tidy up some repeated handling patterns into funcs\n\nIntroduce cli_classic_single_operation() to consolidate the repeating\npattern of multiple CLI operations at once. Also modify\ncli_classic_abort_usage() to take an optional error abort string and\nprint it to stderr, this allows for trimming a few more lines off the\ncli implementation.\n\nV.2: A few fixes upon review:\n - Trim off some unnecessary braces for single line branches.\n - Pass \u0027operation_specified\u0027 by reference.\n - Rename a function.\nV.3: Fix print order of cli_classic_abort_usage().\n\nChange-Id: I54598efdaee2b95cb278b0f2aac05f48bbd95bef\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35611\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "16ec45c0fc9ad172b66f07a94c64a3a17c111ca0", "tree": "88cc20846088743086e4a678d6cee118a662790f", "parents": [ "2a8d4390fa85160b79f9ccf3d2a8c676595611e7" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Fri Oct 04 20:24:53 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Thu Oct 17 01:26:21 2019 +0000" }, "message": "cli_classic: Fix first line of --help to match manpage\n\nMake the first line of --help in usage to align with the\nformat of the man page, including fixing any missing options.\n\nV.2: Add an extra space.\n\nChange-Id: I44f82c6a54fddb54bf268fe6eb22e50acb6025cf\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35793\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "2a8d4390fa85160b79f9ccf3d2a8c676595611e7", "tree": "e96562b5fc1efc245014ccf8dae5caf85b04e4bd", "parents": [ "d954d5d700d7aa2ff144e7f8a5a2b6df08b07590" ], "author": { "name": "Mario Limonciello", "email": "mario.limonciello@dell.com", "time": "Tue Oct 15 13:32:19 2019 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 16 21:50:27 2019 +0000" }, "message": "Correct the pkgconfig generated file naming\n\nThe typical convention is to not use the `lib` prefix (ie `libfoo`)\nbut instead to just use foo.\n\nChange-Id: I5ab46418e2a1708d5c11970f1e56250f2adb7d70\nSigned-off-by: Mario Limonciello \u003cmario.limonciello@dell.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36069\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Richard Hughes \u003crichard@hughsie.com\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "d954d5d700d7aa2ff144e7f8a5a2b6df08b07590", "tree": "6babb137bb091429368d23f745f75713295f0dde", "parents": [ "e0ceedf76d48757a05f22860e7ddd03e430c2252" ], "author": { "name": "Mario Limonciello", "email": "mario.limonciello@dell.com", "time": "Tue Sep 24 16:06:57 2019 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 16 21:47:13 2019 +0000" }, "message": "meson.build: Sanitize the version string\n\nMatch strictly the library version, and remove all starting letters.\n\nChange-Id: I25587ed2ad7fbcffdf14eb758c1f0d6ab2aea545\nSigned-off-by: Mario Limonciello \u003cmario.limonciello@dell.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35566\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Richard Hughes \u003crichard@hughsie.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "e0ceedf76d48757a05f22860e7ddd03e430c2252", "tree": "e74511724d0f856e267825b1bafabe143260164c", "parents": [ "28d081924ea6fca7a643ae273cb56cd11788adc5" ], "author": { "name": "Fabrice Fontaine", "email": "fontaine.fabrice@gmail.com", "time": "Wed Jul 17 19:04:12 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 16 19:30:57 2019 +0000" }, "message": "linux_spi: reorder includes for linux \u003c4.14\n\nThis works around a missing header in spidev.h present in older\nversions of Linux. Patch is ported from:\nhttps://git.buildroot.net/buildroot/tree/package/flashrom/0001-spi.patch\n\nSigned-off-by: \"Yann E. MORIN\" \u003cyann.morin.1998@free.fr\u003e\nSigned-off-by: Fabrice Fontaine \u003cfontaine.fabrice@gmail.com\u003e\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nChange-Id: Ieab60f59bc63aca0dc4867f31699dab4167da05b\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35830\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "28d081924ea6fca7a643ae273cb56cd11788adc5", "tree": "f8b63bb8fc1337da5d76cb262cd4ce1728e2a7d4", "parents": [ "7f15de164c2b6fcb82fb9634d5d43a2368338ac3" ], "author": { "name": "David Hendricks", "email": "dhendrix@chromium.org", "time": "Sun Sep 08 13:59:42 2019 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Mon Oct 14 05:23:01 2019 +0000" }, "message": "util/git-hooks: Check for Signed-off-by line\n\nEnforce the DCO. The logic comes from coreboot\u0027s commit-msg hook,\nand I\u0027ve added a pointer to flashrom\u0027s development guidelines.\n\nChange-Id: Iea49a06c2d4824be073eff98c8aae1cbc5b145e4\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35295\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "7f15de164c2b6fcb82fb9634d5d43a2368338ac3", "tree": "68bc0a0affb1705f828c6b956f007bb64cf5bb37", "parents": [ "d58128eb83e59e09113666c80da81c891d76e949" ], "author": { "name": "Jonathan Liu", "email": "net147@gmail.com", "time": "Sun Oct 06 16:22:04 2019 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 08 18:12:26 2019 +0000" }, "message": "Fix compilation if CONFIG_INTERNAL\u003dno\n\nChange-Id: Id9e07332003832465a0eccf1d89e73d15abb35c0\nSigned-off-by: Jonathan Liu \u003cnet147@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35808\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "d58128eb83e59e09113666c80da81c891d76e949", "tree": "8ef79ded03a5d02eac66c0dde923a24fcd8408b2", "parents": [ "9e2dc2fc818cc9c1b46924e103ce669ad154b7ab" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Oct 06 21:07:44 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 08 09:59:22 2019 +0000" }, "message": "chipset_enable.c: Mark Intel Q75 as DEP\n\nTested reading, writing and erasing the internal flash chip using an HP\nPro 6300 SFF mainboard with an Intel Q75 PCH. However, since ME-enabled\nchipsets are marked as DEP instead of OK, this one shall also be.\n\nChange-Id: I273af0eb33e74b31bc4fdc95362527bba080c5a0\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35826\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "9e2dc2fc818cc9c1b46924e103ce669ad154b7ab", "tree": "0aa6df52053c8e7cb9a04614551ce0779c589e3e", "parents": [ "5374dc3461f1e74a56a4db1a8d684b29cb3a92e5" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 23 22:00:47 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 05 23:36:34 2019 +0000" }, "message": "Makefile,meson.build: Enable/assume -Wextra\n\nEnable all -Wextra warnings but -Wunused-parameter. Nobody seems to\nmiss warnings about unused parameters and we have a lot unavoidable\noccurrences in flashrom because of common interfaces.\n\nChange-Id: Id2ece264c2d483e34019985dd3a7631c4889abe6\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30411\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\n" }, { "commit": "5374dc3461f1e74a56a4db1a8d684b29cb3a92e5", "tree": "311ed873936176c06226c160ea04a574a3cbe046", "parents": [ "92b17a52a3aaec7e87aabfc6ce5f05726d1000c0" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 04 16:16:15 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 05 23:33:22 2019 +0000" }, "message": "flashchips: Add missing block erasers for GD25Q256D\n\nChange-Id: I7e49e468c7f1eaf0ddd5fc08d6cc6569274faf94\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35798\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "92b17a52a3aaec7e87aabfc6ce5f05726d1000c0", "tree": "1f2789021c48219aa78b0a2fdea8b1d7fb288353", "parents": [ "961f4a1f29787cbb6bd9a8a43b6ac4f3f0d024c0" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 04 18:47:24 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 05 23:27:00 2019 +0000" }, "message": "board_enable: Work around -Wtype-limits issue\n\nIn case of an empty `board_matches` list (i.e. on non-x86), we checked\nif the `unsigned i` is smaller 0. Shuffling the computation avoids that\nproblem.\n\nChange-Id: I636d73c920a7b7e7507eafe444bab8236d7acb67\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35801\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nReviewed-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\n" }, { "commit": "961f4a1f29787cbb6bd9a8a43b6ac4f3f0d024c0", "tree": "13023be2c6cc0140cbfa97dee108a441e696b638", "parents": [ "b417c0c2d2616feff30cc87316a278055da8c64a" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 04 17:34:22 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 05 23:26:25 2019 +0000" }, "message": "Fix more sign-compare issues\n\nThe one in the `dummyflasher` is a little peculiar. We actually never\nknew the type of the `st_size` field in `struct stat`. It happens to\nbe `signed` in some systems (e.g. DJGPP).\n\nChange-Id: If36ba22606021400b385ea6083eacc7b360c20c5\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35800\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nReviewed-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\n" }, { "commit": "b417c0c2d2616feff30cc87316a278055da8c64a", "tree": "9143a7e9b1b9b25e1d1e172cb1ee2fd5076d14ce", "parents": [ "349b5d24345c5a550c0e38cf26452c6338cc1c12" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Sep 24 22:12:40 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 05 22:45:20 2019 +0000" }, "message": "meson: Correct license to GPL-2.0\n\nParts of flashrom are 2.0+ but some are not. As Meson\u0027s purpose is to\nlink these together, it should advertise only GPL-2.0 for the whole.\n\nChange-Id: Iab99c74f5f9d54dac56085ecc7475b14be00a310\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35584\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "349b5d24345c5a550c0e38cf26452c6338cc1c12", "tree": "3a300f5d2819d91db2a8a0ee3f81c399127065e3", "parents": [ "3d8868c2b46548be6885198987492d91933c9ff7" ], "author": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sat Oct 05 12:44:27 2019 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sat Oct 05 20:19:36 2019 +0000" }, "message": "meson: Add spi95.c to fix the build\n\nReported in issue #105 on github.\n\nChange-Id: Ibe484b4ef60533135fa1e96eb203bb55985d1f8e\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35819\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "3d8868c2b46548be6885198987492d91933c9ff7", "tree": "2277db98f8b19982802f812b2a984a2591009e37", "parents": [ "4a84ec273a487c27f91bd3df70cbdf8894af70e1" ], "author": { "name": "Konstantin Grudnev", "email": "grudnevkv@gmail.com", "time": "Tue Jul 23 00:48:54 2019 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 04 17:41:01 2019 +0000" }, "message": "Add support for M95M02-A125\n\nAutomotive 2 Mbit (256KiB) serial SPI bus EEPROM\nPREW tested successfully with use of ch341a programmer\non Linux host 5.2.0-1-MANJARO x86_64\n\nSigned-off-by: Konstantin Grudnev \u003cgrudnevkv@gmail.com\u003e\nChange-Id: Ic29cd9051c7eac4822d620c299834134f987f01b\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34496\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "4a84ec273a487c27f91bd3df70cbdf8894af70e1", "tree": "faee09346d0a195ac778befa68a87c5f669cfe22", "parents": [ "de77ad4678cb33ca0b58edf89fab8113eb304bcd" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Thu Jul 25 19:12:31 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 04 14:35:20 2019 +0000" }, "message": "tree: Enable -Wwrite-strings\n\nWhen compiling, this warning gives string literals the type const char[]\nto help catch accidental modification (which is undefined behaviour).\nThere currently aren\u0027t any instances of this in flashrom, so let\u0027s\nenable this warning to keep it that way. This requires adding const\nqualifiers to the declarations of several variables that work with\nstring literals.\n\nChange-Id: I62d9bc194938a0c9a0e4cdff7ced8ea2e14cc1bc\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34577\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "de77ad4678cb33ca0b58edf89fab8113eb304bcd", "tree": "a4615817583239b756c969e72d8e9327f345b9ac", "parents": [ "8900d6c8e1438ee2a4a77c8e4d3feab81ee261e2" ], "author": { "name": "Miklós Márton", "email": "martonmiklosqdev@gmail.com", "time": "Tue Aug 06 22:43:19 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 04 11:11:47 2019 +0000" }, "message": "Add board enable for Asus P4P800SE\n\nSee github issue #32:\nhttps://github.com/flashrom/flashrom/issues/32\n\nChange-Id: I12b25ca3f85e5f2302681bddbe1adafa49c5fcb9\nSigned-off-by: Miklós Márton \u003cmartonmiklosqdev@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34764\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "8900d6c8e1438ee2a4a77c8e4d3feab81ee261e2", "tree": "5664d15b2f3ca63f9f96ef3284cbbf5c46499179", "parents": [ "7d6b526ef5b7b11f89eee37062e91590f5fa7f43" ], "author": { "name": "Miklós Márton", "email": "martonmiklosqdev@gmail.com", "time": "Tue Jul 30 00:03:22 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 04 11:03:46 2019 +0000" }, "message": "helpers: Implement strndup() for MinGW\n\nProvide strndup implementation if compiled with MinGW because\nit is a POSIX only method\n\nSigned-off-by: Miklós Márton \u003cmartonmiklosqdev@gmail.com\u003e\nChange-Id: If418080bffff1f5961cacf2a300ea9c666682458\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34621\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "7d6b526ef5b7b11f89eee37062e91590f5fa7f43", "tree": "c10247a7a5f2f15f83e9f55d1a85c03edb8d682f", "parents": [ "0cd11d8919c66351b9508f58ca0a7f7aaad6dd59" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Mon Sep 23 22:53:14 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Fri Oct 04 10:45:15 2019 +0000" }, "message": "cli_classic: Add convenient \u0027--{flash,get}-size\u0027 cli opt\n\nWe have this in the ChromiumOS fork of flashrom which we rely\non to obtain the current flash chip in use. This ports it for\nupstream consumption.\n\nV.2: Constrain number_of_operations to one as per Nico\u0027s comment.\nV.3: Rename \u0027--get-size\u0027 to \u0027--flash-size\u0027 however keep old arg as\n \u0027undocumented\u0027 for back-compat.\nV.4: Add missing --help line.\nV.5: Add man page entry.\nV.6: Use printf() directly.\n\nChange-Id: I8f002f3b2012aec4d26b0e81456697b9a5de28d6\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35592\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "0cd11d8919c66351b9508f58ca0a7f7aaad6dd59", "tree": "4034df1770ba21ccc57c9af8249e275cf2ea7352", "parents": [ "ca598dabc3e658b3b80fd41143417d884d436e06" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Mon Sep 23 22:46:12 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Fri Oct 04 10:43:50 2019 +0000" }, "message": "cli_classic: Add convenient \u0027--flash-name\u0027 cli opt\n\nWe have this in the ChromiumOS fork of flashrom which we rely\non to obtain the current flash chip in use. This ports it for\nupstream consumption.\n\nV.2: Constrain number_of_operations to one as per Nico\u0027s comment.\nV.3: Move two goto\u0027s outside inner if-else block.\nV.4: Add missing --help line.\nV.5: Add man page entry.\nv.6: Use printf() directly.\n\nChange-Id: I23d574a2f8eaf809a5c0524490db9e3a560ede56\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35591\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "ca598dabc3e658b3b80fd41143417d884d436e06", "tree": "9404e4002f46fb82bd9db759422274a06830fb31", "parents": [ "1c0c8fd9da34d29d549803f3ddff9a68dd95dfed" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Mon Aug 12 10:44:17 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Sep 24 19:12:51 2019 +0000" }, "message": "dummyflasher: Add error check for file read\n\nPrint an error message and return if the read from emu_persistent_image\nfails.\n\nChange-Id: Icd1a72f9171e547f2081ba4bc53834a17ef7fcab\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nFound-by: Coverity CID 1403912\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34845\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "1c0c8fd9da34d29d549803f3ddff9a68dd95dfed", "tree": "4cdf8d00d844fc0286f05cda7677d298d9ead6b9", "parents": [ "4a7970bc98c5bacd2cebcc2b4a3a39be304a1cae" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Mon Aug 12 14:14:40 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Sep 24 19:09:29 2019 +0000" }, "message": "linux_spi: Use fgets() to read buffer size\n\nSince fread() returns the number of bytes read, this currently will only\ncheck for errors if it returns 0 (i.e. the file was empty). However, it\nis possible for fread() to encounter an error after reading a few bytes,\nwhich this doesn\u0027t catch. Fix this by using fgets() instead, which will\nreturn NULL if EOF or an error is encountered, and is simpler anyway.\n\nChange-Id: I4f37c70e97149b87c6344e63a57d11ddde7638c4\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nFound-by: Coverity CID 1403824\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34848\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "4a7970bc98c5bacd2cebcc2b4a3a39be304a1cae", "tree": "edf5151351669ba16c2d845974997ad398494200", "parents": [ "ba7199958c9eef803845dcd9f3930277bbf9eb76" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Mon Aug 12 14:31:46 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Sep 24 19:07:45 2019 +0000" }, "message": "print: Fix vendor string memory leak\n\nFreeing this string won\u0027t really matter in the incredible case that we\nrun out of memory, but it keeps Coverity happy.\n\nChange-Id: I962d2f2227850473b70272bc48b3fc0a0fb11342\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nFound-by: Coverity CID 1403822\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34849\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "ba7199958c9eef803845dcd9f3930277bbf9eb76", "tree": "83b9c4c92e2d3c39e4e25d33a870a02f38ca3e1d", "parents": [ "1c091d1aebb055149c89f88fd5766ca4e33b7b3e" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Mon Aug 12 12:07:03 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Sep 24 19:07:02 2019 +0000" }, "message": "linux_mtd: Fix param memory leak\n\nextract_programmer_param() stores allocated memory in param, so make\nsure it is freed at the end of the function.\n\nChange-Id: I363e66b49c1ed4034ac058b94a938c8bb197e048\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nFound-by: Coverity CID 1403823\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34847\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "1c091d1aebb055149c89f88fd5766ca4e33b7b3e", "tree": "1ca7c754bcaaf1b9e8150af14af58a8a609838bf", "parents": [ "15f539c8c978e002f2b6397a7a74e1af817d5cb3" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Mon Aug 12 11:14:14 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Sep 24 19:02:48 2019 +0000" }, "message": "internal: Fix board vendor and model memory leaks\n\nThe board vendor and model are sometimes specified as arguments during\nan internal flash, so make sure they are freed at the end of\ninitialization.\n\nChange-Id: I9f43708f3b075896be67acec114bc6f390f8c6ca\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nFound-by: Coverity CID 1230664, 1230665\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34846\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "15f539c8c978e002f2b6397a7a74e1af817d5cb3", "tree": "933422f889c4d668cace147b383c4aa3a9b024a6", "parents": [ "a1fc01d9e2f28d3d5f1506117c11f35bd42a7a6a" ], "author": { "name": "David Hendricks", "email": "dhendrix@chromium.org", "time": "Thu Aug 26 21:27:17 2010 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Sep 24 18:49:09 2019 +0000" }, "message": "ichspi: Replace default JEDEC_BE_D8 with JEDEC_SE\n\nThis aligns the upstream master branch with chromium\u0027s. On-the-fly\nopcode reprogramming is supported by both branches so the default\nopcode shouldn\u0027t matter.\n\nReview URL: http://codereview.chromium.org/3239001\n\nChange-Id: I379549e8fa966e75e3d8b7932700df62cf50df64\nSigned-off-by: Mayur Panchal \u003cpanchalm@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34689\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "a1fc01d9e2f28d3d5f1506117c11f35bd42a7a6a", "tree": "c800a57c8c1bc4dc851ac939b289dd21ad03b33b", "parents": [ "07b8a17db65ad38ffcb7344192ba37d79f03193e" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Mon Sep 23 17:12:44 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Sep 24 03:20:55 2019 +0000" }, "message": "flashchips.c: Add W25Q128.V..M printlock attribute\n\nAdd a printlock attribute for the Winbond W25Q128.V..M chip. The\nprintlock attributes matches the ChromiumOS repo\u0027s definition of this\nchip.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I775d5d40677593dcb2d05750f8bbc62871b0e551\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35549\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "07b8a17db65ad38ffcb7344192ba37d79f03193e", "tree": "5f69f7abdcb32f73a25e14d9d0c4039385f84676", "parents": [ "86fc9cf7ab221bc54ef6f10252e296fc2d7a22d2" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Mon Sep 23 16:47:05 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Sep 24 03:19:00 2019 +0000" }, "message": "flashchips.c: Mark W25Q40EW as TESTED_PREW\n\nMark Winbond W25Q40EW as TESTED_PREW.\n\nThe Winbond W25Q40EW has been marked TESTED_PREW in the ChromiumOS\nrepository. ChromiumOS has the same defintion for this chip as this\nrepo, except that ChromiumOS does not have FEATURE_OTP.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I4be5b2e1069a3f735f0dc6ec92d5f4c8946fbb02\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35535\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "86fc9cf7ab221bc54ef6f10252e296fc2d7a22d2", "tree": "8ef1d074dab28dee198fe84fab0ef7dbccf7bfd2", "parents": [ "40f0757750f246bd78981fb7c02aadf1d47b18e8" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Mon Aug 26 15:02:12 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Sep 24 03:00:33 2019 +0000" }, "message": "flashchips.c: Add GD25Q256D from downstream\n\nTake definition of GD25Q256D from ChromiumOS repository.\n\nThis chip was added in `commit 0c38355c` by dlaurie@google.com\n2019-03-17.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I79d4ed48aa9126a8a6ce455a9564451346195b8f\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35480\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "40f0757750f246bd78981fb7c02aadf1d47b18e8", "tree": "81f42762d82c932b7024a1a403090ab1781a7ebe", "parents": [ "4362e629762857fefecd54fc970cdfbf5f9d6741" ], "author": { "name": "Mario Limonciello", "email": "mario.limonciello@dell.com", "time": "Thu Aug 29 14:19:21 2019 -0500" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Tue Sep 24 01:15:48 2019 +0000" }, "message": "libflashrom.h: Add types not included in all projects\n\nAdd \u003cstdbool.h\u003e and \u003cstdint.h\u003e to allow compilation in fwupd.\n\nSigned-off-by: Mario Limonciello \u003cmario.limonciello@dell.com\u003e\nChange-Id: Ib48ddc6412f82677f43e445346dc64ccfadf2423\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35155\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\n" }, { "commit": "4362e629762857fefecd54fc970cdfbf5f9d6741", "tree": "5a4d3dacda6d39344416481eab4b0586f1a3d691", "parents": [ "03707300db4369a8c197fdda0b7730d4a43182fd" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Mon Aug 26 15:02:12 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Wed Sep 18 01:20:33 2019 +0000" }, "message": "flashchips.c: Mark EN29F002(A)(N)B as tested +EW\n\nMark EN29F002(A)(N)B as tested for erase and write. This chip was marked\ntested in the Chromium (downstream) repo change\n98d917cfba55b68516cdf64c754d2f36c8c26722 \"Add a bunch of new/tested\nstuff and various small changes 8\"\n\nTEST\u003dBuild and run flashrom -L\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Idd26187905f389fc858eea5b13915af88e40afe9\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35092\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "03707300db4369a8c197fdda0b7730d4a43182fd", "tree": "38c72cfe7cee022776e9a71876738dadb9e39262", "parents": [ "4f00912c704ea6b69df8dc331199503b1c6739c3" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Mon Aug 26 12:50:43 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Sep 17 07:40:02 2019 +0000" }, "message": "flashchips.c: Identify MX25L25645G part\n\nApply downstream patch d978051c2e7da88088ec4ef19827c04873a5479d,\n\"flashrom: Identify MX25L25645G part\" from\nchris_zhou@compal.corp-partner.google.com 2019-04-13. Change description\nwas:\n\n\"\"\"\nMX25L25635F and MX25L25645G have the same chips identify. Add\nMX25L25645G to the name of the part so that it doesn\u0027t confused people.\n\"\"\"\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I317345b4753cfc46fdca8f673a0591e33b62138b\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35091\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "4f00912c704ea6b69df8dc331199503b1c6739c3", "tree": "18b7d84641364382629a82122b858bd5d90db5b3", "parents": [ "dd59220e7e774d3e8fa100cd0b448fa363e3be73" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Mon Aug 26 10:45:18 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Sep 17 06:29:47 2019 +0000" }, "message": "flashchips: Add GD25Q127C name to the GD25Q128C entry\n\nRenamed GigaDevice GD25Q128 to GD25Q127C/GD25Q128.\n\nAccording to downstream (ChromiumOS) change\n4216ba3d0fbd1804a71002b9c17e0b04029a03f1 \"flashchips: Add GD25Q127C name\nto the GD25Q128C entry\", the 127C chip is replacement for the 128C chip.\nI have confirmed that 127C is newer and that 128C does not appear to be\ndocumented on Gigadevice\u0027s website or available from Digikey.\n\nTEST\u003dRan flashrom -L\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I3366e5904eff2443fda90552f7f5e31a8785d8b3\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35089\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "dd59220e7e774d3e8fa100cd0b448fa363e3be73", "tree": "6d7c8fb007bf977a011c3b4b63bb906f5872b677", "parents": [ "71b706f544eff68657a15139c39b9f0d8c3b2940" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Fri Aug 23 10:11:37 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Sep 17 06:29:13 2019 +0000" }, "message": "flashchips.c: Put SFDP-capable chip back into position\n\nPut entry for Unknown SFDP-capable chip back into place at end of file.\n\nChange 1f9cc7d89992114c70f7a0545ad9f98701bebe56 \"flashchips.c: Sort file\nby vendor and model\" reordered many entries in flashchips.c, including\nthis one. However, the entry for Unknown, SFDP-capable chip should not\nhave been moved before any specific chip entries.\n\nAs reported by Angel Pons \u003cth3fanbus@gmail.com\u003e at\nhttps://review.coreboot.org/c/flashrom/+/33931:\n\n\"\"\"\nOops, this introduced a bug: the SFDP entry is no longer at the end of\nflashchips.c, so probing on a SFDP-capable Winbond chip results in added\nnoise (flashrom says things about an unknown chip, and then has two\ndefinitions for the same chip).\n\"\"\"\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I5955020456dbcd5e7db280a459b668a743e464dc\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35037\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "71b706f544eff68657a15139c39b9f0d8c3b2940", "tree": "c1dde02bfa7df1aeb1c29d2dd881f826f0b6c118", "parents": [ "188127e5692df218c560253095a1e96cdff7c6cd" ], "author": { "name": "Artur Raglis", "email": "artur.raglis@3mdeb.com", "time": "Wed Jun 05 19:24:52 2019 +0200" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Tue Sep 17 00:34:37 2019 +0000" }, "message": "libflashrom: add querying functions with meson integration\n\nWork based on lukasz.dmitrowski@gmail.com code\n\nChange-Id: I49041b8fa5700dabe59fef0d2337339d34cd6c6f\nSigned-off-by: Artur Raglis \u003cartur.raglis@3mdeb.com\u003e\nSigned-off-by: Lukasz Dmitrowski \u003clukasz.dmitrowski@gmail.com\u003e\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34363\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "188127e5692df218c560253095a1e96cdff7c6cd", "tree": "f4e17efd282d0c26c07ab5c1342c9120874e45b6", "parents": [ "ea0c093246fbaba9ab89348400ba4e99032aa4e0" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Tue Aug 06 16:10:34 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Wed Aug 21 06:18:16 2019 +0000" }, "message": "flashchips: upstream changes to GD25LQ128\n\nChange name of GD25LQ128 to GD25LQ128CD. This is an upstreaming of the\nchange from the chromium flashrom repo SHA\n6c957d745f5d3dcadd1035734a5cf1b804bd0f2f (Also visible at\nhttps://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/1181175)\n\nThe rationale from that change was:\n\n The GD25LQ128C part is EOL. It\u0027s replacement is GD25LQ128D, but\n both chips identify in the same manner. Add GD25LQ128D to the name\n of the part so that it doesn\u0027t confused people.\n\nMaking this name consistent will simplify further merging from the\nchromium fork.\n\nChange-Id: I57804f1a33170668e029a7b08ac050d9a3bd6dbb\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34735\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "ea0c093246fbaba9ab89348400ba4e99032aa4e0", "tree": "f5982cd4b2d3e207d064612083a286fcd5ad5cfc", "parents": [ "bde44a1989342859240c6993d1f782945bb4ce94" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Jul 04 17:34:16 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:33:25 2019 +0000" }, "message": "chipset_enable: Mark Intel CM236 and CM246 as DEP\n\nThe usual ME-lock limitations apply, so this is DEP instead of OK.\n\nTested on Kontron/bSL6 (SKL) and Siemens/Field PG M6 (CFL) and also\nregression tested on Apollo Lake. Flashrom works fine, and logs and\ndescriptor dumps look good. Also, register and descriptor output\nagree on the flash layout and permissions.\n\nChange-Id: I40db4773f127bec63e377e1d2ab402b47edf9a61\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34073\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "bde44a1989342859240c6993d1f782945bb4ce94", "tree": "8887b05e3561727001e0dd6ad14ee1d040ff9ee3", "parents": [ "2a5dfaf140eb8f22c923a026df855da0c5e9bf82" ], "author": { "name": "Matt DeVillier", "email": "matt.devillier@puri.sm", "time": "Thu Jul 04 17:52:40 2019 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:29:46 2019 +0000" }, "message": "chipset_enable: Add support for Cannon Lake U Premium\n\nAdd support for Cannon Lake U Premium (CFL-U/WHL-U).\nSame as discrete 300-series CNP PCH.\n\nTested on a WHL-U laptop w/unlocked IFD.\n\nChange-Id: I8a318d63cf408a3b2cec436a3fa6e26cf8552ead\nSigned-off-by: Matt DeVillier \u003cmatt.devillier@puri.sm\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34076\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "2a5dfaf140eb8f22c923a026df855da0c5e9bf82", "tree": "a1d231512e360758c35367d3b9b71e69f1ccbc57", "parents": [ "5ec84b3c096c9ace0bf3650206a0a9412e977c64" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Jul 04 16:01:51 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:29:37 2019 +0000" }, "message": "ichspi: Add support for discrete Cannon Lake PCHs\n\nOnly minor differences in the Firmware Descriptor, compared to their\npredecessors.\n\nWe extend our check on the `ICCRIBA` field in the descriptor to dis-\ntinguish it from older generation. Alas, the `freq_read` field was\nrepurposed, so we can\u0027t use it as sanity check any more.\n\nChange-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34072\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\n" }, { "commit": "5ec84b3c096c9ace0bf3650206a0a9412e977c64", "tree": "473c877a4c2901830e7a8005aa45b07d50323e9d", "parents": [ "045b97ebd97426b70706db7338a7fd76790b8781" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Mar 19 17:00:03 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:29:24 2019 +0000" }, "message": "chipset_enable: Add support for discrete Cannon Lake PCHs\n\nThe Cannon Lake \"300 Series\" PCHs [1,2] share the register layout of the\nSkylake \"100 Series\". Mark them as BAD until `ichspi.c` is adapted.\n\n[1] Intel(R) 300 Series and Intel(R) C240 Series\n Chipset Family Platform Controller Hub\n Datasheet - Volume 1 of 2\n Revison 4 (Dec 2018)\n Document Number 337347\n\n[2] Intel(R) 300 Series Chipset Families Platform Controller Hub\n Datasheet - Volume 2 of 2\n Revision 2? (Oct 2018)\n Document Number 337348\n\nChange-Id: If0b54799d5b93169ee660409bad57ae14677340c\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34071\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\nReviewed-by: Jeremy Soller \u003cjackpot51@gmail.com\u003e\n" }, { "commit": "045b97ebd97426b70706db7338a7fd76790b8781", "tree": "428bed111f3cc84a29c0059d74e337fe4cf7c7c9", "parents": [ "e8e7b0e6e8b7f665c0cce4e9a68c5b7573d39130" ], "author": { "name": "Jacob Creedon", "email": "jcreedon@google.com", "time": "Mon Jul 22 12:26:56 2019 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Aug 05 21:12:47 2019 +0000" }, "message": "flashchips: Add missing MT25Q erase commands\n\nThis adds additional 32KiB subsector erase commands 0x5c and 0x52 and an\nadditional bulk erase command of 0x60.\n\nSigned-off-by: Jacob Creedon \u003cjcreedon@google.com\u003e\nChange-Id: I5307c4b96cbd62203f5bad0c94737180fda621aa\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34490\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "e8e7b0e6e8b7f665c0cce4e9a68c5b7573d39130", "tree": "28ad082eab9008a0906bd409bf01377511202b27", "parents": [ "08e9d1d895edc2a86e8c89aeda6ffe03b503eb24" ], "author": { "name": "Jacob Creedon", "email": "jcreedon@google.com", "time": "Mon Jul 22 12:21:22 2019 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Aug 05 21:12:41 2019 +0000" }, "message": "flashchips: Fix N25Q512 bulk erase\n\nThe N25Q is a stacked device, so it requires 0xC4 to perform a die\nerase.\n\nSigned-off-by: Jacob Creedon \u003cjcreedon@google.com\u003e\nChange-Id: Ib408fbe5633abd8b657e3907142b997e88b33f84\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34489\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" } ], "next": "08e9d1d895edc2a86e8c89aeda6ffe03b503eb24" }