)]}' { "log": [ { "commit": "f9a30554803a670f9b95a7794be00f03929d6ecd", "tree": "46da1dafce0c76ab5730540540aaf4093463f551", "parents": [ "291764a70e6d8b212680e311bfb0825abf2b9a2f" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Sat May 23 20:30:30 2015 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Thu May 17 16:49:16 2018 +0000" }, "message": "linux_mtd: Import driver from ChromiumOS\n\nThis imports a series of patches from chromiumos for MTD support.\nThe patches are squashed to ease review and original Change-Ids have\nbeen removed to avoid confusing Gerrit.\n\nThere are a few changes to integrate the code:\n- Conflict resolution\n- Makefile changes\n- Remove file library usage from linux_mtd. We may revisit this and use\n it for other Linux interfaces later on.\n- Switch to using file stream functions for reads and writes.\n\nThis consolidated patch is\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\n\nThe first commit\u0027s message is:\nInitial MTD support\n\nThis adds MTD support to flashrom so that we can read, erase, and\nwrite content on a NOR flash chip via MTD.\n\nBUG\u003dchrome-os-partner:40208\nBRANCH\u003dnone\nTEST\u003dread, write, and erase works on Oak\n\nSigned-off-by: David Hendricks \u003cdhendrix@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/272983\nReviewed-by: Shawn N \u003cshawnn@chromium.org\u003e\n\nThis is the 2nd commit message:\n\nlinux_mtd: Fix compilation errors\n\nThis fixes compilation errors from the initial import patch.\n\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\n\nThis is the 3rd commit message:\n\nlinux_mtd: Suppress message if NOR device not found\n\nThis just suppresses a message that might cause confusion for\nunsuspecting users.\n\nBUG\u003dnone\nBRANCH\u003dnone\nTEST\u003dran on veyron_mickey, \"NOR type device not found\" message\nno longer appears under normal circumstances.\nSigned-off-by: David Hendricks \u003cdhendrix@chromium.org\u003e\n\nReviewed-on: https://chromium-review.googlesource.com/302145\nCommit-Ready: David Hendricks \u003cdhendrix@chromium.org\u003e\nTested-by: David Hendricks \u003cdhendrix@chromium.org\u003e\nReviewed-by: Shawn N \u003cshawnn@chromium.org\u003e\n\nThis is the 4th commit message:\n\nlinux_mtd: Support for NO_ERASE type devices\n\nSome mtd devices have the MTD_NO_ERASE flag set. This means\nthese devices don\u0027t require an erase to write and might not have\nimplemented an erase function. We should be conservative and skip\nerasing altogether, falling back to performing writes over the whole\nflash.\n\nBUG\u003db:35104688\nTESTED\u003dZaius flash is now written correctly for the 0xff regions.\n\nSigned-off-by: William A. Kennington III \u003cwak@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/472128\nCommit-Ready: William Kennington \u003cwak@google.com\u003e\nTested-by: William Kennington \u003cwak@google.com\u003e\nReviewed-by: Brian Norris \u003cbriannorris@chromium.org\u003e\n\nThis is the 5th commit message:\n\nlinux_mtd: do reads in eraseblock-sized chunks\n\nIt\u0027s probably not the best idea to try to do an 8MB read in one syscall.\nTheoretically, this should work; but MTD just relies on the SPI driver\nto deliver the whole read in one transfer, and many SPI drivers haven\u0027t\nbeen tested well with large transfer sizes.\n\nI\u0027d consider this a workaround, but it\u0027s still good to have IMO.\n\nBUG\u003dchrome-os-partner:53215\nTEST\u003dboot kevin; `flashrom --read ...`\nTEST\u003dcheck for performance regression on oak\nBRANCH\u003dnone\n\nSigned-off-by: Brian Norris \u003cbriannorris@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/344006\nReviewed-by: David Hendricks \u003cdhendrix@chromium.org\u003e\n\nThis is the 6th commit message:\n\nlinux_mtd: make read/write loop chunks consistent, and documented\n\nTheoretically, there should be no maximum size for the read() and\nwrite() syscalls on an MTD (well, except for the size of the entire\ndevice). But practical concerns (i.e., bugs) have meant we don\u0027t quite\ndo this.\n\nFor reads:\nBug https://b/35573113 shows that some SPI-based MTD drivers don\u0027t yet\nhandle very large transactions. So we artificially limit this to\nblock-sized chunks.\n\nFor writes:\nIt\u0027s not clear there is a hard limit. Some drivers will already split\nlarge writes into smaller chunks automatically. Others don\u0027t do any\nsplitting. At any rate, using *small* chunks can actually be a problem\nfor some devices (b:35104688), as they get worse performance (doing an\ninternal read/modify/write). This could be fixed in other ways by\nadvertizing their true \"write chunk size\" to user space somehow, but\nthis isn\u0027t so easy.\n\nAs a simpler fix, we can just increase the loop increment to match the\nread loop. Per David, the original implementation (looping over page\nchunks) was just being paranoid.\n\nSo this patch:\n * clarifies comments in linux_mtd_read(), to note that the chunking is\n somewhat of a hack that ideally can be fixed (with bug reference)\n * simplifies the linux_mtd_write() looping to match the structure in\n linux_mtd_read(), including dropping several unnecessary seeks, and\n correcting the error messages (they referred to \"reads\" and had the\n wrong parameters)\n * change linux_mtd_write() to align its chunks to eraseblocks, not page\n sizes\n\nNote that the \"-\u003epage_size\" parameter is still somewhat ill-defined, and\nonly set by the upper layers for \"opaque\" flash. And it\u0027s not actually\nused in this driver now. If we could figure out what we really want to\nuse it for, then we could try to set it appropriately.\n\nBRANCH\u003dnone\nBUG\u003db:35104688\nTEST\u003dvarious flashrom tests on Kevin\nTEST\u003dReading and writing to flash works on our zaius machines over mtd\n\nChange-Id: I3d6bb282863a5cf69909e28a1fc752b35f1b9599\nSigned-off-by: Brian Norris \u003cbriannorris@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/505409\nReviewed-by: David Hendricks \u003cdhendrix@chromium.org\u003e\nReviewed-by: Martin Roth \u003cmartinroth@chromium.org\u003e\nReviewed-by: William Kennington \u003cwak@google.com\u003e\nReviewed-on: https://review.coreboot.org/25706\nTested-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Philipp Deppenwiese \u003czaolin.daisuki@gmail.com\u003e\n" }, { "commit": "291764a70e6d8b212680e311bfb0825abf2b9a2f", "tree": "8c6d1c5156ba4e73169d4b541704a4f7c6326566", "parents": [ "2099c648b929cd36c500202089ef4b7a8c14680f" ], "author": { "name": "Alex James", "email": "theracermaster@gmail.com", "time": "Sat Apr 14 22:59:57 2018 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri May 11 16:32:42 2018 +0000" }, "message": "ch341a_spi: Avoid deprecated libusb functions\n\nlibusb 1.0.22 marked libusb_set_debug as deprecated. For such versions\nof libusb, use libusb_set_option instead.\n\nChange-Id: Ib71ebe812316eaf49136979a942a946ef9e4d487\nSigned-off-by: Alex James \u003ctheracermaster@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/25681\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "2099c648b929cd36c500202089ef4b7a8c14680f", "tree": "d934dc4be97cd3e0e97b948f66463142c598b8cd", "parents": [ "256835787229205b6522a3c12322b22303bb4152" ], "author": { "name": "Maxime Vincent", "email": "maxime.vince@gmail.com", "time": "Fri Nov 24 13:04:08 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri May 11 16:15:19 2018 +0000" }, "message": "buspirate_spi: Tristate IOs when using using pullup\u003don\n\nAvoid putting 3.3V on IO pins when pullup\u003don to avoid damage to 1.8V\nchips.\n\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nChange-Id: I9ac4c6b7a0079bb1022f2d70030a6eb29996108f\nReviewed-on: https://review.coreboot.org/23864\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "256835787229205b6522a3c12322b22303bb4152", "tree": "2748ffea8f72a8d7000fc8b928df9756c689aca1", "parents": [ "25584de9d0108a5dde41e0296fdf0a7854390a81" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Mar 30 13:50:13 2018 +0200" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun May 06 21:00:41 2018 +0000" }, "message": "flashchips: Add Winbond 25Q40EW and rename 25Q40.W\n\nSame story as for 25Q80BW/EW, 25Q40EW has a new ID and the only known\nchip with the old ID is the BW variant.\n\nChange-Id: Ib610b0d6f3a5561b2ac3505ef15bdee8b0edae25\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/25462\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "25584de9d0108a5dde41e0296fdf0a7854390a81", "tree": "d505c037e5a2e729e1eb64882c60fd69fcb1b40e", "parents": [ "1b365931ea8a9d5766972c17c7cf91b9de595fb1" ], "author": { "name": "Wei Hu", "email": "wei@aristanetworks.com", "time": "Mon Apr 30 14:02:08 2018 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun May 06 20:56:02 2018 +0000" }, "message": "flashchips: Add SST26VF016B(A), SST26VF032B(A), SST26VF064B(A)\n\nThis patch seems to have originally been from\nhttps://patchwork.coreboot.org/patch/4126/ . The most recent version\nseems to be in OpenEmbedded (commit 503a572) which added support for\n16Mbit and 32Mbit variants.\n\nThe OpenEmbedded patch also makes changes to linux_spi.c to add some\ndebug prints which are omitted in this version.\n\nFrom the original commit message:\nDifferences between SST26 and SST25:\n1. The WREN instruction must be executed prior to WRSR [Section 5.31].\n There is no EWSR.\n2. Block protection bits are no longer in the status register. There\n is a dedicated 144-bit register [Table 5-6]. The device is\n write-protected by default. A Global Block-Protection Unlock\n command unlocks the entire memory [Section 4.1].\n\nChange-Id: Ib019bed8ce955049703eb3376c32a83ef607c219\nSigned-off-by: Wei Hu \u003cwei@aristanetworks.com\u003e\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@student.tuwien.ac.at\u003e\nReviewed-on: https://review.coreboot.org/25962\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "1b365931ea8a9d5766972c17c7cf91b9de595fb1", "tree": "36230b9c41038bc2e97c090907bb9c8472d9b71a", "parents": [ "e083880279119677e443fc16b4694f8c81bf2c40" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Wed Apr 25 16:03:51 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Apr 25 14:36:38 2018 +0000" }, "message": "udelay.c: Remove trailing whitespace\n\nChange-Id: Ibd77c2a99bd839c01ae7ff058365eda7e30db261\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/25824\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "e083880279119677e443fc16b4694f8c81bf2c40", "tree": "03413b996779bc4c86ec41590f3e7bcdd97d0ef5", "parents": [ "124ef38f7afc61ad7c713c22aad7c5c7f79bdb9b" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Mon Apr 02 11:14:02 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 24 20:21:41 2018 +0000" }, "message": "Remove address from GPLv2 headers\n\nChange-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/25381\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "124ef38f7afc61ad7c713c22aad7c5c7f79bdb9b", "tree": "980f498681fcc053ec1e591e22bb16afbef0a191", "parents": [ "3f7e3419887c6d37330387f8e32c86ba47bdf70c" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Tue Mar 27 12:15:09 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 24 20:18:58 2018 +0000" }, "message": "Fix whitespace errors\n\nChange-Id: Ic2d3bb9d8581a0471a8568a130f893b34dddf113\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/25380\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "3f7e3419887c6d37330387f8e32c86ba47bdf70c", "tree": "e51bbf17118c5ae3a4c1894892643ef09a6c8dbd", "parents": [ "f73f8a732f8fd37a6a7dfef4acb7f7c416832ab2" ], "author": { "name": "Luc Verhaegen", "email": "libv@skynet.be", "time": "Wed Mar 28 12:31:22 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Mar 29 11:01:20 2018 +0000" }, "message": "board_enable: add AOpen i965GMt-LA\n\nChange-Id: I8899bbe06707fe76256539f90f5b670301228d52\nSigned-off-by: Luc Verhaegen \u003clibv@skynet.be\u003e\nReviewed-on: https://review.coreboot.org/25396\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f73f8a732f8fd37a6a7dfef4acb7f7c416832ab2", "tree": "4d65a6d09dd2a30bb24ba82aad1747c9c0a79e9b", "parents": [ "c699f5cde113377099d038234c1e46e7b928336f" ], "author": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Wed Feb 21 07:34:34 2018 -0800" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Wed Mar 28 22:07:50 2018 +0000" }, "message": "dediprog: implement command spec for firmware \u003e\u003d 7.2.30\n\nThis adds support for the latest command spec for Dediprog SF100/SF600\nprogrammers. Since we now have more than two protocols to\ndeal with the is_new_prot() function is replaced with protocol() which\nreturns an enum specifying which protocol is supported.\n\nThe latest spec (FW \u003e\u003d 7.2.30) updates read and write packets. It\u0027s\nbeen tested on an SF600 using firmware 7.2.21 and SF600Plus using FW\n7.2.30.\n\nThe latest command protocol has a few small but important changes:\n- Read packets have two more bytes:\n 11: B4Addr: address len (3 or 4)\n 12: Dummy cycle /2\n\n- Write packets have four more bytes:\n 11, 12: 16 HSBs of page size\n 13, 14: 16 LSBs of page size\n\n(The spec seems to be mistaken, though, as 11 and 12 are actually\n LSBs instead of HSBs)\n\nChange-Id: I1a53c143948ec40d40433621891a2871d8815f2f\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/23836\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "c699f5cde113377099d038234c1e46e7b928336f", "tree": "de4124ad4da2436bdde3f527b17b4239c2defa79", "parents": [ "f5775448448d62c334a24618cd19692bb4a5f8a6" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Sun Mar 11 17:29:49 2018 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Wed Mar 28 19:37:12 2018 +0000" }, "message": "flashchips: W25Q80.W --\u003e W25Q80BW\n\nThe W25Q80BW appears to have been succeeded by the W25Q80EW which has a\ndifferent manufacturer ID but is otherwise similar. Consequently, W25Q80.W\nno longer matches all chips in this family.\n\nThis patch makes the original entry specific to W25Q80BW.\n\nChange-Id: I2980272c2691eb62a68056a7a4c308e9b4810347\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/25100\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f5775448448d62c334a24618cd19692bb4a5f8a6", "tree": "baf27821d13eba40852c7547a46fa9fec0108368", "parents": [ "a9a03cc6ba71825bfae0d64e1888f33c77345bc3" ], "author": { "name": "Stanislav Sedov", "email": "ssedov@fb.com", "time": "Wed Mar 07 14:16:51 2018 -0800" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Wed Mar 28 19:34:59 2018 +0000" }, "message": "Add support for Atmel/Adesto AT25SF161 and Winbond W25Q80EW\n\nChange-Id: Ia9e8f7f23896f7002401c6b1e616c0dc102198e2\nSigned-off-by: Stanislav Sedov \u003cssedov@fb.com\u003e\nReviewed-on: https://review.coreboot.org/25099\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "a9a03cc6ba71825bfae0d64e1888f33c77345bc3", "tree": "ac9eebdd5036f969f0eadb6d57c62f0bc964d6fc", "parents": [ "b6e3d257f97fd4e3998e0743968d17010047b4c1" ], "author": { "name": "Khem Raj", "email": "raj.khem@gmail.com", "time": "Sat Mar 17 23:08:29 2018 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Mar 23 14:33:38 2018 +0000" }, "message": "platform: Add riscv to known platforms\n\nChange-Id: I724a99e2493fcbf71c2fc2d9f6a1ad607c737087\nSigned-off-by: Khem Raj \u003craj.khem@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/25260\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "b6e3d257f97fd4e3998e0743968d17010047b4c1", "tree": "6932c164c28e36b00788b35db201dbe40660e058", "parents": [ "22418428ed28d803bfca151623bbf017d1ba6bfc" ], "author": { "name": "Antonio Ospite", "email": "ao2@ao2.it", "time": "Sat Mar 03 18:40:24 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Mar 23 14:31:49 2018 +0000" }, "message": "Fix compilation with older MinGW versions\n\nThe __MINGW_PRINTF_FORMAT constant has been defined back in 2012\nhttps://sourceforge.net/p/mingw-w64/mingw-w64/ci/77bc5d6103b5fb9f59fbddab1583e69549913312/\n\nHowever older toolchains are still around and some user reported the\nfollowing compilation failure:\n\n flash.h:336:1: error: \u0027__MINGW_PRINTF_FORMAT\u0027 is an unrecognized format function  type [-Werror\u003dformat\u003d]\n  __attribute__((format(__MINGW_PRINTF_FORMAT, 2, 3)));\n\nFix this by defining the constant when it isn\u0027t already; the change does\nnot affect other compilers because it\u0027s guarded by \"#ifdef __MINGW32__\".\n\nSetting __MINGW_PRINTF_FORMAT to gnu_printf is exactly what newer MinGW\nversions do when __USE_MINGW_ANSI_STDIO is defined, which it is in\nflashrom Makefile.\n\nChange-Id: I48de3e4303b9a389c515a8ce230282d9210576fd\nTested-by: Miklos Marton \u003cmartonmiklosqdev@gmail.com\u003e\nSigned-off-by: Antonio Ospite \u003cao2@ao2.it\u003e\nReviewed-on: https://review.coreboot.org/25130\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "22418428ed28d803bfca151623bbf017d1ba6bfc", "tree": "6fbf0e0bd0ce3dd315c849309f4f62139a933756", "parents": [ "a3ab6c6c3ae7ec62944aad580bbfc1701b3a8581" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Mar 08 16:14:15 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Mar 20 10:01:20 2018 +0000" }, "message": "linux_spi: Reduce maximum read chunksize\n\nIt turned out that older kernels use a single buffer of `bufsiz` bytes\nfor combined input and output data. So we have to account for the read\ncommand + max 4 address bytes.\n\nChange-Id: Ide50db38af1004fde09a70b15938e77f5e1285ac\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nTested-by: Julian von Mendel \u003cgit@jinvent.de\u003e\nReviewed-on: https://review.coreboot.org/25149\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Julian von Mendel \u003cgit@jinvent.de\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "a3ab6c6c3ae7ec62944aad580bbfc1701b3a8581", "tree": "2c40d90017f1a810983692cf6d969d90dbcd6e64", "parents": [ "4f444794de11bd638ebe8daef5c8364c20a8e8ec" ], "author": { "name": "jvm", "email": "git@jinvent.de", "time": "Thu Mar 08 15:43:20 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Mar 14 11:04:04 2018 +0000" }, "message": "Add support for Atmel / Adesto AT25SF041 SPI flash chip\n\nprobe/erase/read/write/verify hardware-tests were done.\n\nChange-Id: I0be930ff2258300508398e12fbe5abe10400fea2\nSigned-off-by: Julian von Mendel \u003cgit@jinvent.de\u003e\nSigned-off-by: jvm \u003cgit@jinvent.de\u003e\nReviewed-on: https://review.coreboot.org/25047\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "4f444794de11bd638ebe8daef5c8364c20a8e8ec", "tree": "14333facfdb159334f5297dde7b9357b2a0c2bb5", "parents": [ "1d50abc4cc1892e2b81999396de795f0c63b57ca" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@student.tuwien.ac.at", "time": "Mon Jun 27 11:44:03 2011 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Mar 08 09:17:52 2018 +0000" }, "message": "dmi: Don\u0027t print dmidecode shell error\n\nDon\u0027t print the error \"sh: dmidecode: not found\" if dmidecode is not there.\nUses stderr redirection to /dev/null (or NUL on Windows).\n\nChange-Id: I3ded8e1bad14b5e809185a79c4e3a17329b1ecb9\nSigned-off-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@student.tuwien.ac.at\u003e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/23802\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\n" }, { "commit": "1d50abc4cc1892e2b81999396de795f0c63b57ca", "tree": "ce8927ee3e66b6959db11fb83d4c80cc4c5dafb4", "parents": [ "a72d5a98286272094dda06f5c69b48910f6a7451" ], "author": { "name": "Arthur Heymans", "email": "arthur@aheymans.xyz", "time": "Sat Jun 03 21:29:55 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Mar 07 12:53:00 2018 +0000" }, "message": "Whitelist Lenovo Thinkpad X220\n\nCoreboot uses the subvendor VID/DID of the Thinkpad X220-Tablet for\nall X220 variants. Don\u0027t specify a dmidecode string so that it can be\nused with coreboot on all X220 variants and on X220-Tablet with vendor\nfirmare.\n\nChange-Id: Idd667da8209a664469c1a909a549d2b625714a78\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-on: https://review.coreboot.org/23225\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "a72d5a98286272094dda06f5c69b48910f6a7451", "tree": "f75e3e21a0309e493158027b6b762b93e8968b1a", "parents": [ "4164c54196deca789b80e6a0b1be5f70e142b729" ], "author": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Feb 11 17:58:44 2018 -0800" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Thu Feb 22 01:37:55 2018 +0000" }, "message": "flashchips: Add ZD25D20\n\nThis adds another Zetta Device chip, the ZD25D20.\n\nChange-Id: Idf805252647be44e28296a161d2e6160710bcc71\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/23702\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "4164c54196deca789b80e6a0b1be5f70e142b729", "tree": "1ac54bf4faea74f55f26f82bb7b757d9522cacfb", "parents": [ "cbb46e261d5f2837df21e0853c7cd4170d226b40" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 22 02:09:18 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Feb 21 21:20:50 2018 +0000" }, "message": "git-hooks: Fix install script for various git versions\n\nThere are older versions of git-rev-parse that don\u0027t understand the\n`--git-path` switch. Also, when the install script was written, git-\nrev-parse had a bug when it wasn\u0027t run from the root directory. They\nfixed the behaviour by now. To simplify things and not have to account\nfor that too, we just bail out when the script is run from a sub-\ndirectory.\n\nChange-Id: I7ee8d4d54db48f7207fe8abf895c7fbba7685ad2\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22971\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "cbb46e261d5f2837df21e0853c7cd4170d226b40", "tree": "04e07a8adc469d232a07c56fe1d43d867270b551", "parents": [ "8c7e78b9deaa550339940a2efd7bcaef03267751" ], "author": { "name": "nybash", "email": "ny.bash@gmail.com", "time": "Sun Feb 11 17:53:49 2018 -0800" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Wed Feb 21 17:40:03 2018 +0000" }, "message": "flashchips: Add Zettadevice ZD25D40\n\nThis introduces the Zettadevice manufacturer ID and adds support for the\nZD25D40 chip.\n\nBased on PR20 from Github.\nChange-Id: I0400b059ddacdf166d1b77f619becec3a250cece\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/23701\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "8c7e78b9deaa550339940a2efd7bcaef03267751", "tree": "0cc522fdda05d1a5b197c5a05e3e6ee9b0a5d395", "parents": [ "c9ee0ed8a62d5b165a22d536753e960e0158460c" ], "author": { "name": "Leah Rowe", "email": "leah@libreboot.org", "time": "Fri Jan 26 00:57:10 2018 +0000" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Tue Feb 20 01:32:16 2018 +0000" }, "message": "board_enable: Whitelist several ThinkPad laptops\n\nNewly whitelisted laptops include:\n\n* ThinkPad R400\n* ThinkPad T500\n* ThinkPad W500\n* Libiquity Taurinus X200\n\nChange-Id: I772f8e109c56a5fd40f6b1aff0f592b915669c17\nSigned-off-by: Leah Rowe \u003cleah@libreboot.org\u003e\nReviewed-on: https://review.coreboot.org/23781\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "c9ee0ed8a62d5b165a22d536753e960e0158460c", "tree": "eb795574c05b61a4a3f82dbd916c26cc27c256e5", "parents": [ "f701f343117270b4373320eb25ae259b8e513b7d" ], "author": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Feb 11 17:40:53 2018 -0800" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Tue Feb 20 01:09:29 2018 +0000" }, "message": "flashchips: Add Winbond W25P80/16/32 support\n\nThis adds support for W25P80/16/32 chips. Most notably these chips only\nhave two erase commands - one for 64KiB \"sectors\" and one for chip\nerase.\n\nChange-Id: Ie09ba8e28fee35c42e17ca05219dc673413de93b\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/23700\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "f701f343117270b4373320eb25ae259b8e513b7d", "tree": "2749940aec9f2b1dc0ad53069079b78f225d76cf", "parents": [ "3a826043dbd389b4be2f5783c1b984ba297b8179" ], "author": { "name": "Paul Kocialkowski", "email": "contact@paulk.fr", "time": "Mon Jan 15 01:10:36 2018 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 11 16:54:14 2018 +0000" }, "message": "Add support for reading the current flash contents from a file\n\nWhen developing software that has to be flashed to a flash chip to be\nexecuted, it often takes a long time to read the current flash contents\n(for flashrom to know what pages to erase and reprogram) each time\nwhen writing the new image. However, when the flash was just reprogrammed,\nits current state is known to be the previous image that was flashed\n(assuming it was verified).\n\nThus, it makes sense to provide that image as a file for the flash contents\ninstead of wasting valuable time read the whole flash each time.\n\nChange-Id: Idf153b6955f37779ae9bfb228a434ed10c304947\nSigned-off-by: Mike Banon \u003cmikebdp2@gmail.com\u003e\nSigned-off-by: Paul Kocialkowski \u003ccontact@paulk.fr\u003e\nReviewed-on: https://review.coreboot.org/23263\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3a826043dbd389b4be2f5783c1b984ba297b8179", "tree": "c52c86c6821aa657abdd4ac24de7db15559bc57b", "parents": [ "a590f4840b41430a8d2a457eac04e7050584ef48" ], "author": { "name": "Mike Banon", "email": "mikebdp2@gmail.com", "time": "Mon Jan 15 01:09:16 2018 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 11 16:53:47 2018 +0000" }, "message": "edi: Print debug info like others while probing for ENE chips\n\nInstead of just \"Probing for ENE KB9012 (EDI), 128 kB:\", lets print\nsome debug info - like it is currently being printed for other chips:\n\nProbing for ENE KB9012 (EDI), 128 kB: edi_chip_probe: hwversion 0xc3, ediid 0x04\nFound ENE flash chip \"KB9012 (EDI)\" (128 kB, SPI) on ch341a_spi.\n\nChange-Id: Id8e62bc9f6785b4bf0be0aaf0f74c8120d77c0d4\nSigned-off-by: Mike Banon \u003cmikebdp2@gmail.com\u003e\nSigned-off-by: Paul Kocialkowski \u003ccontact@paulk.fr\u003e\nReviewed-on: https://review.coreboot.org/23261\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a590f4840b41430a8d2a457eac04e7050584ef48", "tree": "57ae686e0692e8b4ae28e0e3fdcb453c735a8896", "parents": [ "80ae14e5105bb938679193906d1ee43b7a51c094" ], "author": { "name": "Paul Kocialkowski", "email": "contact@paulk.fr", "time": "Mon Jan 15 01:08:39 2018 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 11 16:53:42 2018 +0000" }, "message": "edi: Add dummy read to ensure proper detection of ENE chips\n\nENE chips enable EDI by detecting a clock frequency between 1 MHz and 8 MHz.\nIn many cases, the chip won\u0027t be able to both detect the clock signal and\nserve the associated request at the same time.\n\nThus, a dummy read has to be added to ensure that EDI is enabled and\noperational starting from the next request.\n\nChange-Id: I69ee71674649cd8ba4fc635f889cb39a1cd204b9\nSigned-off-by: Mike Banon \u003cmikebdp2@gmail.com\u003e\nSigned-off-by: Paul Kocialkowski \u003ccontact@paulk.fr\u003e\nReviewed-on: https://review.coreboot.org/23260\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "80ae14e5105bb938679193906d1ee43b7a51c094", "tree": "629130fad3e6b0b731429bb90dc8e285a91ea8ab", "parents": [ "995f755ff569cbf6ed8d4eec5920b41628aa8ac9" ], "author": { "name": "Paul Kocialkowski", "email": "contact@paulk.fr", "time": "Mon Jan 15 01:07:46 2018 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 11 16:53:34 2018 +0000" }, "message": "Add support for the ENE Embedded Debug Interface EDI and KB9012 EC\n\nThe ENE Embedded Debug Interface (EDI) is a SPI-based interface for\naccessing the memory of ENE embedded controllers.\n\nThe ENE KB9012 EC is an embedded controller found on various laptops\nsuch as the Lenovo G505s. It features a 8051 microcontroller and\nhas 128 KiB of internal storage for program data.\n\nEDI can be accessed on the KB9012 through pins 59-62 (CS-CLK-MOSI-MISO)\nwhen flash direct access is not in use. Some firmwares disable EDI at runtime\nso it might be necessary to ground pin 42 to reset the 8051 microcontroller\nbefore accessing the KB9012 via EDI.\n\nThe example of flashing KB9012 at Lenovo G505S laptop could be found here:\nhttp://dangerousprototypes.com/docs/Flashing_KB9012_with_Bus_Pirate\n\nChange-Id: Ib8b2eb2feeef5c337d725d15ebf994a299897854\nSigned-off-by: Mike Banon \u003cmikebdp2@gmail.com\u003e\nSigned-off-by: Paul Kocialkowski \u003ccontact@paulk.fr\u003e\nReviewed-on: https://review.coreboot.org/23259\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "995f755ff569cbf6ed8d4eec5920b41628aa8ac9", "tree": "8bf525250f29a35eac59e1140da8c039790842cd", "parents": [ "31b5e3bfe6c01180d9a079813ecd199b4808315d" ], "author": { "name": "Paul Kocialkowski", "email": "contact@paulk.fr", "time": "Mon Jan 15 01:06:09 2018 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 11 16:52:48 2018 +0000" }, "message": "Add support for selecting the erased bit value with a flag\n\nMost flash chips are erased to ones and programmed to zeros. However, some\nother chips, such as the ENE KB9012 internal flash, work the opposite way.\n\nChange-Id: Ia7b0de8568e31f9bf263ba0ad6b051e837477b6b\nSigned-off-by: Mike Banon \u003cmikebdp2@gmail.com\u003e\nSigned-off-by: Paul Kocialkowski \u003ccontact@paulk.fr\u003e\nReviewed-on: https://review.coreboot.org/23258\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "31b5e3bfe6c01180d9a079813ecd199b4808315d", "tree": "3acefe04a94524cf9f3fdd47d4136f7c5b137b60", "parents": [ "305a2b3ed36ce87663aea177a806c6f435a4ceec" ], "author": { "name": "Mike Banon", "email": "mikebdp2@gmail.com", "time": "Mon Jan 15 01:10:00 2018 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 11 16:52:30 2018 +0000" }, "message": "Add a SPI command class to `struct flashchip`\n\nBy default, we want to probe for SPI25 chips only. Other SPI use cases,\nlike the ENE/EDI protocol, might use commands that can confuse these\ncommon chips.\n\nNow, flashrom will probe for a chip only if one of these conditions is\ntrue:\n1) no chip has been specified AND the chip uses the SPI25 commands\n2) this chip has been specified by -c | --chip \u003cchipname\u003e\n\nThe CLI can later be extended to probe for a specific class of chips.\n\nChange-Id: I89a53ccaef2791a2ac32904d7ab813da7478a6f0\nSigned-off-by: Mike Banon \u003cmikebdp2@gmail.com\u003e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/23262\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Kocialkowski \u003ccontact@paulk.fr\u003e\n" }, { "commit": "305a2b3ed36ce87663aea177a806c6f435a4ceec", "tree": "a9dcc88821f3f7f8174c5ed1ba851f3522240b62", "parents": [ "2b5adfb1b656dd6a6efbf45a7a411c87840c5394" ], "author": { "name": "Lubomir Rintel", "email": "lkundrak@v3.sk", "time": "Mon Jan 08 05:31:55 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 26 15:27:42 2018 +0000" }, "message": "chipset_enable: Mark VX855 as tested\n\nI can confirm a successful reading and writing of SST49LF080A (LPC) on a\nWyse Cx0 Thin Client (Phoenix BIOS 1.0G).\n\nChange-Id: I8f48b49ccb760f69d676ec6cbb233e532b12fbe8\nSigned-off-by: Lubomir Rintel \u003clkundrak@v3.sk\u003e\nReviewed-on: https://review.coreboot.org/23158\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "2b5adfb1b656dd6a6efbf45a7a411c87840c5394", "tree": "cfc4bf09d45d4ad59b645c0cadaec9507ba5c152", "parents": [ "25fde40f8594b1c13ba7a4c3a605b96b200a4e11" ], "author": { "name": "Shawn Anastasio", "email": "shawnanastasio@yahoo.com", "time": "Sun Dec 31 00:17:15 2017 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 26 15:23:10 2018 +0000" }, "message": "buspirate_spi: Add support for variable serial speeds\n\nThis patch sets the default baud rate for communication between\nthe host device and the Bus Pirate for hardware versions 3.0\nand greater to 2M baud.\n\nIt also introduces the ability to manually set the baud rate via\nthe added \u0027serialspeed\u0027 programmer parameter.\n\nThis is done in two parts. Firstly, the requested serial speed is looked up\nin a table to determine the appropriate clock divisor and the divisor is sent\nto the bus pirate. Then, the system\u0027s baud rate for the selected serial port\nis set using serial.c\u0027s \u0027serialport_config\u0027. This function\u0027s prototype had to\nbe added to programmer.h.\n\nIn testing, using the 2M baud rate was able to significantly decrease\nflash times (down from 20+ minutes to less than 2 minutes for an 8MB flash).\n\nChange-Id: I3706f17a94fdf056063f2ad4a5f0a219665cdcbf\nSigned-off-by: Shawn Anastasio \u003cshawnanastasio@yahoo.com\u003e\nReviewed-on: https://review.coreboot.org/23057\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "25fde40f8594b1c13ba7a4c3a605b96b200a4e11", "tree": "8e19343934bcd9be2503441b556ccf4e0871fed2", "parents": [ "73c882086fe7d6fac9859e2faa93ec56cc96b9bd" ], "author": { "name": "Rudolf Marek", "email": "r.marek@assembler.cz", "time": "Fri Dec 29 16:30:49 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jan 06 22:38:58 2018 +0000" }, "message": "Fix the documentation and DOS port\n\nUpdate the DOS cross-compile documentation,\nand workaround issue with valloc() with the\nlatest DJGPP.\n\nChange-Id: I909c5635aec5076440d2fde73d943f8ad10b8051\nSigned-off-by: Rudolf Marek \u003cr.marek@assembler.cz\u003e\nReviewed-on: https://review.coreboot.org/23039\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "73c882086fe7d6fac9859e2faa93ec56cc96b9bd", "tree": "b6f32ecc6126de577c687718c9810f5c1bfbd132", "parents": [ "d0803c8407c459e972cb9912a4a3cbfeebb93d9e" ], "author": { "name": "Lubomir Rintel", "email": "lkundrak@v3.sk", "time": "Thu Dec 28 20:19:21 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jan 02 20:15:56 2018 +0000" }, "message": "chipset_enable: Mark VX900 as tested\n\nI can confirm a successful reading and writing of MX25L8005 (SPI) on a HP t5550\nThin Client (AMI BIOS 786R9 v1.04).\n\nChange-Id: I190253b0c1920747b710ed7155e78191cce139eb\nSigned-off-by: Lubomir Rintel \u003clkundrak@v3.sk\u003e\nReviewed-on: https://review.coreboot.org/23030\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d0803c8407c459e972cb9912a4a3cbfeebb93d9e", "tree": "7c361a17c153b09bf9da9ea685e29b4648118218", "parents": [ "aac81424ebb8234b54cbab8fe47350b562b84fae" ], "author": { "name": "Lubomir Rintel", "email": "lkundrak@v3.sk", "time": "Mon Oct 30 07:57:53 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jan 02 20:15:45 2018 +0000" }, "message": "vt_vx: check whether the chipset\u0027s MMIO range is configured\n\nAvoid attempting to read the SPI bases from the location 0x00000000, all\nzeroes mean that the chipset\u0027s MMIO area is not enabled.\n\nChange-Id: I5d3a1ba695153e854e0979ae634f8ed97e6b6293\nSigned-off-by: Lubomir Rintel \u003clkundrak@v3.sk\u003e\nReviewed-on: https://review.coreboot.org/23029\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "aac81424ebb8234b54cbab8fe47350b562b84fae", "tree": "2806be52075a5a3a46c5e7be2ccdb6d69b6e1a0f", "parents": [ "fe34d2af28bd81aaa1e23ba38febaa98ec4bb90c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 10 22:54:13 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jan 02 20:15:35 2018 +0000" }, "message": "flashchips: Revise all 4BA chips\n\nAdvertise all 4BA features that are currently supported by flashrom,\nplus add a new feature flag for the 4BA fast-read instruction. Also,\nlist all supported 3BA and 4BA erase-block functions.\n\nAs this adds a lot of new code paths that could be taken for these\nchips, mark them all as untested again.\n\nChange-Id: I0598496ee7058e3b170684d366f58e4014e0e871\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22423\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "fe34d2af28bd81aaa1e23ba38febaa98ec4bb90c", "tree": "53bda4d3445a94505455ffb12a96da602ba97af6", "parents": [ "1cf407b4f8d56035816efaf936a40553441eca46" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 10 21:10:20 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jan 02 20:15:30 2018 +0000" }, "message": "spi25: Revise decision when to enter/exit 4BA mode\n\nInstead of arbitrarily deciding whether to enter 4BA mode in the flash\nchip\u0027s declaration, advertise that entering 4BA mode is supported and\nonly enter it if the SPI master supports 4-byte addresses. If not, exit\n4BA mode (the chip might be in 4BA mode after reset). If we can\u0027t assure\nthe state of 4BA mode, we bail out to simplify the code (we\u0027d have to\nensure that we don\u0027t run any instructions that can usually be switched\nto 4BA mode otherwise).\n\nTwo new feature flags are introduced:\n\n* FEATURE_4BA_ENTER:\n Can enter/exit 4BA mode with instructions 0xb7/0xe9 w/o WREN.\n* FEATURE_4BA_ENTER_WREN\n Can enter/exit 4BA mode with instructions 0xb7/0xe9 after WREN.\n\nFEATURE_4BA_SUPPORT is dropped, it\u0027s completely implicit now.\n\nAlso, draw the with/without WREN distinction into the enter/exit\nfunctions to reduce code redundancy.\n\nChange-Id: I877fe817f801fc54bd0ee2ce4e3ead324cbb3673\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22422\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "1cf407b4f8d56035816efaf936a40553441eca46", "tree": "c8e41e1172aaeb567af161a9763521c53073bdc4", "parents": [ "ed098d62d66d91cf7330a37f9b83e303eb7f56d8" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 10 20:18:23 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jan 02 20:14:34 2018 +0000" }, "message": "spi_master: Introduce SPI_MASTER_4BA feature flag\n\nAdd a feature flag SPI_MASTER_4BA to `struct spi_master` that advertises\nprogrammer-side support for 4-byte addresses in generic commands (and\nread/write commands if the master uses the default implementations). Set\nit for all masters that handle commands address-agnostic.\n\nDon\u0027t prefer native 4BA instructions if the master doesn\u0027t support them.\n\nChange-Id: Ife66e3fc49b9716f9c99cad957095b528135ec2c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22421\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "ed098d62d66d91cf7330a37f9b83e303eb7f56d8", "tree": "639b6233e588fd8b4150b42112da36e239ba7fa4", "parents": [ "7e3c81ae7122120fe10d43fcba61a513e2461de9" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Apr 21 23:47:08 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:49:05 2017 +0000" }, "message": "spi: Move ICH BBAR quirk out of the way\n\nGet rid of the layering violations around ICH\u0027s BBAR. Move all the weird\naddress handling into (surprise, surprise) `ichspi.c`. Might fix writes\nfor the `BBAR !\u003d 0` case by accident.\n\nBackground: Some ICHs have a BBAR (BIOS Base Address Configuration\nRegister) that, if set, limits the valid address range to [BBAR, 2^24).\nCurrent code lifted addresses for REMS, RES and READ operations by BBAR,\nnow we do it for all addresses in ichspi. Special care has to be taken\nif the BBAR is not aligned by the flash chip\u0027s size. In this case, the\nlower part of the chip (from BBAR aligned down, up to BBAR) is inacces-\nsible (this seems to be the original intend behind BBAR) and has to be\nleft out in the address offset calculation.\n\nChange-Id: Icbac513c5339e8aff624870252133284ef85ab73\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22396\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7e3c81ae7122120fe10d43fcba61a513e2461de9", "tree": "f505342cd2879b9cc77c2cbf66dda0231869ee9c", "parents": [ "0ee2dc06839d2f4f3197dd0ef51202e51e945bea" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 18:56:50 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:48:28 2017 +0000" }, "message": "spi25: Merge remainder of spi4ba in\n\nChange-Id: If581e24347e45cbb27002ea99ffd70e334c110cf\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22388\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0ee2dc06839d2f4f3197dd0ef51202e51e945bea", "tree": "6eb5e8b7e9f16767ed5b63ea909ecb5b7001414c", "parents": [ "7a077222566c84546dca4a56c1a509626036e429" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 18:27:13 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:47:05 2017 +0000" }, "message": "spi4ba: Drop now obsolete, redundant functions\n\nChange-Id: I1d04448fd1acbfc37b8e17288f497a4292dfd6d6\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22387\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7a077222566c84546dca4a56c1a509626036e429", "tree": "b4cd487275dd4ffc92ad6ac885268842efbe9eb3", "parents": [ "a1672f829328e877d9b8dea7777f25e2eba52d0e" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 18:18:30 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:46:54 2017 +0000" }, "message": "spi25: Remove now obsolete `four_bytes_addr_funcs` path\n\nChange-Id: Idb7c576cb159630da2268813388b497cb5f46b43\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22386\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a1672f829328e877d9b8dea7777f25e2eba52d0e", "tree": "8f90cab7e18bc875241ff66eef153b80e7c4a71b", "parents": [ "f43c654ad0dcb11b2738bbfac9246d09bb1949e5" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 18:00:20 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:45:46 2017 +0000" }, "message": "spi25: Enable native 4BA read and write using feature bits\n\nPrefer the native 4BA instruction when they are supported. In this\ncase, override our logic to decide to use a 4BA address.\n\nChange-Id: I2f6817ca198bf923671a7aa67e956e5477d71848\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22385\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "f43c654ad0dcb11b2738bbfac9246d09bb1949e5", "tree": "1d1f74d771dc2e8e8a67dab985945c00f68e0097", "parents": [ "0ecbacbfca7f919f1780f5062c775d94c7869d81" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 17:47:28 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:44:17 2017 +0000" }, "message": "spi25: Integrate 4BA support\n\nAllow 4-byte addresses for instructions usually used with 3-byte\naddresses. Decide in which way the 4th byte will be communicated\nbased on the state of the chip (i.e. have we enabled 4BA mode)\nand a new feature bit for an extended address register. If we\nare not in 4BA mode and no extended address register is available\nor the write to it fails, bail out.\n\nWe cache the state of 4BA mode and the extended address register\nin the flashctx.\n\nChange-Id: I644600beaab9a571b97b67f7516abe571d3460c1\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22384\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0ecbacbfca7f919f1780f5062c775d94c7869d81", "tree": "2f84f6406d00bc89dd13dfeff3e69f77671a8f9e", "parents": [ "a3140d0b18058610a2694fc3592031a849b0c92a" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 16:50:43 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:42:49 2017 +0000" }, "message": "spi25: Use common code for nbyte read/write and block erase\n\nIntroduce spi_prepare_address() and spi_write_cmd() and use them in\nnbyte_program, nbyte_read and block-erase procedures. The former\nabstracts over the address part of a SPI command to make it exten-\nsible for 4-byte adressing. spi_write_cmd() implements a WREN + write\noperation with address and optionally up to 256 bytes of data. It\nprovides a common path to reduce overall redundancy.\n\nAlso, reduce the polling delay in spi_block_erase_c4() from 500s to\n500ms as the comment suggests.\n\nChange-Id: Ibc1ae48acbfbd427a30bcd64bdc080dc3dc20503\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22383\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "a3140d0b18058610a2694fc3592031a849b0c92a", "tree": "194083a9889bb76a70cb447a14660d6ec449506c", "parents": [ "c8801734727e1e510cbd99e305007b73f9f57e93" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 11:20:58 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:41:38 2017 +0000" }, "message": "spi25: Introduce spi_simple_write_cmd()\n\nspi_simple_write_cmd() executes WREN plus a single byte write and polls\nWIP afterwards. It\u0027s used to replace current spi_erase_chip_*() imple-\nmentations.\n\nChange-Id: Ib244356fa471e15863b52e6037899d19113cb4a9\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22382\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "c8801734727e1e510cbd99e305007b73f9f57e93", "tree": "84c6914f12ad1f4e1b00ae5bc76d159951233af0", "parents": [ "095522cceca4aede4b4a5e8cd74cbbd8f63e1116" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 01 18:19:43 2017 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Dec 19 12:37:06 2017 +0000" }, "message": "internal: Only build on x86 and mipsel\n\ninternal_init() explicitly fails on everything but x86 and mipsel.\nInstead, we can just never build the internal programmer on other\narchitectures and drop a lot of #if boilerplate.\n\nChange-Id: I672ddab0415df3baa49ff39a1c9db1b41d8143a4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22671\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Patrick Rudolph \u003csiro@das-labor.org\u003e\n" }, { "commit": "095522cceca4aede4b4a5e8cd74cbbd8f63e1116", "tree": "dacb6975b940eec5772060afe2af35bfc9adc090", "parents": [ "19eb0792b8439198d7ef0077b8f79f275fa39a9d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 01 18:33:02 2017 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Dec 19 12:36:38 2017 +0000" }, "message": "Move endianness definitions and provide it inside Makefile\n\nAdd an `endiantest.c` similar to `archtest.c` to provide the endianness\ninside the Makefile. The __FLASHROM_(LITTLE|BIG)_ENDIAN__ definitions\nhad to move from `hwaccess.h` into `platform.h`, therefor. This will\nbe used to decide whether to build the internal programmer in a follow-\nup.\n\nChange-Id: I55dcf5a88da48f885cda9ad89ab87395d895a891\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22670\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "19eb0792b8439198d7ef0077b8f79f275fa39a9d", "tree": "b2d1e9a9e53150c48828f2e38afbf6264d48b6ac", "parents": [ "3083ed90c62e9516615e2322f23ca798e5124a8f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Dec 13 00:44:45 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Dec 19 12:30:05 2017 +0000" }, "message": "ichspi: Fix 100 series PCH (Skylake) support\n\nPretty subtle missing `else` made flashrom treat Skylake like older\nchipsets.\n\nChange-Id: I14bf578964124d4677cb5dfca01c9d1b0d279c9c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReported-by: Youness Alaoui \u003ckakaroto@kakaroto.homelinux.net\u003e\nReviewed-on: https://review.coreboot.org/22832\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Youness Alaoui \u003csnifikino@gmail.com\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "3083ed90c62e9516615e2322f23ca798e5124a8f", "tree": "172265fd17a3d1c1184215bf898248505c92d7e0", "parents": [ "57a3b731daa8f0a6ed9d193b1b9e03216b66a802" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Tue May 02 13:25:56 2017 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Dec 11 18:20:59 2017 +0000" }, "message": "flashchips: Add ISSI IS25LP128 and IS25WP128\n\nIS25LP128 is the 3.3V variant, IS25WP128 is the 1.8V variant.\n\nTested read, erase, and write using Dediprog SF600 on each.\n\nChange-Id: Ia1c7a9a950043c30b7525196e03ee394689e89a5\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/22784\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "57a3b731daa8f0a6ed9d193b1b9e03216b66a802", "tree": "3ff81dcdd9f0991d076757b16979e8ba5b792ed4", "parents": [ "48729d31a6d5dcf9ed887df332518594e1ac6310" ], "author": { "name": "Martin Schiller", "email": "ms@dev.tdt.de", "time": "Thu Nov 23 06:24:57 2017 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Mon Dec 11 03:37:30 2017 +0000" }, "message": "Do not stop probing for flashchips after map_flash() failed\n\nInstead, continue probing the next chip.\n\nThis fixes the problem that flashrom aborts probing for\nflashchips if one big flashchip (e.g. 32M/64M) can\u0027t be mapped\nbecause of activated CONFIG_STRICT_DEVMEM kernel option.\n\nChange-Id: Iaecfb6d30a5152c8c4b5d2804efacac85fc615f9\nSigned-off-by: Martin Schiller \u003cms@dev.tdt.de\u003e\nReviewed-on: https://review.coreboot.org/22685\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "48729d31a6d5dcf9ed887df332518594e1ac6310", "tree": "4cbcbcd595c72368d4058ee1cff1e23c7664a3ef", "parents": [ "b007278fac68f6c6f4926df336fd59a78404bbb8" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Fri Dec 08 14:44:07 2017 -0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 10 00:13:07 2017 +0000" }, "message": "flashchips: Mark W25Q128.W as tested\n\nTested read, erase, and write using W25Q128FWSIG and Dediprog SF600.\n\nChange-Id: Id0ef331ad3b3a8ab05a9472f3053f76c0789b1f9\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/22790\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b007278fac68f6c6f4926df336fd59a78404bbb8", "tree": "a4b219351b967333b4486a6fac71f03dfa1729cf", "parents": [ "97a90497a7d0df5076b4412c3e995a7e4a2ff8cc" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Dec 06 21:02:57 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 09 23:11:13 2017 +0000" }, "message": "flashchips: Add MX25L6473F\n\nJust another chip sharing the same ID. Tested by somebody on IRC.\n\nChange-Id: Ibea956e48e10fda91930b65b3bf3b3ae4ad13f63\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22759\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "97a90497a7d0df5076b4412c3e995a7e4a2ff8cc", "tree": "f590cd7fd6b2ab4cd4a6b45c17ff6dddf130fe7c", "parents": [ "6891709a1f04a78bc45ad4174f4416f24169a020" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 01 18:19:43 2017 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 09 22:42:55 2017 +0000" }, "message": "internal: Fix warnings about unused constants\n\nBy adding more #if guards, fix warnings about unused constants that\nare enabled by default in newer GCC versions.\n\nChange-Id: Ib3b6d7c0c2fadc4faeab971673bfadb1a6d25919\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22669\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Patrick Rudolph \u003csiro@das-labor.org\u003e\n" }, { "commit": "6891709a1f04a78bc45ad4174f4416f24169a020", "tree": "e0565fb6640d919bf9278ffa9fbe86abc038298e", "parents": [ "bbf0dbde3855a58f7324dedb81fdcce0f99c1c87" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Nov 13 20:12:58 2017 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Fri Dec 01 00:30:15 2017 +0000" }, "message": "README: Update packaging section for Git repositories\n\nChange-Id: I8d9c56be8c1381b175ce7695c53f31b1767d9d17\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22454\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n" }, { "commit": "bbf0dbde3855a58f7324dedb81fdcce0f99c1c87", "tree": "081df1b795f34cfe65e4d436dc076f967af10c8e", "parents": [ "1f33cb58001f95c3de69f037acae6f72baddca2b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 19 16:29:45 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Nov 21 22:29:27 2017 +0000" }, "message": "chipset_enable: Mark SiS 630 as tested OK\n\nTested on an Elitegroup P6STMT with an SST39SF020A parallel flash [1].\n\n[1] https://mail.coreboot.org/pipermail/flashrom/2017-November/015193.html\n\nChange-Id: If8cc2af262e392bfba326a62c1a48c658c7d6ce8\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22522\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "1f33cb58001f95c3de69f037acae6f72baddca2b", "tree": "863f297f755279f16fbb4f4e2615b01279ae9733", "parents": [ "22f2dc5ec0b13a413a9ce42a5836ec2aa3b1abfc" ], "author": { "name": "Keno Fischer", "email": "keno@juliacomputing.com", "time": "Sun Nov 15 14:58:25 2015 +0000" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Thu Nov 16 06:28:01 2017 +0000" }, "message": "linux_spi: Dynamically detect max buffer size\n\nRead max buffer size from sysfs if available.\n\nChange-Id: Ic541e548ced8488f074d388f1c92174cad123064\nSigned-off-by: Keno Fischer \u003ckeno@juliacomputing.com\u003e\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/22441\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "22f2dc5ec0b13a413a9ce42a5836ec2aa3b1abfc", "tree": "9b496559cd9503628b42f19c5789400e0bcc5373", "parents": [ "1f081530b60ee805532f106f59cc33973e160481" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Aug 31 16:14:22 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 05 22:33:41 2017 +0000" }, "message": "ichspi: Disable software sequencing by default for Skylake\n\nSkylake is a mess, especially with coreboot. We have now a present and\nconfigured software sequencing interface with SCGO supposedly being\nreadonly (Apollo Lake has that feature and a strap documented, Skylake\nbehaviour might be the same). As we can\u0027t easily check if it\u0027s read-\nonly, just enable hardware sequencing by default (even if the software\nsequencing interface seems usable).\n\nChange-Id: I8a13fb9c3ca679b3f7d39ad1dc56d5efdc80045b\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/22274\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "1f081530b60ee805532f106f59cc33973e160481", "tree": "ebb7155eaeda5f891a435d4087e6532ccb8a15c5", "parents": [ "8b2152d54a67e4139525ce49aefe1a6d0e41b85c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 15:01:13 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 05 14:36:50 2017 +0000" }, "message": "spi25_statusreg: Return defined value on failed RDSR\n\nThe interface of spi_read_status_register() is broken and can\u0027t return\nerrors. Let\u0027s not return random stack data at least.\n\nChange-Id: I714b20001a5443bba665c2e0061ca14069777581\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22017\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "8b2152d54a67e4139525ce49aefe1a6d0e41b85c", "tree": "6b2b15743a972873d96c12591767780cdc905539", "parents": [ "f268d8b2d6fe5ea5ab0e0e2c5eec02c16d023ce5" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Aug 31 13:18:49 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 03 16:53:36 2017 +0000" }, "message": "ichspi: Fix software sequencing for Skylake\n\nTwo occurences of ICH9_REG_OPMENU were overlooked and not replaced,\nrendering the software sequencing unusable on Skylake.\n\nChange-Id: I16eebcf37ab8ba39b02f33135535552e380b0b92\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/22273\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Patrick Rudolph \u003csiro@das-labor.org\u003e\n" }, { "commit": "f268d8b2d6fe5ea5ab0e0e2c5eec02c16d023ce5", "tree": "e1bc61384072608248941a03ed03b1c0507816be", "parents": [ "e1a960e0a520263b380d898459b6909a8d7f59c5" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Thu Oct 26 18:45:00 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 03 16:50:17 2017 +0000" }, "message": "Fix standalone ich_descriptor_tool compilation with MinGW and DJGPP\n\nTARGET_OS as well as EXEC_SUFFIX were only set when called via the\nmain makefile and even then __USE_MINGW_ANSI_STDIO was not set\nfor MinGW.\n\nWhile at it, also replace the hardcoded gnu_printf printf format\nattribute with __MINGW_PRINTF_FORMAT which is set according to\n__USE_MINGW_ANSI_STDIO respectively.\n\nChange-Id: Id146f5ba06a0e510397c6f32a2bd7c819a405a25\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21838\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "e1a960e0a520263b380d898459b6909a8d7f59c5", "tree": "afbbff719b0b4dec023f26d8b074ed90be1c6c3a", "parents": [ "4343e7d44006dcda2ea76b0e7625837832141539" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Thu Oct 19 14:54:44 2017 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sat Oct 21 02:15:58 2017 +0000" }, "message": "Use bzip2 when making a tarball\n\nTarballs on download.flashrom.org are generally packaged using bzip2, so\nwe may as well be internally consistent.\n\nChange-Id: Ib9fb1ea6d5994cd0285ce8db9675640fae992773\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/22116\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "4343e7d44006dcda2ea76b0e7625837832141539", "tree": "18f07dec45cafc53621d1af74c33ae60e4169916", "parents": [ "2ec33f9e6a303a729ceb164d34a85563b6e2c1b0" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 10 17:38:07 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 20 19:27:08 2017 +0000" }, "message": "fixup! nicintel_eeprom: Support for I210 emulated EEprom\n\nFix is_i210(), add a comment and break an overlong line.\n\nChange-Id: I5d3f71e4e0f77cc8793e7f395baf69e1fad930a3\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/21934\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "2ec33f9e6a303a729ceb164d34a85563b6e2c1b0", "tree": "05b5cd18d0a9d7393dcefdfc5048f5c66bf91b0d", "parents": [ "615ba1849c1ad67503cf000c9fea311962175525" ], "author": { "name": "Michael Zhilin", "email": "mizhka@gmail.com", "time": "Fri Dec 02 14:41:26 2016 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 19 15:17:05 2017 +0000" }, "message": "Fix serprog on FreeBSD\n\nUsing serprog on FreeBSD to read an SPI flash (MX25L6406) via an\nArduino Nano V3 with flashrom hangs after 5 seconds while reading. The\nproblem is that kernel method \"ttydisc_rint\" ignores some bytes. It\nhappens due to enabled IEXTEN local flag of termios. TTY cuts a few\nbytes, Arduino reads 11264 bytes, but flashrom gets only 11244 bytes\nand waits for the remaining 20 bytes.\n\nThe fix is simple: turn off the IEXTEN local flag.\n\nTested on Arduino Nano V3 + FreeBSD 12-CURRENT.\n\nChange-Id: I7aa6a283d523c544d9b8923cd4c622bf08c0fb3f\nSigned-off-by: Michael Zhilin \u003cmizhka@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/21919\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Urja Rannikko \u003curjaman@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "615ba1849c1ad67503cf000c9fea311962175525", "tree": "94c2b9ad0d8f1e486c2b5ac41acd0b65ebd7225a", "parents": [ "beaefe0f96758297d013bd48b598225410b44e34" ], "author": { "name": "Urja Rannikko", "email": "urjaman@gmail.com", "time": "Thu Jun 15 15:28:27 2017 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 19 15:14:30 2017 +0000" }, "message": "serial: Support custom baud rates on linux\n\nThe function to do this is contained in custom_baud.c because\nof broken include stuff.\n\nChange-Id: I2a20f9182cb85e7bce5d6654a2caf20e6202b195\nSigned-off-by: Urja Rannikko \u003curjaman@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/20224\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "beaefe0f96758297d013bd48b598225410b44e34", "tree": "044fcb25328c80d0c57a9bc5b07cf60be9810ab7", "parents": [ "af111e25a9d00c3d99eae6196c616461cfdfb193" ], "author": { "name": "dhendrix", "email": "dhendrix@chromium.org", "time": "Sun Sep 03 18:06:53 2017 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Tue Oct 17 06:49:59 2017 +0000" }, "message": "Move get_layout() from flashrom.c to layout.c\n\nChange-Id: Ic67cf53abddc0aa905674acbcde717d9aed2f66e\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/21367\nReviewed-by: Philippe Mathieu-Daudé \u003cf4bug@amsat.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "af111e25a9d00c3d99eae6196c616461cfdfb193", "tree": "b3b5ca8fc36a572ece5db17ffa79e2a86e095a97", "parents": [ "e29591dfb30fa8fc2bec930cf3bebe733469fb86" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Sun Oct 08 05:44:10 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Oct 16 16:36:49 2017 +0000" }, "message": "Fix ID of ST M25P05\n\nThe (old) ST (now Micron) M25P05 does only support RES for identification.\nUnfortunately, the vendor datasheet states the same ID as for the M25P10\n(0x10) and thus flashrom has treated these two as evil twins in the past.\nHowever, real hardware confirmed that the real ID of this chip is 0x05.\n\nChange-Id: Idc75f8cb98e7ef0c47c4527cedcc4da3723bd779\nSigned-off-by: Serge Vasilugin \u003cvasilugin@yandex.ru\u003e\nTested-by: Serge Vasilugin \u003cvasilugin@yandex.ru\u003e\nReviewed-on: https://review.coreboot.org/21920\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e29591dfb30fa8fc2bec930cf3bebe733469fb86", "tree": "846fef6ac949d75a035b21ce542f858d9c937c36", "parents": [ "5bdb87e61f154524f37e249fa6ddae893840b9e5" ], "author": { "name": "Timothy Pearson", "email": "tpearson@raptorengineering.com", "time": "Sat Aug 27 15:43:00 2016 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 13:43:28 2017 +0000" }, "message": "Initial MX66L51235F support\n\nChange-Id: I94bee2832469d2df399a09e2f535a107edaec3e7\nSigned-off-by: Timothy Pearson \u003ctpearson@raptorengineering.com\u003e\nReviewed-on: https://review.coreboot.org/19856\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "5bdb87e61f154524f37e249fa6ddae893840b9e5", "tree": "ec2140efe09446bbdce0c046d77b0b2be58cd698", "parents": [ "199ab391145497645967b7629c0f74b1bdd2d46d" ], "author": { "name": "Timothy Pearson", "email": "tpearson@raptorengineering.com", "time": "Sat Aug 27 14:02:50 2016 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 13:38:24 2017 +0000" }, "message": "Initial MX25L25635F support\n\nChange-Id: I292e12d92cdf3961b8d47492a1d5679ff1ea21ce\nSigned-off-by: Timothy Pearson \u003ctpearson@raptorengineering.com\u003e\nReviewed-on: https://review.coreboot.org/19855\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "199ab391145497645967b7629c0f74b1bdd2d46d", "tree": "0a6c99ad32fd78d48c62037068151cf86a0d4eb7", "parents": [ "cc20a9b08e849437a58402f4a64d63d3710684af" ], "author": { "name": "Ed Swierk", "email": "eswierk@skyportsystems.com", "time": "Mon Jul 03 13:33:44 2017 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 12:37:34 2017 +0000" }, "message": "4BA: Add Micron N25Q/MT25QL 32MB and 64MB 3V SPI flash\n\nUse direct 4-byte address commands.\n\nChange-Id: I3c130c5ecf4bcc7cf3b34257cb5fc3df523ce08b\nSigned-off-by: Ed Swierk \u003ceswierk@skyportsystems.com\u003e\nReviewed-on: https://review.coreboot.org/20511\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "cc20a9b08e849437a58402f4a64d63d3710684af", "tree": "01975202af6298ab6c357532b0e1d6e1d77715b8", "parents": [ "d94d254262594b912c65511b5d0675c6ab900d60" ], "author": { "name": "Ed Swierk", "email": "eswierk@skyportsystems.com", "time": "Mon Jul 03 13:17:18 2017 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 12:37:03 2017 +0000" }, "message": "4BA: Allow disabling 4-byte address mode for SPI flash\n\nThis allows us to support flash chips in any of the following\nconfigurations, regardless of whether the chip powers up in 3-byte or\n4-byte address mode.\n\n- standard commands with extended address register (*_4ba_ereg) or\n direct commands (*_4ba_direct) in 3-byte address mode (.set_4ba \u003d\n spi_exit_4ba_*)\n- standard commands (*_4ba) or direct commands (*_4ba_direct) in\n 4-byte address mode (.set_4ba \u003d spi_enter_4ba_*)\n- direct commands (*_4ba_direct) in either address mode (.set_4ba \u003d\n NULL)\n\nChange-Id: I0b25309d731426940fc50956b744b681ab599e87\nSigned-off-by: Ed Swierk \u003ceswierk@skyportsystems.com\u003e\nReviewed-on: https://review.coreboot.org/20510\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d94d254262594b912c65511b5d0675c6ab900d60", "tree": "6e972f84e4bc74db8b76292aadbcc52fd1fba3d7", "parents": [ "7fe85694c4a597abb2a83c2f0f3a62a1a22e130e" ], "author": { "name": "Ed Swierk", "email": "eswierk@skyportsystems.com", "time": "Mon Jul 03 13:02:18 2017 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 12:35:55 2017 +0000" }, "message": "4BA: Add spi_exit_4ba function to switch SPI flash to 3-byte addressing\n\nChange-Id: I553e7fb5028f35e14a3a81b3fa8903c1b321a223\nSigned-off-by: Ed Swierk \u003ceswierk@skyportsystems.com\u003e\nReviewed-on: https://review.coreboot.org/20509\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7fe85694c4a597abb2a83c2f0f3a62a1a22e130e", "tree": "0da033666d79e9b3dc471762d1b02ee41a7a7a8d", "parents": [ "5de3b9b7263196b1d2bf41659ca44c7ea386b8ab" ], "author": { "name": "Boris Baykov", "email": "dev@borisbaykov.com", "time": "Sat Jun 11 18:29:03 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 12:35:08 2017 +0000" }, "message": "4BA: Support for new direct-4BA instructions + W25Q256.V update\n\nLarge flash chips usually support special instructions to work with\n4-bytes address directly from 3-bytes addressing mode and without\ndo switching to 4-bytes mode. There are 13h (4BA Read), 12h (4BA Program)\nand 21h,5Ch,DCh (4BA Erase), correspondingly. However not all these\ninstructions are supported by all large flash chips. Some chips\nsupport 13h only, some 13h,12h,21h and DCh, but not 5Ch. This depends\non the manufacturer of the chip.\n\nThis patch provides code to use direct 4-bytes addressing instructions.\n\nThis code should work but it tested partially only. My W25Q256FV has\nsupport for 4BA_Read (13h), but doesn\u0027t have support 4BA_Program (12h)\nand 4BA_Erase instructions. So, direct 4BA program and erase\nshould be tested after.\n\nPatched files\n-------------\nchipdrivers.h\n+ added functions declarations for spi4ba.c\n\nflash.h\n+ feature definitions added\n\nflashchips.c\n+ modified definition of Winbond W25Q256BV/W25Q256FV chips\n\nflashrom.c\n+ modified switch to 4-bytes addressing for direct-4BA instructions\n\nspi4ba.h\n+ definitions for 4-bytes addressing JEDEC commands\n+ functions declarations from spi4ba.c (same as in chipdrivers.h, just to see)\n\nspi4ba.c\n+ functions for read/write/erase directly with 4-bytes address (from any mode)\n\nChange-Id: Ib51bcc5de7826b30ad697fcbb9a5152bde2c2ac9\nSigned-off-by: Boris Baykov \u003cdev@borisbaykov.com\u003e, Russia, Jan 2014\n[clg: ported from\n https://www.flashrom.org/pipermail/flashrom/2015-January/013198.html ]\nSigned-off-by: Cédric Le Goater \u003cclg@kaod.org\u003e\nReviewed-on: https://review.coreboot.org/20508\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5de3b9b7263196b1d2bf41659ca44c7ea386b8ab", "tree": "f3480e7191c83965a9ab97d429f090e07f30a552", "parents": [ "aa6c37444c1d1a5944ea8bb3912bb0efe27dffce" ], "author": { "name": "Boris Baykov", "email": "dev@borisbaykov.com", "time": "Sat Jun 11 18:29:02 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 12:33:37 2017 +0000" }, "message": "4BA: Support for 4-bytes addressing via Extended Address Register\n\nOn some flash chips data with addresses more than 24-bit field\ncan address may be accessed by using Extended Address Register.\nThe register has 1-byte size and stores high byte of 32-bit address.\nThen flash can be read from 3-bytes addressing mode with writing\nhigh byte of address to this Register. By using this way we have\naccess to full memory of a chip. Some chips may support this method\nonly.\n\nThis patch provides code use Extended Address Register.\n\nPatched files\n-------------\nchipdrivers.h\n+ added functions declarations for spi4ba.c\n\nflash.h\n+ feature definitions added\n\nflashrom.c\n+ modified switch to 4-bytes addressing to support extended address register\n\nspi4ba.h\n+ definitions for 4-bytes addressing JEDEC commands\n+ functions declarations from spi4ba.c (same as in chipdrivers.h, just to see)\n\nspi4ba.c\n+ functions for write Extended Address Register\n+ functions for read/write/erase with Extended Address Register\n\nChange-Id: I09a8aa11de2ca14901f142c67c83c4fa0def4e27\nSigned-off-by: Boris Baykov \u003cdev@borisbaykov.com\u003e, Russia, Jan 2014\n[clg: ported from\n https://www.flashrom.org/pipermail/flashrom/2015-January/013200.html ]\nSigned-off-by: Cédric Le Goater \u003cclg@kaod.org\u003e\nReviewed-on: https://review.coreboot.org/20507\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "aa6c37444c1d1a5944ea8bb3912bb0efe27dffce", "tree": "cd9f0a67153f1b53dc067c10d7db09fc102bd75c", "parents": [ "9912718de18e455e16d26458aca4eac37f792aa2" ], "author": { "name": "Boris Baykov", "email": "dev@borisbaykov.com", "time": "Sat Jun 11 18:29:01 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 12:31:22 2017 +0000" }, "message": "4BA: Winbond W25Q256.V chip (32MB) declaration, 4-bytes addr mode\n\nHere is the definition of new W25Q256xV chip with new functions pointers\nfor 4-bytes addressing reads and writes. Erase functions pointers are\nchanged in their old places. New feature flags for 4-bytes mode added.\n\nPatched files\n-------------\nflashchips.c\n+ added definition for Winbond W25Q256BV/W25Q256FV chips\n\nChange-Id: I90226f453f8147ae5ac7dbbef7549ee3bfacc3d6\nSigned-off-by: Boris Baykov \u003cdev@borisbaykov.com\u003e, Russia, Jan 2014\n[clg: ported from\n https://www.flashrom.org/pipermail/flashrom/2015-January/013201.html ]\nSigned-off-by: Cédric Le Goater \u003cclg@kaod.org\u003e\nReviewed-on: https://review.coreboot.org/20506\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cf4bug@amsat.org\u003e\nReviewed-by: Lijian Zhao \u003clijian.zhao@intel.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "9912718de18e455e16d26458aca4eac37f792aa2", "tree": "d447b47feb1d0f497c17ab6941e0b4c9afbed5cb", "parents": [ "b1f88360fc806ee69d7cf1b9404b3977bc53aace" ], "author": { "name": "Boris Baykov", "email": "dev@borisbaykov.com", "time": "Sat Jun 11 18:29:00 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 12:30:26 2017 +0000" }, "message": "4BA: Flashrom integration for the 4-bytes addressing extensions\n\nThis patch integrates code of the previous patch into Flashrom\u0027s code.\nAll the integrations is around 3 functions spi_nbyte_read, spi_nbyte_program\nand spi_byte_program. After this patch then are not static and can be called\nby their pointers saved in flashchips array. Also I added to flashrom.c some\ncode to switch a chip to 4-bytes addressing mode. And one error message is\ncorrected in spi.c because it\u0027s not suitable for 32-bit addresses.\n\nPatched files\n-------------\nflash.h\n+ added set of 4-bytes address functions to flashchip structure definition\n\nflashrom.c\n+ added switch to 4-bytes addressing more for chips which support it\n\nserprog.c\n+ added 4-bytes addressing spi_nbyte_read call to serprog_spi_read\n\nspi.c\n+ fixed flash chip size check in spi_chip_read\n\nspi25.c\n+ added 4-bytes addressing spi_nbyte_read call to spi_read_chunked\n+ added 4-bytes addressing spi_nbyte_program call to spi_write_chunked\n+ added 4-bytes addressing spi_byte_program call to spi_chip_write_1\n\nConflicts:\n\tserprog.c\n\nChange-Id: Ib051cfc93bd4aa7580519e0e6206d025f3ca8049\nSigned-off-by: Boris Baykov \u003cdev@borisbaykov.com\u003e, Russia, Jan 2014\n[clg: ported from\n https://www.flashrom.org/pipermail/flashrom/2015-January/013205.html ]\nSigned-off-by: Cédric Le Goater \u003cclg@kaod.org\u003e\nReviewed-on: https://review.coreboot.org/20505\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b1f88360fc806ee69d7cf1b9404b3977bc53aace", "tree": "9c2b6aac3c378702d1596b8eb506f87b180638a0", "parents": [ "50a5660c9c11c77c794783cd9a3343bc3ff07b6e" ], "author": { "name": "Boris Baykov", "email": "dev@borisbaykov.com", "time": "Sat Jun 11 18:28:59 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 10:10:17 2017 +0000" }, "message": "fixup! 4BA: Basic support for 4-bytes addressing mode extensions\n\nFix some whitespace, and braces. Remove sector size from comments that I\ncould not verify.\n\nChange-Id: I4faaa036fea744135fa37f405686fb9fd0882806\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/21947\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "50a5660c9c11c77c794783cd9a3343bc3ff07b6e", "tree": "7095a74f39788084a14c3657bc3b868f923f5340", "parents": [ "f4d7772cee806d68a06db5394ab85a6e76904e88" ], "author": { "name": "Boris Baykov", "email": "dev@borisbaykov.com", "time": "Sat Jun 11 18:28:59 2016 +0200" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sat Oct 14 00:46:41 2017 +0000" }, "message": "4BA: Basic support for 4-bytes addressing mode extensions\n\nIf flash chip is switched to 4-bytes addressing mode then all\nread/erase/program instructions will be switched from 3-bytes mode\nto 4-bytes mode. Then well known instructions like 03h (Read),\n02h (Program) and 20h,52h,D8h (Erase) will become one byte longer\nand accept 4-bytes address instead of 3-bytes.\n\nThis patch provides support for well known instructions in 4-bytes\naddressing mode. Also here is the code to enter 4-bytes addressing\nmode by execute the instruction B7h (Enter 4-bytes mode).\n\nPatched files\n-------------\nchipdrivers.h\n+ added functions declarations for spi4ba.c\n\nflash.h\n+ feature definitions added\n\nMakefile\n+ added spi4ba.c\n\nAdded files\n-----------\nspi4ba.h\n+ definitions for 4-bytes addressing JEDEC commands\n+ functions declarations from spi4ba.c (same as in chipdrivers.h, just to see)\n\nspi4ba.c\n+ functions for enter 4-bytes addressing mode\n+ functions for read/write/erase in 4-bytes addressing mode\n\nChange-Id: Ie72e2a89cd75fb4d09f48e81c4c1d927c317b7a7\nSigned-off-by: Boris Baykov \u003cdev@borisbaykov.com\u003e, Russia, Jan 2014\n[clg: ported from\n https://www.flashrom.org/pipermail/flashrom/2015-January/013199.html ]\nSigned-off-by: Cédric Le Goater \u003cclg@kaod.org\u003e\nReviewed-on: https://review.coreboot.org/20513\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "f4d7772cee806d68a06db5394ab85a6e76904e88", "tree": "355098516d28d14ac5f03bd7b4eff3848a9c4ac9", "parents": [ "63bf222cbaa59b7552b9a268a878350b0919117d" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Fri Oct 06 02:02:46 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 06 08:36:00 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\nwithout the upcache there is no \"offline\" version (yet).\n\nChange-Id: Iac3bf11fbd55cfa034ef8af04ef90fe57182ee2b\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21836\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "63bf222cbaa59b7552b9a268a878350b0919117d", "tree": "9c6c2b8637d5f25bbdb7b7b8ec30250416ab6f78", "parents": [ "f3f996e33ddae9bed8d29f27c9f81516478e65ce" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Wed Oct 04 03:12:09 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 06 08:35:46 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\nrefine the pre-push hook:\n - get rid of the concept of precious brances - all of them on the\n upstream repos are precious (this is a change in the face of\n using gerrit instead of a native git repository for staging purposes)\n - likewise, only allow new versioned stable branches and no feature\n branches there\n\nChange-Id: I1d4b4a7ef2673cabee980ec4a7d7d5fbebdcaed1\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21834\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f3f996e33ddae9bed8d29f27c9f81516478e65ce", "tree": "ebc5236fe001d0b657cb1158490dcca2c5f562ad", "parents": [ "3a937b77320f24b648306d90063df39cd08cf633" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Wed Oct 04 02:56:31 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 05 10:46:33 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\n - update the commit-msg to check for duplicate signoffs/acks\n\nChange-Id: Ia36147e673cceb6d175884b40d4bdd00015b96dc\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21833\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3a937b77320f24b648306d90063df39cd08cf633", "tree": "c9bdf39db6adebb02195aa922613423851c75f36", "parents": [ "68b5f00930132c12c98705e7728765171142d2ef" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Sun Oct 01 19:15:10 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 05 10:45:21 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\n - update the commit-msg hook to the latest one provided by Gerrit.\n However, disable the (new) code that would avoid adding Change-IDs\n to fixup/squash commits as needed on the staging branch\n\nChange-Id: I2f2d7ae58dcd7d3e55959e18fe664df10bc3cc41\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21832\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "68b5f00930132c12c98705e7728765171142d2ef", "tree": "2adfd0c736509a4ab2974f011dd16f379fbe8098", "parents": [ "fa25bc3cd433e2cdbf8d0922a29be71815a072cd" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Sun Oct 01 16:52:55 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 05 10:45:08 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\n - wrap a line in the hook installer. The line still exceeds our\n maximum limit by two chars but it makes no sense to break\n apart the one long argument IMHO\n\nChange-Id: I0e931fbb5902d2714d5399c1d1bfac0de35523bb\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21831\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "fa25bc3cd433e2cdbf8d0922a29be71815a072cd", "tree": "c15a00533e57c120f7700284f991af4a9f51aa0f", "parents": [ "5bf6b855d4083070390b5c0eb03bca678090d75d" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Wed Oct 04 03:47:26 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 05 10:43:05 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\n - exploit Make\u0027s -include statement to simplify execution flow\n - expand and refine respective comment to better describe and\n match the new behavior\n\nChange-Id: I0c66f2508cc754cf9219211a06d6f305a32c422d\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21830\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5bf6b855d4083070390b5c0eb03bca678090d75d", "tree": "ee7e58ceb379e20056a6a393f97b749ab29acee0", "parents": [ "8eb1df69ab22829d61366e7d8e4eca6d7ed13657" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Wed Oct 04 03:46:51 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 05 10:41:23 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\nRename getrevision\u0027s local_revision function to just revision.\nAll revisions are local in git and we certainly wont go back to\na non-distributed VCS :)\n\nChange-Id: I6689ac24077b3981b471ed69de7cc3ef79d435b1\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21829\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "8eb1df69ab22829d61366e7d8e4eca6d7ed13657", "tree": "db7a20661678df0e5aa1e724f53e55241dd13f00", "parents": [ "9620912607d5e99650624f74545268bba0f310ca" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Sun Oct 01 16:45:49 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 05 10:40:08 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\nNote the non-strict POSIX compatibility in getrevision.sh and a add missing full stop*.* ;)\n\nChange-Id: Ia60186f783067ba084439a8ef701dc8f4c0072f0\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21828\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "9620912607d5e99650624f74545268bba0f310ca", "tree": "d5fdf853e610a0422e5c64284d68caf397a653a5", "parents": [ "2dc5d294004f5d3ec37cc7bfd5d49ce1a41bf215" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Sun Oct 01 16:41:35 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 05 10:39:25 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\n - make version string generation independent of the actual VCS\n used by not generating \"unknown\" in the makefile but letting\n getrevision do that\n - make hook installation independent of version string generation\n since they have nothing to do with each other and there are no\n synergies anymore\n\nChange-Id: Iedc9df4c033a70447b8b1b65c83764c769b02c3f\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21827\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "2dc5d294004f5d3ec37cc7bfd5d49ce1a41bf215", "tree": "e9a4ac8b9e11e5644f7f7f19788f6c1f33912949", "parents": [ "e4136854f18adcf3e753ebe6a2cc2cc9b9e43201" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Wed Oct 04 02:18:33 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 05 10:37:35 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\nUse a more generic file name for the exported VCS data.\n\nChange-Id: Ie57b20dc014ba44ded5783bdb432eb7d0e0e28ad\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21826\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "e4136854f18adcf3e753ebe6a2cc2cc9b9e43201", "tree": "6c7f39e023d2c4b636f5a4e906a2f3cbb7a4beac", "parents": [ "60f7a221e080e1847b56bd8aa03451c2459efc1c" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Sun Oct 01 15:57:25 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 05 10:37:15 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\nFix broken/one-off loop to restore file dates.\nExplain what the sed program actually does because it is non-trivial.\n\nChange-Id: Iff4021be49a9fab208b619c555b9f9e81f671ab8\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21825\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "60f7a221e080e1847b56bd8aa03451c2459efc1c", "tree": "30e22a28114d451775b7f5f81406e3d6a14cb576", "parents": [ "f0cbbb05c909340607a5e7a14e80523752b6434c" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Sun Oct 01 15:45:06 2017 +0200" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Thu Oct 05 04:10:11 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\nFix broken export\n\nChange-Id: I9d0fe93291de81b4d303589fd01565f429a61e9a\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21824\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f0cbbb05c909340607a5e7a14e80523752b6434c", "tree": "bd0f695ebf6db71d3fb111c5f65cfa681ce9c065", "parents": [ "79d838d31696542105a4185758f23db13d8ea045" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Sun Oct 01 00:49:05 2017 +0200" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Wed Oct 04 01:21:12 2017 +0000" }, "message": "Add modification date to manpage header instead of the section\n\n\"System Manager\u0027s Manual\" or similar is way less interesting.\n\nChange-Id: I45c5d6a2316c51a57a49fd010682dc3f0f915382\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21822\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "79d838d31696542105a4185758f23db13d8ea045", "tree": "20162a2ada71c7ece57f96d9790ce8c7b791bb5c", "parents": [ "75a2a79aebe9ffd0bcdb5f8d014d9e5583973014" ], "author": { "name": "David Hendricks", "email": "dhendrix@chromium.org", "time": "Wed Sep 27 09:25:34 2017 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Tue Oct 03 00:23:34 2017 +0000" }, "message": "fixup! nicintel_eeprom: Support for I210 emulated EEprom\n\nA couple of C99-style variable declarations within loops are causing\ncompilation failures on some systems (gcc 4.9.2-10 on Raspbian). This\nmoves them to make gcc happy.\n\nChange-Id: Ib7ad5a69244e462f84eae93df9e841716e089b31\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/21702\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "75a2a79aebe9ffd0bcdb5f8d014d9e5583973014", "tree": "6ea9442fc25620fb9fe0bf887501a4a715e13610", "parents": [ "26d33d2be2851ce0ac16252bc0997eb67068fbed" ], "author": { "name": "Ricardo Ribalda Delgado", "email": "ricardo.ribalda@gmail.com", "time": "Thu Mar 23 23:38:04 2017 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Sep 17 18:14:28 2017 +0000" }, "message": "nicintel_spi: Define BIT() macro\n\nReplace bit shits with BIT() macro. This improves the readability of the\ncode.\n\nChange-Id: I30315891f18d4d5bfbc247bb9012560479afab90\nSigned-off-by: Ricardo Ribalda Delgado \u003cricardo.ribalda@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/21432\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "26d33d2be2851ce0ac16252bc0997eb67068fbed", "tree": "2a70468056dfd8ca894b8ebee80e6890309eea79", "parents": [ "9fe1fb71c7e53e4f44d633fe52dc33453b36848b" ], "author": { "name": "Ricardo Ribalda Delgado", "email": "ricardo.ribalda@gmail.com", "time": "Wed Mar 22 14:30:52 2017 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Sep 17 18:06:05 2017 +0000" }, "message": "nicintel_spi: Support for I210/I211 cards\n\nImplements I210 \"raw\" flash access as detailed in:\nhttp://www.intel.com/content/www/us/en/embedded/products/networking/i210-ethernet-controller-datasheet.html\n\nUnfortunately, most of the time the card is in Secure Mode, which means\nthat the raw access is not available. But his should be pretty useful\nfor bringing up boards.\n\nChange-Id: I8598ab21297b85dcae1e650a168043aa4cc15c10\nSigned-off-by: Ricardo Ribalda Delgado \u003cricardo.ribalda@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/21430\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "9fe1fb71c7e53e4f44d633fe52dc33453b36848b", "tree": "726c76de3e2b36ea50bb50ff9e87f75aeecd3d21", "parents": [ "7b629bcde47e18d094e496fb8ae537272ead0998" ], "author": { "name": "Ricardo Ribalda Delgado", "email": "ricardo.ribalda@gmail.com", "time": "Thu Mar 23 15:11:22 2017 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Sep 17 18:05:16 2017 +0000" }, "message": "nicintel_eeprom: Support for I210 emulated EEprom\n\nOn the I210 family there is no MAC EEprom, instead there is a big flash\n(typically around 16Mb) with contents of the old MAC plus other stuff.\nThere is an interface to program the whole flash, but once it is\nprogrammed it enters a \"Secure Mode\" that disables the interface.\n\nLuckily, the section with the MAC can still be updated via the EEprom\ninterface. This patch adds support for this interface.\n\nroot@qt5022-fglrx:~# ./flashrom -p nicintel_eeprom:pci\u003d01:0.0 -w kk.raw -V\nflashrom v0.9.9-unknown on Linux 4.10.0-qtec-standard (x86_64)\nflashrom is free software, get the source code at https://flashrom.org\n\nflashrom was built with libpci 3.4.1, GCC 5.3.0, little endian\nCommand line (5 args): ./flashrom -p nicintel_eeprom:pci\u003d01:0.0 -w kk.raw -V\nCalibrating delay loop... OS timer resolution is 1 usecs, 1856M loops per second, 10 myus \u003d 10 us,\n100 myus \u003d 102 us, 1000 myus \u003d 1017 us, 10000 myus \u003d 10044 us, 4 myus \u003d 4 us, OK.\nInitializing nicintel_eeprom programmer\nFound \"Intel I210 Gigabit Network Connection\" (8086:1533, BDF 01:00.0).\nRequested BAR is of type MEM, 32bit, not prefetchable\nRequested BAR is of type MEM, 32bit, not prefetchable\nThe following protocols are supported: Programmer-specific.\nProbing for Programmer Opaque flash chip, 0 kB: Found Programmer flash chip \"Opaque flash chip\"\n(4 kB, Programmer-specific) on nicintel_eeprom.\nFound Programmer flash chip \"Opaque flash chip\" (4 kB, Programmer-specific).\nReading old flash chip contents... done.\nErasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:W\nErase/write done.\nVerifying flash... VERIFIED.\n\nChange-Id: I553f33e5dcb4412d682fc93095b29bcfed11713c\nSigned-off-by: Ricardo Ribalda Delgado \u003cricardo.ribalda@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/21431\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "7b629bcde47e18d094e496fb8ae537272ead0998", "tree": "3c44a9d573fb61ca483054a845722e051558aefd", "parents": [ "8681df128708a548e64865bb6fd8f6cd957e061d" ], "author": { "name": "Ricardo Ribalda Delgado", "email": "ricardo.ribalda@gmail.com", "time": "Wed Mar 22 14:08:31 2017 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Sep 17 18:03:42 2017 +0000" }, "message": "sb600spi: Add support for Merlin Falcon Chipset\n\nThis patch has been tested on a board similar to AMD Bettong.\n\n00:14.0 SMBus [0c05]: Advanced Micro Devices, Inc. [AMD] FCH SMBus\nController [1022:790b] (rev 4a)\n00:14.3 ISA bridge [0601]: Advanced Micro Devices, Inc. [AMD] FCH LPC\nBridge [1022:790e] (rev 11)\nroot@qt5022-fglrx:~# ./flashrom -p internal -w kk.rom\n\nflashrom v0.9.9-unknown on Linux 4.10.0-qtec-standard (x86_64)\nflashrom is free software, get the source code at\nhttps://flashrom.org\n\nCalibrating delay loop... OK.\ncoreboot table found at 0x9ffd6000.\nFound chipset \"AMD FP4\".\nEnabling flash write... OK.\nFound Micron/Numonyx/ST flash chip \"N25Q128..1E\" (16384 kB, SPI)\nmapped at physical address 0x00000000ff000000.\nReading old flash chip contents... done.\nErasing and writing flash chip... Erase/write done.\nVerifying flash... VERIFIED.\n\nChange-Id: I66a240ebc8382cc7e5156686045aee1a9d03fe6d\nSigned-off-by: Ricardo Ribalda Delgado \u003cricardo.ribalda@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/21429\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "8681df128708a548e64865bb6fd8f6cd957e061d", "tree": "835c820539d876f6bbe8b1f3430caf64d3a0d29f", "parents": [ "7a8305f1bd452a74a1679e75383f888b48e67f4d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 28 20:53:29 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Sep 03 20:29:24 2017 +0000" }, "message": ".gitignore: Add Doxygen dir `libflashrom-doc/`\n\nChange-Id: Id25d05cdf6107cc7a99b94a8523e23bd8698c2d6\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/20811\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "7a8305f1bd452a74a1679e75383f888b48e67f4d", "tree": "233c0b969a71ffc196466e5ff4138060a2654bc1", "parents": [ "0eb00d4e77d3ad0fceef62b0d2ea69aa4835aa8e" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Fri Sep 01 20:16:58 2017 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Sep 03 19:33:08 2017 +0000" }, "message": "ich_descriptors: Use MAX_NUM_FLREGS for entries[]\n\n5 regions made sense in 2013 when this bit of code was originally\nwritten. MAX_NUM_FLREGS is now used to keep track of the max number of\nflash regions and is \u003e5 since Sunrise Point.\n\nChange-Id: Idb559e618369fecf930724a7c1c84765247f3e38\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/21338\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "0eb00d4e77d3ad0fceef62b0d2ea69aa4835aa8e", "tree": "9860c6d1b56afd370a1fdeaa7a43511ac96aa095", "parents": [ "a5216367d5640f07d58a6549fa6df86d91daff1a" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Fri Sep 01 20:02:36 2017 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Sep 03 19:32:52 2017 +0000" }, "message": "Move ich_layout from layout.h to ich_descriptors.h\n\nThis moves the ich_layout declaration from one header to another. This\nwill avoid a circular dependency when we update the entries[] member in\nthe follow-up patch to use MAX_NUM_FLREGS which is defined in\nich_descriptors.h.\n\nChange-Id: I08006f1f7c9ccdd17a9a6d74881ed2c8541d4de1\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/21337\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "a5216367d5640f07d58a6549fa6df86d91daff1a", "tree": "72cb2a7ba167ed6d6e0509ad8292ea7283932e7a", "parents": [ "aa91d5c16858cb400cc61e8a759838f645e3f314" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Tue Aug 08 20:02:22 2017 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Fri Sep 01 20:34:44 2017 +0000" }, "message": "chipset_enable: Add support for C620-series Lewisburg PCH\n\nThis adds PCI IDs for C620-series PCHs and adds\nCHIPSET_C620_SERIES_LEWISBURG as a new entry in the ich_chipset enum.\n\nLewisburg is very similar to Sunrise Point for Flashrom\u0027s purposes,\nhowever one important difference is the way the \"number of masters\" is\ninterpreted from the flash descriptor (0-based vs. 1-based). There are\nalso new flash regions defined.\n\nChange-Id: I96c89bc28bdfcd953229c17679f2c28f8b874d0b\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/20922\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "aa91d5c16858cb400cc61e8a759838f645e3f314", "tree": "163b27954a680ea02f945ee383f8dbc7c1cc03c8", "parents": [ "a1bccd88c3c8c0041795b96faef2cb4179bfbd7c" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Sat Aug 19 17:04:21 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Aug 21 21:21:47 2017 +0000" }, "message": "ichspi: \"Fix\" access permission reporting for regions \u003e 7\n\nCan\u0027t find bits that tell us the actual permissions in charge. So report\nthem as unknown.\n\nChange-Id: Ib73f95e0348f5c6d89988e3ea3529af0ec3b23a6\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/21106\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" } ], "next": "a1bccd88c3c8c0041795b96faef2cb4179bfbd7c" }