)]}' { "log": [ { "commit": "f2cd32570eb8624c60e97aecd5c9045249b376fe", "tree": "6a268512dc000d2a0e0a08e68ccad9df4b5853c5", "parents": [ "c4e9fd0abc51959885aafe6312a2d8c9b3935434" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Sep 30 19:03:45 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Nov 01 16:37:32 2018 +0000" }, "message": "flashchips: Add Sanyo LE25FU206/A and LE25FU106B\n\nAs per user `The_Raven Raven` on the mailing list. Since the added\nvalues had some inconsistencies, the chips are marked as untested.\n\nChange-Id: I6c26aafdca232110986334e85297d73d513600dc\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28813\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "c4e9fd0abc51959885aafe6312a2d8c9b3935434", "tree": "d04cdf7484dac323c64eff0ec80526d26e2f3aa5", "parents": [ "61818dc098edf3bf41f2d6502456fe0cd078c007" ], "author": { "name": "Tristan Corrick", "email": "tristan@corrick.kiwi", "time": "Thu Nov 01 00:33:57 2018 +1300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Nov 01 11:06:07 2018 +0000" }, "message": "chipset_enable.c: Mark Intel H81 as DEP\n\nTested on an ASRock H81M-HDS. The flash chip has been read, written, and\nerased many times without issue. Most boards with this chipset will have\nthe ME region locked, hence the selection of DEP.\n\nChange-Id: I30aae956b2851c741e59403f5e49b80b5ba7c5e4\nSigned-off-by: Tristan Corrick \u003ctristan@corrick.kiwi\u003e\nReviewed-on: https://review.coreboot.org/29391\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "61818dc098edf3bf41f2d6502456fe0cd078c007", "tree": "ac2ba748f001cf84e2b69edbc48f169adac70797", "parents": [ "4987679d73fbbf270c4c2ee628652985d02de3c4" ], "author": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Oct 28 01:02:21 2018 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 30 09:39:15 2018 +0000" }, "message": "flashchips: Add IS25LP256 and IS25WP256\n\nTested IS25LP256 using Raspberry Pi and Dediprog SF600 programmers.\nTested IS25WP256 using Dediprog SF600.\n\nChange-Id: Idf7a224abcde5f7935d9ef88309f78207de60a7a\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/29306\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "4987679d73fbbf270c4c2ee628652985d02de3c4", "tree": "b07ff5f9d3a2de7e04b9ba7179bccfd8d0d81134", "parents": [ "3a41e2a27e45f17889b0789eb2ba43b97af0d1b6" ], "author": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sat Oct 27 20:19:42 2018 +0000" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Mon Oct 29 22:50:49 2018 +0000" }, "message": "flashchips: Add W25Q256JV support\n\nSimilar to W25Q256FV, but it supports the native 4BA page program\ninstruction (12h). Note that the variant with QE enabled by default\nshares the device ID of the W25Q256FV.\n\nTested using a Raspberry Pi.\n\nChange-Id: I76d7362777d364594d2a733d7e478741b0bef7c4\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/29305\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "3a41e2a27e45f17889b0789eb2ba43b97af0d1b6", "tree": "e3dad0477a3486c447feb447aae67d2057132f66", "parents": [ "f56607e66bdce71ec992c167633c7e7f0eb0482c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Sep 23 17:45:59 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 23 21:15:53 2018 +0000" }, "message": "dmi: Remove nonsense guard; Makefile handles it\n\nChange-Id: If4216be1f9ed308e4580c36d0356480e637ffc82\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/28715\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n" }, { "commit": "f56607e66bdce71ec992c167633c7e7f0eb0482c", "tree": "737e077587a7356ade0d48cf1ac80a935330b7d5", "parents": [ "c82900b661420989856a969cd9edf27410b758eb" ], "author": { "name": "Kasper Revsbech", "email": "krev@triax.com", "time": "Fri Oct 19 23:59:17 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 23 21:15:45 2018 +0000" }, "message": "flashchips: Mark MX25L25635F as tested\n\nAs reported by Kasper Revsbech on 2018-10-19.\n\nChange-Id: Icf05288c4e7e34af2e3f4b951457df695078847d\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/29202\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "c82900b661420989856a969cd9edf27410b758eb", "tree": "2f0ac2c60530769830ee6386047712fb46cdccd0", "parents": [ "4acc3f3a8990cda15f04e5eabf028c5cda0d6619" ], "author": { "name": "Arthur Heymans", "email": "arthur@aheymans.xyz", "time": "Wed Jan 10 12:48:16 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 23 21:15:05 2018 +0000" }, "message": "Add support to get layout from fmap (e.g. coreboot rom)\n\nFlashmap, or simply fmap, is a binary data format for describing\nregion offsets, sizes, and certain attributes and is widely used by\ncoreboot. This patch adds support for the fmap data format version 1.1\nand adds --fmap and --fmap-file arguments.\n\nUsing --fmap will make flashrom to search the ROM content for fmap\ndata. Using --fmap-file will make flashrom search a supplied file\nfor fmap data.\n\nAn example of how to update the COREBOOT region of a ROM:\nflashrom -p programmer --fmap -w coreboot.rom -i COREBOOT\nflashrom -p programmer --fmap-file coreboot.rom -w coreboot.rom -i COREBOOT\n\nThe fmap functions are mostly copied from cbfstool.\n\nCurrently it is made mutually exclusive with other layout options until\nwe are more clever about this input.\n\nChange-Id: I0e7fad38ed79a84d41358e1f175c36d255786c12\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/23203\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nTested-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Werner Zeh \u003cwerner.zeh@siemens.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "4acc3f3a8990cda15f04e5eabf028c5cda0d6619", "tree": "ce763d072afff4636de2c9fc9f8622ebfc67cc18", "parents": [ "73ab88d58ee6ca1f0a822faafe0b14996e65ddbf" ], "author": { "name": "Sergey Alirzaev", "email": "zl29ah@gmail.com", "time": "Wed Aug 01 16:39:17 2018 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Oct 08 14:01:08 2018 +0000" }, "message": "ft2232_spi: add an ability to use GPIO for chip selection\n\nChange-Id: I6db05619e0d69ad18549c8556ef69225337b1532\nSigned-off-by: Sergey Alirzaev \u003czl29ah@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28911\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "73ab88d58ee6ca1f0a822faafe0b14996e65ddbf", "tree": "bd539c80e1d257465ab421de57c8f0118be8f273", "parents": [ "f112e242ab84534eee1b8e90e9cd6302a0db742f" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Oct 07 13:07:55 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Oct 08 11:59:15 2018 +0000" }, "message": "chipset_enable.c: Mark Intel HM65 as DEP\n\nTested reading, writing and erasing the internal flash chip using a\nToshiba L755 laptop with an Intel HM65. However, since all ME-enabled\nchipsets are marked as DEP instead of OK, this one shall follow suit as\nwell.\n\nChange-Id: I3fd62c3b4ee17a403cc3937422f3d850fd2878a4\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28955\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f112e242ab84534eee1b8e90e9cd6302a0db742f", "tree": "82a8febc4e1cc1a215a0675d46034817698c2467", "parents": [ "34323495319fe20da7b7f7585fd70f0edcb8c53a" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Sep 30 20:14:17 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 07 11:16:41 2018 +0000" }, "message": "flashchips: Add Macronix MX25U8032E\n\nAs per `The_Raven Raven` on the mailing list.\n\nChange-Id: I422c3d51e5011e081ff6bccff294817c8c1765d0\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28821\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "34323495319fe20da7b7f7585fd70f0edcb8c53a", "tree": "218d2d4a1ff1e9ae068e10d89ab586b512abd197", "parents": [ "2f1d0076b3e3b8a85ae0e698949079305cac87a2" ], "author": { "name": "Patrick Rudolph", "email": "patrick.rudolph@9elements.com", "time": "Thu Oct 04 14:59:40 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 05 14:26:28 2018 +0000" }, "message": "flashchips: Add W25Q128.V..W\n\nPort the code from chromeos flashrom.\nTested using W25Q128JVSIM in SPI mode.\n\nChange-Id: I38397a0c831407afa21cddca8485664576fce92c\nSigned-off-by: Patrick Rudolph \u003cpatrick.rudolph@9elements.com\u003e\nReviewed-on: https://review.coreboot.org/28910\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "2f1d0076b3e3b8a85ae0e698949079305cac87a2", "tree": "3654cda71f7827f494b2817632edc705ae2ae11a", "parents": [ "1a7fb6e0c327bc23290ad02a2b97410f15fdde4a" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Thu Oct 04 10:42:42 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 05 11:36:07 2018 +0000" }, "message": "Remove unneeded whitespace\n\nChange-Id: I0e72e3e3736a39685b7f166c5e6b06cc241b26be\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/28707\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "1a7fb6e0c327bc23290ad02a2b97410f15fdde4a", "tree": "26a80659f05c6fdf6dc93ddda41f46bbed36b582", "parents": [ "b27b8d1d1627b7eef592901fe4b8648180c58a3a" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 02 20:34:13 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 04 07:56:54 2018 +0000" }, "message": "flashchips: Mark S25FL208K as tested\n\nAs report by Frédéric Germain on 2017-12-17.\n\nChange-Id: I0a7fc10e75f4a675de41e9765525defe2d2640e4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/28883\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "b27b8d1d1627b7eef592901fe4b8648180c58a3a", "tree": "5705fe1b340c164809085f2ee7a625692314de48", "parents": [ "49e23d2e3750c91776662380fea4c6e6e3b1e14f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 02 20:46:21 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 04 07:55:56 2018 +0000" }, "message": "flashchips: Add ISSI IS25WP064 and IS25WP032\n\nThe IS25WP064 was tested successfully by Simon Buhrow as reported on\n2018-9-4. While we are at it, also add the 32Mbit version which shares\nthe datasheet (as does the already supported 128Mbit version).\n\nChange-Id: Ie0887b4ae6e6465118a5dc2e20b784f783d161b8\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/28884\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "49e23d2e3750c91776662380fea4c6e6e3b1e14f", "tree": "4b26dbbf3877520cf43b06329cb279e100f0256d", "parents": [ "6329b0af1d5338ed5e6066168544b80f9a2c4435" ], "author": { "name": "Hal Martin", "email": "hal.martin@gmail.com", "time": "Sun May 27 14:18:43 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 14:49:39 2018 +0000" }, "message": "flashchips: Add ATMEL AT25SL128A\n\nChange-Id: I60c433ffe9e34663c2cfc608b8b76943cd92a8ba\nSigned-off-by: Hal Martin \u003chal.martin@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/26576\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "6329b0af1d5338ed5e6066168544b80f9a2c4435", "tree": "c0d96e76e958d4a8499a1e49784c1e8e23ee5e08", "parents": [ "86bddb5d52659f23531282db137350cbf7fb5992" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Mar 13 18:14:52 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 13:16:20 2018 +0000" }, "message": "Enable native 4BA instructions for Spansion 25FL256S\n\nChange-Id: I0ffc816ca714ecce5b89b1eaadb5e73ccb38d9ab\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: Michael Fuckner \u003cmichael@fuckner.net\u003e\nReviewed-on: https://review.coreboot.org/25134\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "86bddb5d52659f23531282db137350cbf7fb5992", "tree": "2f2b2da3f475065c9e86218b79ded18547c6b2c3", "parents": [ "57dbd64b33143964bb8eb91d33d72a2147f0091c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Mar 13 18:14:52 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 13:14:57 2018 +0000" }, "message": "Enable 4BA mode for Spansion 25FL256S\n\n4BA mode is entered by setting bit 7 for the extended address register.\n\nChange-Id: I807bf55d65763a9f48a6a3377f14f4e5288a7a4c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: Michael Fuckner \u003cmichael@fuckner.net\u003e\nReviewed-on: https://review.coreboot.org/25133\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "57dbd64b33143964bb8eb91d33d72a2147f0091c", "tree": "1606d103406bf36144602971ca2ac970d3a61482", "parents": [ "3eb5a8c82c00769bffc95c2c6c479de6d20dbd09" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Mar 13 18:01:05 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 13:10:17 2018 +0000" }, "message": "flashchips: Add Spansion 25FL256S......0\n\nThe Spansion 25SFL256S supports 4BA through an extended address register,\na 4BA mode set by bit 7 of that register, or native 4BA instructions.\nEnable the former only for now.\n\nUnfortunately the S25SF256S uses another instruction to write the exten-\nded address register. So we add an override for the instruction byte.\n\nChange-Id: I0a95a81dfe86434f049215ebd8477392391b9efc\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: Michael Fuckner \u003cmichael@fuckner.net\u003e\nReviewed-on: https://review.coreboot.org/25132\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "3eb5a8c82c00769bffc95c2c6c479de6d20dbd09", "tree": "5fcad139204c37de57ac9b47da2f554c620266fa", "parents": [ "250aebaadba0bfcd8dd25558e9e5a9aaa3b15c43" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Tue Oct 02 01:21:24 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 12:15:35 2018 +0000" }, "message": "flashchips: Mark Spansion S25FL128P......0 as tested\n\nTested with a Spansion FL128PIF.\n\nChange-Id: Ic99eabb67d5bce3910e9275d0056a7cfa8cff36f\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28866\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "250aebaadba0bfcd8dd25558e9e5a9aaa3b15c43", "tree": "ed4947e32d351ad00ece54185f8033cdd10ae8a1", "parents": [ "3164a0cb28aa592f93d1a07ec11b01cc2039e87d" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Sep 30 20:28:22 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 11:55:55 2018 +0000" }, "message": "flashchips: Mark Atmel AT45DB081D as tested\n\nAs per `The_Raven Raven` on the mailing list.\n\nChange-Id: I225984b9e2589713f25d0f9b49eb1c3abdcff3cd\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28825\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "3164a0cb28aa592f93d1a07ec11b01cc2039e87d", "tree": "cdc8818c97a7b5ec6a5176c8aee1b8dba07d83bf", "parents": [ "05127bf4a4a235bbd8f82d655334c4cf35651c24" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Sep 30 20:26:06 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 11:55:37 2018 +0000" }, "message": "flashchips: Mark Winbond W25Q40BW as tested\n\nAs per `The_Raven Raven` on the mailing list.\n\nThe tested chip was `W25Q40.W`, but it was later renamed to `W25Q40BW`\nwhen the `W25Q40EW` was added.\n\nChange-Id: I624adef2c5b4dd83f0ce93d6069e315fc407db19\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28824\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "05127bf4a4a235bbd8f82d655334c4cf35651c24", "tree": "e43a6ef233c41c96709fe1884aaf8414ea4b96a6", "parents": [ "ce2c09d80f98ca19247c0f9bd34a8e1a5fc687a6" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Sep 30 20:23:24 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 11:55:17 2018 +0000" }, "message": "flashchips: Mark PMC Pm25LD040 as tested\n\nAs per `The_Raven Raven` on the mailing list.\n\nChange-Id: Ied8d07c54f8a222dbe05503f859f82bba27d8336\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28823\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "ce2c09d80f98ca19247c0f9bd34a8e1a5fc687a6", "tree": "2420bf3300c54b98f732d9367dcbd50d13bc530f", "parents": [ "f5822a8b9a0dfc1ca25b1c88f0162a362b1d585e" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Sep 30 20:22:02 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 11:55:04 2018 +0000" }, "message": "flashchips: Mark Sanyo LE25FU406C as tested\n\nAs per `The_Raven Raven` on the mailing list.\n\nChange-Id: I1dba38d03c826a53bff3ddad0aa536032c5532a1\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28822\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f5822a8b9a0dfc1ca25b1c88f0162a362b1d585e", "tree": "7ff4672ccfe023088b9d23019910f8ef871e12ef", "parents": [ "bce364ca7873196714ff54314049e23a2feee62c" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Sep 30 20:09:58 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 11:52:49 2018 +0000" }, "message": "flashchips: Mark PMC Pm25LD020 as tested\n\nAs per `The_Raven Raven` on the mailing list.\n\nChange-Id: I16d5a207599b434fe52b42709e42f1f32a8e6698\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28820\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "bce364ca7873196714ff54314049e23a2feee62c", "tree": "0d291e00cba81d530d2ced0b46c56e94d2483f99", "parents": [ "6f08835c0ab7ab35888cf675e280104420620eb9" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Sep 30 20:04:14 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 11:52:28 2018 +0000" }, "message": "flashchips: Mark GigaDevice GD25Q128C as tested\n\nAs per Tomasz Walach on the mailing list.\n\nChange-Id: Ib0d7485c7221f92ec13995c58065a48e08f57cd8\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28819\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "6f08835c0ab7ab35888cf675e280104420620eb9", "tree": "9a80fa4e2a0ae38406b3cab271a13760a3ddb94c", "parents": [ "c4d3efbffdf22367c71ec712c828969aafadab54" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Sep 30 19:59:42 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 11:51:07 2018 +0000" }, "message": "flashchips: Mark AMIC A25L40PU as tested\n\nAs per Stefan Szwarnowski on the mailing list.\n\nChange-Id: I574094bdb83611a3cda2fcc455bcf9aed3774011\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28818\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "c4d3efbffdf22367c71ec712c828969aafadab54", "tree": "5d58335b26f0643e815664fe7eda48ff47c0ae01", "parents": [ "3130cbd89b14bf29da32a9c151a4a633fb023e54" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Sep 30 19:39:41 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 11:50:51 2018 +0000" }, "message": "chipset_enable.c: Mark Broadwell U Premium as DEP\n\nAs per Laurent Grimaud on the mailing list. I also have said chipset.\nSince all ME-enable chipsets are marked as DEP instead of OK, this\none shall follow suit as well.\n\nChange-Id: Ie195e8ec9ea1a2393e31bebdaede4fd3c3301a17\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28817\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "3130cbd89b14bf29da32a9c151a4a633fb023e54", "tree": "d8862d6adc354b5a5f64f164082ea089b19f8d4b", "parents": [ "09dddd83bbc3ffcadee55f5e5c34046505b25611" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Sep 30 19:32:30 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 11:50:35 2018 +0000" }, "message": "flashchips: Mark Winbond W25Q256.V as tested\n\nAs per Richard Hughes via the mailing list.\n\nChange-Id: Ic562a65d1a7d394f9d2c3980833d10a87bd9358a\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28816\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "09dddd83bbc3ffcadee55f5e5c34046505b25611", "tree": "0e5c0ea87c8e35df5128d2ce133ce0741d1f2af7", "parents": [ "8b5b9627822a41acb264d2e11a19bed36f07fd4e" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Sep 30 19:23:43 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 11:49:32 2018 +0000" }, "message": "flashchips: Mark Macronix MX66L51235 as tested\n\nAs per Nick (cel366) on 2018-05-16 via mailing list.\n\nChange-Id: I44363e6755167adbc120444a481b09bb4e1063c5\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28815\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "8b5b9627822a41acb264d2e11a19bed36f07fd4e", "tree": "d1e44aee6edc50005e273d787633b2d66f6d3c23", "parents": [ "471da8334578e3d880f7cef3fc07b087188279ea" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Sep 30 19:13:15 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 11:48:57 2018 +0000" }, "message": "flashchips: Mark Atmel AT25DF161 as tested\n\nAs per Konstantin on 2018-06-08 via mailing list.\n\nChange-Id: I75fb4b17cf330451489811ae9303cbb33ebcb183\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28814\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "471da8334578e3d880f7cef3fc07b087188279ea", "tree": "1107398f702531d8359c04297f1bb8a4e1e5dfa7", "parents": [ "c748be5f7142b59a8656b51e990fc4990c37e2b2" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Sep 30 17:29:48 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 11:44:39 2018 +0000" }, "message": "flashchips: Mark Macronix MX25U12835F as tested\n\nAs reported by David Martinka on the mailing list.\n\nErase has not been tested, but since writes are reported as working, it\nis very likely erase works as well.\n\nChange-Id: I172453fe902ccface2a3a85817d775d45dd7cf80\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28812\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "c748be5f7142b59a8656b51e990fc4990c37e2b2", "tree": "64f042d4c4337c4745adfd25b679b8cf86428a3c", "parents": [ "20657ce19c0ed4c138997462f57e1aacfb9ef3a5" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Sep 30 17:23:03 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 11:25:31 2018 +0000" }, "message": "flashchips: Mark Eon EN25S40 as tested\n\nAs reported by `The_Raven Raven` on the mailing list.\n\nChange-Id: I00f9c6fcf13c486765d0ac4fe06a8b0989b03f91\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28811\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "20657ce19c0ed4c138997462f57e1aacfb9ef3a5", "tree": "bf4b7c2e185ac6fb3dd39d7e0ae1868ebe68c041", "parents": [ "2ef47f384a07915d8eb780375343d8c9e083296c" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Sep 30 17:05:18 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 11:23:47 2018 +0000" }, "message": "flashchips: Mark GigaDevice GD25B128B/GD25Q128B as tested\n\nAlexander reported this chip as tested using a GD25B128CPIG (same device\nID, apparently) on 2018-08-30 via the mailing list. The chip name is\nupdated as well.\n\nChange-Id: I134d3816c0f02e20764ab132a01bcba9f4e93f0d\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28810\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "2ef47f384a07915d8eb780375343d8c9e083296c", "tree": "c425232ff88dacffab59604749d687e503ad79d8", "parents": [ "3ed5a3555a1aeccfa00a996686c3036068015bdd" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Sep 30 16:47:30 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 11:20:29 2018 +0000" }, "message": "flashchips: Add ISSI IS25LP064\n\nGrabbed from mailing list, created by Simon Buhrow. Since no logs were\nattached, the chip is marked as untested.\n\nChange-Id: Idc26162fc5a5a429acef546b30b12d8b1f195e0a\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28809\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "3ed5a3555a1aeccfa00a996686c3036068015bdd", "tree": "ad7e3b400bb6bd16806a0666b55bf85be4ed6b40", "parents": [ "cabe3206abd8d0cf51d80c55fa1e6464faf46008" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Sep 30 16:31:09 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 11:18:30 2018 +0000" }, "message": "flashchips: Mark Micron MT25QL512 as tested\n\nAs reported by `Yuta Teshima` on the mailing list.\n\nChange-Id: I7325d42b43b71ab5fc2c7618e0577e4a7b31f01a\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28808\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "cabe3206abd8d0cf51d80c55fa1e6464faf46008", "tree": "e3ff87dad26c2d8be11e4559506941c3ec93b083", "parents": [ "7ecfe48b19c3e97341a3f2b0d85e7367ab92f2b6" ], "author": { "name": "Jay Thompson", "email": "thompson.jay.thomas@gmail.com", "time": "Fri Aug 17 14:30:04 2018 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Sep 11 12:34:00 2018 +0000" }, "message": "Add initial support for Dediprog SF200.\n\nChange-Id: I025d1533e249f6a75b6d9015a18a6abf350456b6\nSigned-off-by: Jay Thompson \u003cthompson.jay.thomas@gmail.com\u003e\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/28272\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "7ecfe48b19c3e97341a3f2b0d85e7367ab92f2b6", "tree": "8114881424b47ca6c3044e39da8e16615001887b", "parents": [ "af499198a49fe342a0bb3dbbfa362b8788a8fb4e" ], "author": { "name": "Marc Schink", "email": "flashrom-dev@marcschink.de", "time": "Thu Mar 17 16:07:23 2016 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 30 09:55:57 2018 +0000" }, "message": "helpers: Add reverse_byte() and reverse_bytes()\n\nChange-Id: I9d2e1e2856c835d22eed3b3a34bc0379773dd831\nSigned-off-by: Marc Schink \u003cflashrom-dev@marcschink.de\u003e\nReviewed-on: https://review.coreboot.org/28086\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "af499198a49fe342a0bb3dbbfa362b8788a8fb4e", "tree": "1d3b92f384508e6622ed91240a50477a07884148", "parents": [ "1d507a07a919f49e74aa05803bf37919ac95adb1" ], "author": { "name": "Daniel Thompson", "email": "daniel.thompson@linaro.org", "time": "Thu Jul 12 12:03:51 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 30 09:54:50 2018 +0000" }, "message": "usbdev: Refactor device discovery code\n\nCurrently there is a lot of code shared between\nusb_dev_get_by_vid_pid_serial() and usb_dev_get_by_vid_pid_number().\nFix this by pulling out the conditional filtering at the heart of each loop\nand calling it via a function pointer.\n\nI haven\u0027t got (two) dediprog programmers to test with but I have tested\nboth by...serial() and by...number() calls using a pair of Developerboxen\nand a hacked driver.\n\nChange-Id: I31ed572501e4314b9455e1b70a5e934ec96408b1\nSigned-off-by: Daniel Thompson \u003cdaniel.thompson@linaro.org\u003e\nReviewed-on: https://review.coreboot.org/27444\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "1d507a07a919f49e74aa05803bf37919ac95adb1", "tree": "24d460c41877990f4a6724c0e8b4513e2d679daa", "parents": [ "ccfa8f9d9a68b1e4238d2dbbc4e9c8bcf9bae8a6" ], "author": { "name": "Daniel Thompson", "email": "daniel.thompson@linaro.org", "time": "Thu Jul 12 11:02:28 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 30 09:53:58 2018 +0000" }, "message": "usbdev: Extract libusb1 device discovery into a separate file\n\nCurrently there is a TODO-like comment in the dediprog driver: \"Might be\nuseful for other USB devices as well\". Act on this comment by collecting\nall the device discovery code for libusb1 devices into a separate file.\n\nChange-Id: Idfcc79371241c2c1dea97faf5e532aa971546a79\nSigned-off-by: Daniel Thompson \u003cdaniel.thompson@linaro.org\u003e\nReviewed-on: https://review.coreboot.org/27443\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "ccfa8f9d9a68b1e4238d2dbbc4e9c8bcf9bae8a6", "tree": "d8b4b128709d5c5173269494c56d388c8e8434dd", "parents": [ "e2c90c45f7d1dbdd02269f0a8f3c95cb8ee5fa91" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Tue Aug 21 03:30:58 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Aug 22 10:26:51 2018 +0000" }, "message": "chipset_enable.c: Mark Intel HM55 as DEP\n\nTested reading, writing and erasing the internal flash chip using an HP\n630 laptop with an Intel HM55. However, since all ME-enabled chipsets\nare marked as DEP instead of OK, this one shall follow suit as well.\n\nChange-Id: Iaedd5bdc34dfff9b8588a3f4e1ad46460077fdf9\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28253\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "e2c90c45f7d1dbdd02269f0a8f3c95cb8ee5fa91", "tree": "2abda8ef6e3506d00711dcf527b97f61a5b930fd", "parents": [ "5bd11dc8476b4b17cef58d8d855f2b50e74da2f4" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Sat Aug 18 09:04:41 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Aug 19 10:42:45 2018 +0000" }, "message": "Fix typos\n\nChange-Id: I20745d5f30f9577622e27abf2f45220f026f65ac\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/28206\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "5bd11dc8476b4b17cef58d8d855f2b50e74da2f4", "tree": "1d11b50457a755374ede6d3981248d7e1cd5cfd2", "parents": [ "c6fe5d83373783973cfa3c0ab8499f05b23da02f" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Sat Aug 18 09:24:26 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Aug 19 10:41:55 2018 +0000" }, "message": "Remove empty line at EOF\n\nChange-Id: Id6063cb5d406d7139abf7fcdf2ae265363640f9f\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/28207\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "c6fe5d83373783973cfa3c0ab8499f05b23da02f", "tree": "1edc2ebe199cd1038bd4ce522c8945bf6b3fe926", "parents": [ "5a7f942b2810884d0f6e8c7c677c683f64b1e784" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Aug 18 12:45:58 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Aug 19 10:40:31 2018 +0000" }, "message": "flashchips: Mark GigaDevice GD25Q512 as tested\n\nAs reported by `nvflash` on IRC.\n\nChange-Id: Id3928e3790ddac34645959535e646d552ce5328e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/28209\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\n" }, { "commit": "5a7f942b2810884d0f6e8c7c677c683f64b1e784", "tree": "438c3e0d37ededa25dca7169db7fb65e307fdf02", "parents": [ "cadd42025cf5694a391f6cedb6374117336ae2c8" ], "author": { "name": "Nathan Rennie-Waldock", "email": "nathan.renniewaldock@gmail.com", "time": "Fri Aug 10 15:35:23 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Aug 17 21:32:14 2018 +0000" }, "message": "Add support for MX25R6435F\n\nChange-Id: I664ffce6f9aa7544e17b516a1b4179d561208b2f\nSigned-off-by: Nathan Rennie-Waldock \u003cnathan.renniewaldock@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28004\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "cadd42025cf5694a391f6cedb6374117336ae2c8", "tree": "75a95655047afb6f9446dcb91b363f011301a162", "parents": [ "45e91a278cd31019ad6ed5a465661001fbaee065" ], "author": { "name": "Daniel Thompson", "email": "daniel.thompson@linaro.org", "time": "Mon Jun 04 13:52:22 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Aug 17 21:17:41 2018 +0000" }, "message": "flashchips: Add Macronix MX25U51245G\n\nCopy \u0027n paste support for Macronix MX25U51245G. I don\u0027t pretend to know\na whole lot about SPI FLASH so its mostly copied from other MX25U devices\nand double checked a few bits and pieces against the datasheet.\n\nI have tested basic probe, read, erase and write using layout files. I\ntested both with 4MB@0x0000000 and 64K0@0x3f00000 (the later means I\nhave tested 4-byte addressing).\n\nChange-Id: I2117fc205006088967f3d97644375d10db1791f1\nSigned-off-by: Daniel Thompson \u003cdaniel.thompson@linaro.org\u003e\nReviewed-on: https://review.coreboot.org/26949\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "45e91a278cd31019ad6ed5a465661001fbaee065", "tree": "c8cf0b31e69ff5efae8c283369fc67aeab4a6e5c", "parents": [ "455a6fc86e833d1165c68d9dbaef8b0188875bc5" ], "author": { "name": "Daniel Thompson", "email": "daniel.thompson@linaro.org", "time": "Mon Jun 04 13:46:29 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Aug 17 21:17:13 2018 +0000" }, "message": "programmer: Add Developerbox/CP2104 bit bang driver\n\nThe 96Boards Developerbox (a.k.a. Synquacer E-series) provides a CP2102\ndebug UART with its GPIO pins hooked up to the SPI NOR FLASH. The\ncircuit is intended to provide emergency recovery functions without\nrequiring any additional tools (such as a JTAG or SPI programmer). This\nwas expected to be very slow (and it is) but CP2102 is much cheaper than\na full dual channel USB comms chip.\n\nRead performance is roughly on par with a 2400 baud modem (between 60\nand 70 minutes per megabyte if you prefer) and write performance is 50%\nslower still. The full recovery process, with backup and verification of\n4MB data written takes between 14 and 15 hours. Thus it is only really\npractical as an emergency recovery tool, firmware developers will need\nto use an alternative programmer.\n\nChange-Id: I2547a96c1a2259ad0d52cd4b6ef42261b37cccf3\nSigned-off-by: Daniel Thompson \u003cdaniel.thompson@linaro.org\u003e\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/26948\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\n" }, { "commit": "455a6fc86e833d1165c68d9dbaef8b0188875bc5", "tree": "d362e9f7fe5096e83b1c3df9d3ee0d4c225017fc", "parents": [ "b623f403a00a6ce796fe632d4c1ff3fc4f5a5e40" ], "author": { "name": "Daniel Thompson", "email": "daniel.thompson@linaro.org", "time": "Tue Jun 05 09:55:20 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Aug 17 21:16:57 2018 +0000" }, "message": "bitbang_spi: Add half-duplex optimizations\n\nCurrently, the core of bitbang_spi is a full-duplex SPI loop but in\npractice this code is only ever used half-duplex. Spliting this code\ninto two half duplex loops allows us to optimize performance by reducing\ncommunications and/or CPU pipeline stalls.\n\nThe speed up varies depending on how much the overhead of\ngetting/setting pins dominates execution time. For a USB bit bang driver\nrunning on a 7th generation Core i5, the time to probe drops from ~7.7\nseconds to ~6.7 seconds when this patch is applied.\n\nChange-Id: I33b9f363716f651146c09113bda5fffe53b16738\nSigned-off-by: Daniel Thompson \u003cdaniel.thompson@linaro.org\u003e\nReviewed-on: https://review.coreboot.org/26947\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "b623f403a00a6ce796fe632d4c1ff3fc4f5a5e40", "tree": "a2f753c253a18afe6cb09134b9a15d26eca3233b", "parents": [ "9891b75d96a199d1740fbd7df805abf23ae8f347" ], "author": { "name": "Daniel Thompson", "email": "daniel.thompson@linaro.org", "time": "Tue Jun 05 09:38:19 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Aug 17 21:16:12 2018 +0000" }, "message": "bitbang_spi: Add functions to optimize xfers\n\nOn systems where the overhead of getting/setting pins is much greater\nthan the half period (for example, USB bit banging) it significantly\nboosts performance if we can bang more than one bit at the same time.\nAdd support for setting sck at the same time as mosi or miso activity.\n\nThe speed up varies depending on how much the overhead of\ngetting/setting pins dominates execution time. For a USB bit bang driver\nrunning on a 7th generation Core i5, the time to probe drops from ~9.2\nseconds to ~7.7 seconds when set_clk_set_mosi() is implemented.\n\nChange-Id: Ic3430a9df34844cdfa82e109456be788eaa1789a\nSigned-off-by: Daniel Thompson \u003cdaniel.thompson@linaro.org\u003e\nReviewed-on: https://review.coreboot.org/26946\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\nReviewed-by: Idwer Vollering \u003cvidwer@gmail.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "9891b75d96a199d1740fbd7df805abf23ae8f347", "tree": "b446b94916b2a99ca816db1125bd534f20a3f602", "parents": [ "f3ce951fb3d9d23d97a39f0b7e8a090dd477d45a" ], "author": { "name": "Arthur Heymans", "email": "arthur@aheymans.xyz", "time": "Tue Jul 17 02:44:41 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jul 31 20:46:13 2018 +0000" }, "message": "board_enable.c: Fix dmi_match string for ThinkPad X201\n\nTESTED, flashrom now properly works on Thinkpad X201 running vendor\nfirmware and coreboot.\n\nChange-Id: I40dc7204499323148707b392d94ecd4b212f9ace\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-on: https://review.coreboot.org/27504\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Patrick Rudolph \u003csiro@das-labor.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\n" }, { "commit": "f3ce951fb3d9d23d97a39f0b7e8a090dd477d45a", "tree": "71cfad3c91f0fc21906f712e4e8eae129189676e", "parents": [ "b2154e8a1d456875122cbbff2a18e5e1c55ef4d2" ], "author": { "name": "Arthur Heymans", "email": "arthur@aheymans.xyz", "time": "Tue Jul 17 02:16:44 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jul 31 20:45:52 2018 +0000" }, "message": "digilent_spi: Avoid deprecated libusb functions\n\nlibusb 1.0.22 marked libusb_set_debug as deprecated. For such versions of\nlibusb, use libusb_set_option instead.\n\nChange-Id: Ie139de36f15c4f4d87787cab0f968a2f0e6f0c8c\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-on: https://review.coreboot.org/27503\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Martin Roth \u003cmartinroth@google.com\u003e\n" }, { "commit": "b2154e8a1d456875122cbbff2a18e5e1c55ef4d2", "tree": "ee5cf1e29adf35b89d6078ba117638b4009cfd89", "parents": [ "ac01baa073b0f154ffd3ffdc7c9e75987f8b525c" ], "author": { "name": "Lubomir Rintel", "email": "lkundrak@v3.sk", "time": "Sun Jan 14 17:35:33 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 26 10:02:38 2018 +0000" }, "message": "digilent_spi: add a driver for the iCEblink40 development board\n\nThis is driver that supports the Lattice iCE40 evaluation kits. On the\nboard is a SPI flash memory chip labeled ST 25P10VP.\n\nTested to work read/write/erase with \"-p digilent_spi -c M25P10\" or\nwith a patch that resets the part beforehands (in which case it gets\ndetected as a M25P10-A and is way faster due to paged writes).\n\nChange-Id: I7ffcd9a2db4395816f0e8b6ce6c3b0d8e930c9e6\nSigned-off-by: Lubomir Rintel \u003clkundrak@v3.sk\u003e\nReviewed-on: https://review.coreboot.org/23338\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "ac01baa073b0f154ffd3ffdc7c9e75987f8b525c", "tree": "c81104f7a8f08db2c6f0cc5d59f8f0e3fe7ea494", "parents": [ "b0247b3acbc7d8d9f8da1db48a9b81c5f2e24a38" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Mon May 28 16:52:21 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 24 13:44:51 2018 +0000" }, "message": "Remove unneeded white spaces\n\nChange-Id: I90f171924790ced74a62ca344fee8607607aa480\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/26652\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "b0247b3acbc7d8d9f8da1db48a9b81c5f2e24a38", "tree": "27ecfdd694592aab18bec64d887a8cb65c1ae9e2", "parents": [ "a75a2edc05a006c10caa24ccbee12c2b3ddaee66" ], "author": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Wed May 23 21:50:18 2018 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 24 11:47:50 2018 +0000" }, "message": "linux_mtd: Bail out early if sysfs node doesn\u0027t exist\n\nThis checks that the MTD sysfs node we will use actually exists prior\nto calling setup code. Although the setup code will eventually catch\nsuch an error, we need to think about the use case before printing a\npossibly irrelevant/confusing error message to the terminal.\n\nThis patch makes it so that we only print an error message if the\nuser specifies a non-existent MTD device. Otherwise, the failure is\nconsidered benign and we only print a debug message prior to bailing\nout.\n\nChange-Id: I8dc965eecc68cd305a989016869c688fe1a3921f\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/26500\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "a75a2edc05a006c10caa24ccbee12c2b3ddaee66", "tree": "9c1019723c739f5a3e1019bbcb6be88f9d2ff71c", "parents": [ "0b59b0dafc219ba73ee2af5404ce626575d74c6f" ], "author": { "name": "Miklós Márton", "email": "martonmiklosqdev@gmail.com", "time": "Tue Jan 30 20:25:00 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jun 23 19:41:49 2018 +0000" }, "message": "Fix mingw detection on Windows 7 (NT-6.1)\n\nHopefully also for other non-XP Windows build environments.\n\nChange-Id: I7f856dc4847c4ca9197b1935b7a9b9071b46c70a\nSigned-off-by: Miklós Márton \u003cmartonmiklosqdev@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/23865\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "0b59b0dafc219ba73ee2af5404ce626575d74c6f", "tree": "66d5ca2bc1266e1c5d1111c26ab48264feb4393b", "parents": [ "a50b8fde67fa52984980159127de789cf9a1c688" ], "author": { "name": "Steffen Mauch", "email": "steffen.mauch@gmail.com", "time": "Sat Jun 02 23:46:03 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jun 06 08:57:36 2018 +0000" }, "message": "Add support for AT25DF021A\n\nThis is the low-voltage version of the AT25DF021. Tested with FT2232H\nMini Module\n\nChange-Id: If4990e6856c8b77567ef4218459cf754b9c6bc57\nSigned-off-by: Steffen Mauch \u003csteffen.mauch@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/26856\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a50b8fde67fa52984980159127de789cf9a1c688", "tree": "cb7230f818fd01fd47e22de2258e1d6914528b74", "parents": [ "291c101c66adcb1c3435934f3f49fa7f24f7c249" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Mar 20 14:25:09 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jun 04 10:28:53 2018 +0000" }, "message": "chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs\n\nThe Kaby Lake \"200 Series\" PCHs [1,2] share the register layout of their\nSkylake \"100 Series\" siblings.\n\n[1] Intel® 200 Series (including X299) and Intel® Z370 Series\n Chipset Families Platform Controller Hub (PCH)\n Datasheet - Volume 1 of 2\n Revision 003\n Document Number 335192\n\n[2] Intel® 200 Series (including X299) Chipset Family Platform\n Controller Hub (PCH)\n Datasheet - Volume 2 of 2\n Revision 003\n Document Number 335193\n\nChange-Id: Ida545d69ec998a5d3ae4dc88e76adbb13952bceb\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/26232\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "291c101c66adcb1c3435934f3f49fa7f24f7c249", "tree": "a10fe95c4e63493f1939e471f391b7a52fafab85", "parents": [ "7590d1a9375e94d01cef08a2bde10a05177d5829" ], "author": { "name": "Evan Jensen", "email": "evan.p.jensen@gmail.com", "time": "Thu May 17 14:30:19 2018 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jun 04 09:53:50 2018 +0000" }, "message": "Add support for the AT25SF081\n\nChange-Id: I1a3d900462ad9e7a3b34575d7c98acc7c2df0445\nSigned-off-by: Evan Jensen \u003cevan.p.jensen@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/26779\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "7590d1a9375e94d01cef08a2bde10a05177d5829", "tree": "a69d185d67f2b7d846d5f92b358b917b82696b0a", "parents": [ "f9a30554803a670f9b95a7794be00f03929d6ecd" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Tue May 03 13:38:28 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue May 29 14:56:51 2018 +0000" }, "message": "Enable writes with active ME\n\nReplace the `ich_spi_force` logic with more helpful warnings. These can\nbe hidden later, in case the necessary switches are detected. Also,\ndemote some warnings about settings that are the default nowadays (e.g.\nSPI configuration lock, inaccessible ME region).\n\nChange-Id: I94a5e7074b845c227e43d76d04dd1a71082a1cef\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/26261\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "f9a30554803a670f9b95a7794be00f03929d6ecd", "tree": "46da1dafce0c76ab5730540540aaf4093463f551", "parents": [ "291764a70e6d8b212680e311bfb0825abf2b9a2f" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Sat May 23 20:30:30 2015 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Thu May 17 16:49:16 2018 +0000" }, "message": "linux_mtd: Import driver from ChromiumOS\n\nThis imports a series of patches from chromiumos for MTD support.\nThe patches are squashed to ease review and original Change-Ids have\nbeen removed to avoid confusing Gerrit.\n\nThere are a few changes to integrate the code:\n- Conflict resolution\n- Makefile changes\n- Remove file library usage from linux_mtd. We may revisit this and use\n it for other Linux interfaces later on.\n- Switch to using file stream functions for reads and writes.\n\nThis consolidated patch is\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\n\nThe first commit\u0027s message is:\nInitial MTD support\n\nThis adds MTD support to flashrom so that we can read, erase, and\nwrite content on a NOR flash chip via MTD.\n\nBUG\u003dchrome-os-partner:40208\nBRANCH\u003dnone\nTEST\u003dread, write, and erase works on Oak\n\nSigned-off-by: David Hendricks \u003cdhendrix@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/272983\nReviewed-by: Shawn N \u003cshawnn@chromium.org\u003e\n\nThis is the 2nd commit message:\n\nlinux_mtd: Fix compilation errors\n\nThis fixes compilation errors from the initial import patch.\n\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\n\nThis is the 3rd commit message:\n\nlinux_mtd: Suppress message if NOR device not found\n\nThis just suppresses a message that might cause confusion for\nunsuspecting users.\n\nBUG\u003dnone\nBRANCH\u003dnone\nTEST\u003dran on veyron_mickey, \"NOR type device not found\" message\nno longer appears under normal circumstances.\nSigned-off-by: David Hendricks \u003cdhendrix@chromium.org\u003e\n\nReviewed-on: https://chromium-review.googlesource.com/302145\nCommit-Ready: David Hendricks \u003cdhendrix@chromium.org\u003e\nTested-by: David Hendricks \u003cdhendrix@chromium.org\u003e\nReviewed-by: Shawn N \u003cshawnn@chromium.org\u003e\n\nThis is the 4th commit message:\n\nlinux_mtd: Support for NO_ERASE type devices\n\nSome mtd devices have the MTD_NO_ERASE flag set. This means\nthese devices don\u0027t require an erase to write and might not have\nimplemented an erase function. We should be conservative and skip\nerasing altogether, falling back to performing writes over the whole\nflash.\n\nBUG\u003db:35104688\nTESTED\u003dZaius flash is now written correctly for the 0xff regions.\n\nSigned-off-by: William A. Kennington III \u003cwak@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/472128\nCommit-Ready: William Kennington \u003cwak@google.com\u003e\nTested-by: William Kennington \u003cwak@google.com\u003e\nReviewed-by: Brian Norris \u003cbriannorris@chromium.org\u003e\n\nThis is the 5th commit message:\n\nlinux_mtd: do reads in eraseblock-sized chunks\n\nIt\u0027s probably not the best idea to try to do an 8MB read in one syscall.\nTheoretically, this should work; but MTD just relies on the SPI driver\nto deliver the whole read in one transfer, and many SPI drivers haven\u0027t\nbeen tested well with large transfer sizes.\n\nI\u0027d consider this a workaround, but it\u0027s still good to have IMO.\n\nBUG\u003dchrome-os-partner:53215\nTEST\u003dboot kevin; `flashrom --read ...`\nTEST\u003dcheck for performance regression on oak\nBRANCH\u003dnone\n\nSigned-off-by: Brian Norris \u003cbriannorris@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/344006\nReviewed-by: David Hendricks \u003cdhendrix@chromium.org\u003e\n\nThis is the 6th commit message:\n\nlinux_mtd: make read/write loop chunks consistent, and documented\n\nTheoretically, there should be no maximum size for the read() and\nwrite() syscalls on an MTD (well, except for the size of the entire\ndevice). But practical concerns (i.e., bugs) have meant we don\u0027t quite\ndo this.\n\nFor reads:\nBug https://b/35573113 shows that some SPI-based MTD drivers don\u0027t yet\nhandle very large transactions. So we artificially limit this to\nblock-sized chunks.\n\nFor writes:\nIt\u0027s not clear there is a hard limit. Some drivers will already split\nlarge writes into smaller chunks automatically. Others don\u0027t do any\nsplitting. At any rate, using *small* chunks can actually be a problem\nfor some devices (b:35104688), as they get worse performance (doing an\ninternal read/modify/write). This could be fixed in other ways by\nadvertizing their true \"write chunk size\" to user space somehow, but\nthis isn\u0027t so easy.\n\nAs a simpler fix, we can just increase the loop increment to match the\nread loop. Per David, the original implementation (looping over page\nchunks) was just being paranoid.\n\nSo this patch:\n * clarifies comments in linux_mtd_read(), to note that the chunking is\n somewhat of a hack that ideally can be fixed (with bug reference)\n * simplifies the linux_mtd_write() looping to match the structure in\n linux_mtd_read(), including dropping several unnecessary seeks, and\n correcting the error messages (they referred to \"reads\" and had the\n wrong parameters)\n * change linux_mtd_write() to align its chunks to eraseblocks, not page\n sizes\n\nNote that the \"-\u003epage_size\" parameter is still somewhat ill-defined, and\nonly set by the upper layers for \"opaque\" flash. And it\u0027s not actually\nused in this driver now. If we could figure out what we really want to\nuse it for, then we could try to set it appropriately.\n\nBRANCH\u003dnone\nBUG\u003db:35104688\nTEST\u003dvarious flashrom tests on Kevin\nTEST\u003dReading and writing to flash works on our zaius machines over mtd\n\nChange-Id: I3d6bb282863a5cf69909e28a1fc752b35f1b9599\nSigned-off-by: Brian Norris \u003cbriannorris@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/505409\nReviewed-by: David Hendricks \u003cdhendrix@chromium.org\u003e\nReviewed-by: Martin Roth \u003cmartinroth@chromium.org\u003e\nReviewed-by: William Kennington \u003cwak@google.com\u003e\nReviewed-on: https://review.coreboot.org/25706\nTested-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Philipp Deppenwiese \u003czaolin.daisuki@gmail.com\u003e\n" }, { "commit": "291764a70e6d8b212680e311bfb0825abf2b9a2f", "tree": "8c6d1c5156ba4e73169d4b541704a4f7c6326566", "parents": [ "2099c648b929cd36c500202089ef4b7a8c14680f" ], "author": { "name": "Alex James", "email": "theracermaster@gmail.com", "time": "Sat Apr 14 22:59:57 2018 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri May 11 16:32:42 2018 +0000" }, "message": "ch341a_spi: Avoid deprecated libusb functions\n\nlibusb 1.0.22 marked libusb_set_debug as deprecated. For such versions\nof libusb, use libusb_set_option instead.\n\nChange-Id: Ib71ebe812316eaf49136979a942a946ef9e4d487\nSigned-off-by: Alex James \u003ctheracermaster@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/25681\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "2099c648b929cd36c500202089ef4b7a8c14680f", "tree": "d934dc4be97cd3e0e97b948f66463142c598b8cd", "parents": [ "256835787229205b6522a3c12322b22303bb4152" ], "author": { "name": "Maxime Vincent", "email": "maxime.vince@gmail.com", "time": "Fri Nov 24 13:04:08 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri May 11 16:15:19 2018 +0000" }, "message": "buspirate_spi: Tristate IOs when using using pullup\u003don\n\nAvoid putting 3.3V on IO pins when pullup\u003don to avoid damage to 1.8V\nchips.\n\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nChange-Id: I9ac4c6b7a0079bb1022f2d70030a6eb29996108f\nReviewed-on: https://review.coreboot.org/23864\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "256835787229205b6522a3c12322b22303bb4152", "tree": "2748ffea8f72a8d7000fc8b928df9756c689aca1", "parents": [ "25584de9d0108a5dde41e0296fdf0a7854390a81" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Mar 30 13:50:13 2018 +0200" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun May 06 21:00:41 2018 +0000" }, "message": "flashchips: Add Winbond 25Q40EW and rename 25Q40.W\n\nSame story as for 25Q80BW/EW, 25Q40EW has a new ID and the only known\nchip with the old ID is the BW variant.\n\nChange-Id: Ib610b0d6f3a5561b2ac3505ef15bdee8b0edae25\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/25462\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "25584de9d0108a5dde41e0296fdf0a7854390a81", "tree": "d505c037e5a2e729e1eb64882c60fd69fcb1b40e", "parents": [ "1b365931ea8a9d5766972c17c7cf91b9de595fb1" ], "author": { "name": "Wei Hu", "email": "wei@aristanetworks.com", "time": "Mon Apr 30 14:02:08 2018 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun May 06 20:56:02 2018 +0000" }, "message": "flashchips: Add SST26VF016B(A), SST26VF032B(A), SST26VF064B(A)\n\nThis patch seems to have originally been from\nhttps://patchwork.coreboot.org/patch/4126/ . The most recent version\nseems to be in OpenEmbedded (commit 503a572) which added support for\n16Mbit and 32Mbit variants.\n\nThe OpenEmbedded patch also makes changes to linux_spi.c to add some\ndebug prints which are omitted in this version.\n\nFrom the original commit message:\nDifferences between SST26 and SST25:\n1. The WREN instruction must be executed prior to WRSR [Section 5.31].\n There is no EWSR.\n2. Block protection bits are no longer in the status register. There\n is a dedicated 144-bit register [Table 5-6]. The device is\n write-protected by default. A Global Block-Protection Unlock\n command unlocks the entire memory [Section 4.1].\n\nChange-Id: Ib019bed8ce955049703eb3376c32a83ef607c219\nSigned-off-by: Wei Hu \u003cwei@aristanetworks.com\u003e\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@student.tuwien.ac.at\u003e\nReviewed-on: https://review.coreboot.org/25962\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "1b365931ea8a9d5766972c17c7cf91b9de595fb1", "tree": "36230b9c41038bc2e97c090907bb9c8472d9b71a", "parents": [ "e083880279119677e443fc16b4694f8c81bf2c40" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Wed Apr 25 16:03:51 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Apr 25 14:36:38 2018 +0000" }, "message": "udelay.c: Remove trailing whitespace\n\nChange-Id: Ibd77c2a99bd839c01ae7ff058365eda7e30db261\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/25824\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "e083880279119677e443fc16b4694f8c81bf2c40", "tree": "03413b996779bc4c86ec41590f3e7bcdd97d0ef5", "parents": [ "124ef38f7afc61ad7c713c22aad7c5c7f79bdb9b" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Mon Apr 02 11:14:02 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 24 20:21:41 2018 +0000" }, "message": "Remove address from GPLv2 headers\n\nChange-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/25381\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "124ef38f7afc61ad7c713c22aad7c5c7f79bdb9b", "tree": "980f498681fcc053ec1e591e22bb16afbef0a191", "parents": [ "3f7e3419887c6d37330387f8e32c86ba47bdf70c" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Tue Mar 27 12:15:09 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 24 20:18:58 2018 +0000" }, "message": "Fix whitespace errors\n\nChange-Id: Ic2d3bb9d8581a0471a8568a130f893b34dddf113\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/25380\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "3f7e3419887c6d37330387f8e32c86ba47bdf70c", "tree": "e51bbf17118c5ae3a4c1894892643ef09a6c8dbd", "parents": [ "f73f8a732f8fd37a6a7dfef4acb7f7c416832ab2" ], "author": { "name": "Luc Verhaegen", "email": "libv@skynet.be", "time": "Wed Mar 28 12:31:22 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Mar 29 11:01:20 2018 +0000" }, "message": "board_enable: add AOpen i965GMt-LA\n\nChange-Id: I8899bbe06707fe76256539f90f5b670301228d52\nSigned-off-by: Luc Verhaegen \u003clibv@skynet.be\u003e\nReviewed-on: https://review.coreboot.org/25396\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f73f8a732f8fd37a6a7dfef4acb7f7c416832ab2", "tree": "4d65a6d09dd2a30bb24ba82aad1747c9c0a79e9b", "parents": [ "c699f5cde113377099d038234c1e46e7b928336f" ], "author": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Wed Feb 21 07:34:34 2018 -0800" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Wed Mar 28 22:07:50 2018 +0000" }, "message": "dediprog: implement command spec for firmware \u003e\u003d 7.2.30\n\nThis adds support for the latest command spec for Dediprog SF100/SF600\nprogrammers. Since we now have more than two protocols to\ndeal with the is_new_prot() function is replaced with protocol() which\nreturns an enum specifying which protocol is supported.\n\nThe latest spec (FW \u003e\u003d 7.2.30) updates read and write packets. It\u0027s\nbeen tested on an SF600 using firmware 7.2.21 and SF600Plus using FW\n7.2.30.\n\nThe latest command protocol has a few small but important changes:\n- Read packets have two more bytes:\n 11: B4Addr: address len (3 or 4)\n 12: Dummy cycle /2\n\n- Write packets have four more bytes:\n 11, 12: 16 HSBs of page size\n 13, 14: 16 LSBs of page size\n\n(The spec seems to be mistaken, though, as 11 and 12 are actually\n LSBs instead of HSBs)\n\nChange-Id: I1a53c143948ec40d40433621891a2871d8815f2f\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/23836\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "c699f5cde113377099d038234c1e46e7b928336f", "tree": "de4124ad4da2436bdde3f527b17b4239c2defa79", "parents": [ "f5775448448d62c334a24618cd19692bb4a5f8a6" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Sun Mar 11 17:29:49 2018 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Wed Mar 28 19:37:12 2018 +0000" }, "message": "flashchips: W25Q80.W --\u003e W25Q80BW\n\nThe W25Q80BW appears to have been succeeded by the W25Q80EW which has a\ndifferent manufacturer ID but is otherwise similar. Consequently, W25Q80.W\nno longer matches all chips in this family.\n\nThis patch makes the original entry specific to W25Q80BW.\n\nChange-Id: I2980272c2691eb62a68056a7a4c308e9b4810347\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/25100\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f5775448448d62c334a24618cd19692bb4a5f8a6", "tree": "baf27821d13eba40852c7547a46fa9fec0108368", "parents": [ "a9a03cc6ba71825bfae0d64e1888f33c77345bc3" ], "author": { "name": "Stanislav Sedov", "email": "ssedov@fb.com", "time": "Wed Mar 07 14:16:51 2018 -0800" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Wed Mar 28 19:34:59 2018 +0000" }, "message": "Add support for Atmel/Adesto AT25SF161 and Winbond W25Q80EW\n\nChange-Id: Ia9e8f7f23896f7002401c6b1e616c0dc102198e2\nSigned-off-by: Stanislav Sedov \u003cssedov@fb.com\u003e\nReviewed-on: https://review.coreboot.org/25099\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "a9a03cc6ba71825bfae0d64e1888f33c77345bc3", "tree": "ac9eebdd5036f969f0eadb6d57c62f0bc964d6fc", "parents": [ "b6e3d257f97fd4e3998e0743968d17010047b4c1" ], "author": { "name": "Khem Raj", "email": "raj.khem@gmail.com", "time": "Sat Mar 17 23:08:29 2018 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Mar 23 14:33:38 2018 +0000" }, "message": "platform: Add riscv to known platforms\n\nChange-Id: I724a99e2493fcbf71c2fc2d9f6a1ad607c737087\nSigned-off-by: Khem Raj \u003craj.khem@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/25260\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "b6e3d257f97fd4e3998e0743968d17010047b4c1", "tree": "6932c164c28e36b00788b35db201dbe40660e058", "parents": [ "22418428ed28d803bfca151623bbf017d1ba6bfc" ], "author": { "name": "Antonio Ospite", "email": "ao2@ao2.it", "time": "Sat Mar 03 18:40:24 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Mar 23 14:31:49 2018 +0000" }, "message": "Fix compilation with older MinGW versions\n\nThe __MINGW_PRINTF_FORMAT constant has been defined back in 2012\nhttps://sourceforge.net/p/mingw-w64/mingw-w64/ci/77bc5d6103b5fb9f59fbddab1583e69549913312/\n\nHowever older toolchains are still around and some user reported the\nfollowing compilation failure:\n\n flash.h:336:1: error: \u0027__MINGW_PRINTF_FORMAT\u0027 is an unrecognized format function  type [-Werror\u003dformat\u003d]\n  __attribute__((format(__MINGW_PRINTF_FORMAT, 2, 3)));\n\nFix this by defining the constant when it isn\u0027t already; the change does\nnot affect other compilers because it\u0027s guarded by \"#ifdef __MINGW32__\".\n\nSetting __MINGW_PRINTF_FORMAT to gnu_printf is exactly what newer MinGW\nversions do when __USE_MINGW_ANSI_STDIO is defined, which it is in\nflashrom Makefile.\n\nChange-Id: I48de3e4303b9a389c515a8ce230282d9210576fd\nTested-by: Miklos Marton \u003cmartonmiklosqdev@gmail.com\u003e\nSigned-off-by: Antonio Ospite \u003cao2@ao2.it\u003e\nReviewed-on: https://review.coreboot.org/25130\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "22418428ed28d803bfca151623bbf017d1ba6bfc", "tree": "6fbf0e0bd0ce3dd315c849309f4f62139a933756", "parents": [ "a3ab6c6c3ae7ec62944aad580bbfc1701b3a8581" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Mar 08 16:14:15 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Mar 20 10:01:20 2018 +0000" }, "message": "linux_spi: Reduce maximum read chunksize\n\nIt turned out that older kernels use a single buffer of `bufsiz` bytes\nfor combined input and output data. So we have to account for the read\ncommand + max 4 address bytes.\n\nChange-Id: Ide50db38af1004fde09a70b15938e77f5e1285ac\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nTested-by: Julian von Mendel \u003cgit@jinvent.de\u003e\nReviewed-on: https://review.coreboot.org/25149\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Julian von Mendel \u003cgit@jinvent.de\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "a3ab6c6c3ae7ec62944aad580bbfc1701b3a8581", "tree": "2c40d90017f1a810983692cf6d969d90dbcd6e64", "parents": [ "4f444794de11bd638ebe8daef5c8364c20a8e8ec" ], "author": { "name": "jvm", "email": "git@jinvent.de", "time": "Thu Mar 08 15:43:20 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Mar 14 11:04:04 2018 +0000" }, "message": "Add support for Atmel / Adesto AT25SF041 SPI flash chip\n\nprobe/erase/read/write/verify hardware-tests were done.\n\nChange-Id: I0be930ff2258300508398e12fbe5abe10400fea2\nSigned-off-by: Julian von Mendel \u003cgit@jinvent.de\u003e\nSigned-off-by: jvm \u003cgit@jinvent.de\u003e\nReviewed-on: https://review.coreboot.org/25047\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "4f444794de11bd638ebe8daef5c8364c20a8e8ec", "tree": "14333facfdb159334f5297dde7b9357b2a0c2bb5", "parents": [ "1d50abc4cc1892e2b81999396de795f0c63b57ca" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@student.tuwien.ac.at", "time": "Mon Jun 27 11:44:03 2011 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Mar 08 09:17:52 2018 +0000" }, "message": "dmi: Don\u0027t print dmidecode shell error\n\nDon\u0027t print the error \"sh: dmidecode: not found\" if dmidecode is not there.\nUses stderr redirection to /dev/null (or NUL on Windows).\n\nChange-Id: I3ded8e1bad14b5e809185a79c4e3a17329b1ecb9\nSigned-off-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@student.tuwien.ac.at\u003e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/23802\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\n" }, { "commit": "1d50abc4cc1892e2b81999396de795f0c63b57ca", "tree": "ce8927ee3e66b6959db11fb83d4c80cc4c5dafb4", "parents": [ "a72d5a98286272094dda06f5c69b48910f6a7451" ], "author": { "name": "Arthur Heymans", "email": "arthur@aheymans.xyz", "time": "Sat Jun 03 21:29:55 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Mar 07 12:53:00 2018 +0000" }, "message": "Whitelist Lenovo Thinkpad X220\n\nCoreboot uses the subvendor VID/DID of the Thinkpad X220-Tablet for\nall X220 variants. Don\u0027t specify a dmidecode string so that it can be\nused with coreboot on all X220 variants and on X220-Tablet with vendor\nfirmare.\n\nChange-Id: Idd667da8209a664469c1a909a549d2b625714a78\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-on: https://review.coreboot.org/23225\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "a72d5a98286272094dda06f5c69b48910f6a7451", "tree": "f75e3e21a0309e493158027b6b762b93e8968b1a", "parents": [ "4164c54196deca789b80e6a0b1be5f70e142b729" ], "author": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Feb 11 17:58:44 2018 -0800" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Thu Feb 22 01:37:55 2018 +0000" }, "message": "flashchips: Add ZD25D20\n\nThis adds another Zetta Device chip, the ZD25D20.\n\nChange-Id: Idf805252647be44e28296a161d2e6160710bcc71\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/23702\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "4164c54196deca789b80e6a0b1be5f70e142b729", "tree": "1ac54bf4faea74f55f26f82bb7b757d9522cacfb", "parents": [ "cbb46e261d5f2837df21e0853c7cd4170d226b40" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 22 02:09:18 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Feb 21 21:20:50 2018 +0000" }, "message": "git-hooks: Fix install script for various git versions\n\nThere are older versions of git-rev-parse that don\u0027t understand the\n`--git-path` switch. Also, when the install script was written, git-\nrev-parse had a bug when it wasn\u0027t run from the root directory. They\nfixed the behaviour by now. To simplify things and not have to account\nfor that too, we just bail out when the script is run from a sub-\ndirectory.\n\nChange-Id: I7ee8d4d54db48f7207fe8abf895c7fbba7685ad2\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22971\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "cbb46e261d5f2837df21e0853c7cd4170d226b40", "tree": "04e07a8adc469d232a07c56fe1d43d867270b551", "parents": [ "8c7e78b9deaa550339940a2efd7bcaef03267751" ], "author": { "name": "nybash", "email": "ny.bash@gmail.com", "time": "Sun Feb 11 17:53:49 2018 -0800" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Wed Feb 21 17:40:03 2018 +0000" }, "message": "flashchips: Add Zettadevice ZD25D40\n\nThis introduces the Zettadevice manufacturer ID and adds support for the\nZD25D40 chip.\n\nBased on PR20 from Github.\nChange-Id: I0400b059ddacdf166d1b77f619becec3a250cece\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/23701\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "8c7e78b9deaa550339940a2efd7bcaef03267751", "tree": "0cc522fdda05d1a5b197c5a05e3e6ee9b0a5d395", "parents": [ "c9ee0ed8a62d5b165a22d536753e960e0158460c" ], "author": { "name": "Leah Rowe", "email": "leah@libreboot.org", "time": "Fri Jan 26 00:57:10 2018 +0000" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Tue Feb 20 01:32:16 2018 +0000" }, "message": "board_enable: Whitelist several ThinkPad laptops\n\nNewly whitelisted laptops include:\n\n* ThinkPad R400\n* ThinkPad T500\n* ThinkPad W500\n* Libiquity Taurinus X200\n\nChange-Id: I772f8e109c56a5fd40f6b1aff0f592b915669c17\nSigned-off-by: Leah Rowe \u003cleah@libreboot.org\u003e\nReviewed-on: https://review.coreboot.org/23781\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "c9ee0ed8a62d5b165a22d536753e960e0158460c", "tree": "eb795574c05b61a4a3f82dbd916c26cc27c256e5", "parents": [ "f701f343117270b4373320eb25ae259b8e513b7d" ], "author": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Feb 11 17:40:53 2018 -0800" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Tue Feb 20 01:09:29 2018 +0000" }, "message": "flashchips: Add Winbond W25P80/16/32 support\n\nThis adds support for W25P80/16/32 chips. Most notably these chips only\nhave two erase commands - one for 64KiB \"sectors\" and one for chip\nerase.\n\nChange-Id: Ie09ba8e28fee35c42e17ca05219dc673413de93b\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/23700\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "f701f343117270b4373320eb25ae259b8e513b7d", "tree": "2749940aec9f2b1dc0ad53069079b78f225d76cf", "parents": [ "3a826043dbd389b4be2f5783c1b984ba297b8179" ], "author": { "name": "Paul Kocialkowski", "email": "contact@paulk.fr", "time": "Mon Jan 15 01:10:36 2018 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 11 16:54:14 2018 +0000" }, "message": "Add support for reading the current flash contents from a file\n\nWhen developing software that has to be flashed to a flash chip to be\nexecuted, it often takes a long time to read the current flash contents\n(for flashrom to know what pages to erase and reprogram) each time\nwhen writing the new image. However, when the flash was just reprogrammed,\nits current state is known to be the previous image that was flashed\n(assuming it was verified).\n\nThus, it makes sense to provide that image as a file for the flash contents\ninstead of wasting valuable time read the whole flash each time.\n\nChange-Id: Idf153b6955f37779ae9bfb228a434ed10c304947\nSigned-off-by: Mike Banon \u003cmikebdp2@gmail.com\u003e\nSigned-off-by: Paul Kocialkowski \u003ccontact@paulk.fr\u003e\nReviewed-on: https://review.coreboot.org/23263\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3a826043dbd389b4be2f5783c1b984ba297b8179", "tree": "c52c86c6821aa657abdd4ac24de7db15559bc57b", "parents": [ "a590f4840b41430a8d2a457eac04e7050584ef48" ], "author": { "name": "Mike Banon", "email": "mikebdp2@gmail.com", "time": "Mon Jan 15 01:09:16 2018 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 11 16:53:47 2018 +0000" }, "message": "edi: Print debug info like others while probing for ENE chips\n\nInstead of just \"Probing for ENE KB9012 (EDI), 128 kB:\", lets print\nsome debug info - like it is currently being printed for other chips:\n\nProbing for ENE KB9012 (EDI), 128 kB: edi_chip_probe: hwversion 0xc3, ediid 0x04\nFound ENE flash chip \"KB9012 (EDI)\" (128 kB, SPI) on ch341a_spi.\n\nChange-Id: Id8e62bc9f6785b4bf0be0aaf0f74c8120d77c0d4\nSigned-off-by: Mike Banon \u003cmikebdp2@gmail.com\u003e\nSigned-off-by: Paul Kocialkowski \u003ccontact@paulk.fr\u003e\nReviewed-on: https://review.coreboot.org/23261\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a590f4840b41430a8d2a457eac04e7050584ef48", "tree": "57ae686e0692e8b4ae28e0e3fdcb453c735a8896", "parents": [ "80ae14e5105bb938679193906d1ee43b7a51c094" ], "author": { "name": "Paul Kocialkowski", "email": "contact@paulk.fr", "time": "Mon Jan 15 01:08:39 2018 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 11 16:53:42 2018 +0000" }, "message": "edi: Add dummy read to ensure proper detection of ENE chips\n\nENE chips enable EDI by detecting a clock frequency between 1 MHz and 8 MHz.\nIn many cases, the chip won\u0027t be able to both detect the clock signal and\nserve the associated request at the same time.\n\nThus, a dummy read has to be added to ensure that EDI is enabled and\noperational starting from the next request.\n\nChange-Id: I69ee71674649cd8ba4fc635f889cb39a1cd204b9\nSigned-off-by: Mike Banon \u003cmikebdp2@gmail.com\u003e\nSigned-off-by: Paul Kocialkowski \u003ccontact@paulk.fr\u003e\nReviewed-on: https://review.coreboot.org/23260\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "80ae14e5105bb938679193906d1ee43b7a51c094", "tree": "629130fad3e6b0b731429bb90dc8e285a91ea8ab", "parents": [ "995f755ff569cbf6ed8d4eec5920b41628aa8ac9" ], "author": { "name": "Paul Kocialkowski", "email": "contact@paulk.fr", "time": "Mon Jan 15 01:07:46 2018 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 11 16:53:34 2018 +0000" }, "message": "Add support for the ENE Embedded Debug Interface EDI and KB9012 EC\n\nThe ENE Embedded Debug Interface (EDI) is a SPI-based interface for\naccessing the memory of ENE embedded controllers.\n\nThe ENE KB9012 EC is an embedded controller found on various laptops\nsuch as the Lenovo G505s. It features a 8051 microcontroller and\nhas 128 KiB of internal storage for program data.\n\nEDI can be accessed on the KB9012 through pins 59-62 (CS-CLK-MOSI-MISO)\nwhen flash direct access is not in use. Some firmwares disable EDI at runtime\nso it might be necessary to ground pin 42 to reset the 8051 microcontroller\nbefore accessing the KB9012 via EDI.\n\nThe example of flashing KB9012 at Lenovo G505S laptop could be found here:\nhttp://dangerousprototypes.com/docs/Flashing_KB9012_with_Bus_Pirate\n\nChange-Id: Ib8b2eb2feeef5c337d725d15ebf994a299897854\nSigned-off-by: Mike Banon \u003cmikebdp2@gmail.com\u003e\nSigned-off-by: Paul Kocialkowski \u003ccontact@paulk.fr\u003e\nReviewed-on: https://review.coreboot.org/23259\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "995f755ff569cbf6ed8d4eec5920b41628aa8ac9", "tree": "8bf525250f29a35eac59e1140da8c039790842cd", "parents": [ "31b5e3bfe6c01180d9a079813ecd199b4808315d" ], "author": { "name": "Paul Kocialkowski", "email": "contact@paulk.fr", "time": "Mon Jan 15 01:06:09 2018 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 11 16:52:48 2018 +0000" }, "message": "Add support for selecting the erased bit value with a flag\n\nMost flash chips are erased to ones and programmed to zeros. However, some\nother chips, such as the ENE KB9012 internal flash, work the opposite way.\n\nChange-Id: Ia7b0de8568e31f9bf263ba0ad6b051e837477b6b\nSigned-off-by: Mike Banon \u003cmikebdp2@gmail.com\u003e\nSigned-off-by: Paul Kocialkowski \u003ccontact@paulk.fr\u003e\nReviewed-on: https://review.coreboot.org/23258\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "31b5e3bfe6c01180d9a079813ecd199b4808315d", "tree": "3acefe04a94524cf9f3fdd47d4136f7c5b137b60", "parents": [ "305a2b3ed36ce87663aea177a806c6f435a4ceec" ], "author": { "name": "Mike Banon", "email": "mikebdp2@gmail.com", "time": "Mon Jan 15 01:10:00 2018 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 11 16:52:30 2018 +0000" }, "message": "Add a SPI command class to `struct flashchip`\n\nBy default, we want to probe for SPI25 chips only. Other SPI use cases,\nlike the ENE/EDI protocol, might use commands that can confuse these\ncommon chips.\n\nNow, flashrom will probe for a chip only if one of these conditions is\ntrue:\n1) no chip has been specified AND the chip uses the SPI25 commands\n2) this chip has been specified by -c | --chip \u003cchipname\u003e\n\nThe CLI can later be extended to probe for a specific class of chips.\n\nChange-Id: I89a53ccaef2791a2ac32904d7ab813da7478a6f0\nSigned-off-by: Mike Banon \u003cmikebdp2@gmail.com\u003e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/23262\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Kocialkowski \u003ccontact@paulk.fr\u003e\n" }, { "commit": "305a2b3ed36ce87663aea177a806c6f435a4ceec", "tree": "a9dcc88821f3f7f8174c5ed1ba851f3522240b62", "parents": [ "2b5adfb1b656dd6a6efbf45a7a411c87840c5394" ], "author": { "name": "Lubomir Rintel", "email": "lkundrak@v3.sk", "time": "Mon Jan 08 05:31:55 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 26 15:27:42 2018 +0000" }, "message": "chipset_enable: Mark VX855 as tested\n\nI can confirm a successful reading and writing of SST49LF080A (LPC) on a\nWyse Cx0 Thin Client (Phoenix BIOS 1.0G).\n\nChange-Id: I8f48b49ccb760f69d676ec6cbb233e532b12fbe8\nSigned-off-by: Lubomir Rintel \u003clkundrak@v3.sk\u003e\nReviewed-on: https://review.coreboot.org/23158\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "2b5adfb1b656dd6a6efbf45a7a411c87840c5394", "tree": "cfc4bf09d45d4ad59b645c0cadaec9507ba5c152", "parents": [ "25fde40f8594b1c13ba7a4c3a605b96b200a4e11" ], "author": { "name": "Shawn Anastasio", "email": "shawnanastasio@yahoo.com", "time": "Sun Dec 31 00:17:15 2017 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 26 15:23:10 2018 +0000" }, "message": "buspirate_spi: Add support for variable serial speeds\n\nThis patch sets the default baud rate for communication between\nthe host device and the Bus Pirate for hardware versions 3.0\nand greater to 2M baud.\n\nIt also introduces the ability to manually set the baud rate via\nthe added \u0027serialspeed\u0027 programmer parameter.\n\nThis is done in two parts. Firstly, the requested serial speed is looked up\nin a table to determine the appropriate clock divisor and the divisor is sent\nto the bus pirate. Then, the system\u0027s baud rate for the selected serial port\nis set using serial.c\u0027s \u0027serialport_config\u0027. This function\u0027s prototype had to\nbe added to programmer.h.\n\nIn testing, using the 2M baud rate was able to significantly decrease\nflash times (down from 20+ minutes to less than 2 minutes for an 8MB flash).\n\nChange-Id: I3706f17a94fdf056063f2ad4a5f0a219665cdcbf\nSigned-off-by: Shawn Anastasio \u003cshawnanastasio@yahoo.com\u003e\nReviewed-on: https://review.coreboot.org/23057\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "25fde40f8594b1c13ba7a4c3a605b96b200a4e11", "tree": "8e19343934bcd9be2503441b556ccf4e0871fed2", "parents": [ "73c882086fe7d6fac9859e2faa93ec56cc96b9bd" ], "author": { "name": "Rudolf Marek", "email": "r.marek@assembler.cz", "time": "Fri Dec 29 16:30:49 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jan 06 22:38:58 2018 +0000" }, "message": "Fix the documentation and DOS port\n\nUpdate the DOS cross-compile documentation,\nand workaround issue with valloc() with the\nlatest DJGPP.\n\nChange-Id: I909c5635aec5076440d2fde73d943f8ad10b8051\nSigned-off-by: Rudolf Marek \u003cr.marek@assembler.cz\u003e\nReviewed-on: https://review.coreboot.org/23039\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "73c882086fe7d6fac9859e2faa93ec56cc96b9bd", "tree": "b6f32ecc6126de577c687718c9810f5c1bfbd132", "parents": [ "d0803c8407c459e972cb9912a4a3cbfeebb93d9e" ], "author": { "name": "Lubomir Rintel", "email": "lkundrak@v3.sk", "time": "Thu Dec 28 20:19:21 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jan 02 20:15:56 2018 +0000" }, "message": "chipset_enable: Mark VX900 as tested\n\nI can confirm a successful reading and writing of MX25L8005 (SPI) on a HP t5550\nThin Client (AMI BIOS 786R9 v1.04).\n\nChange-Id: I190253b0c1920747b710ed7155e78191cce139eb\nSigned-off-by: Lubomir Rintel \u003clkundrak@v3.sk\u003e\nReviewed-on: https://review.coreboot.org/23030\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d0803c8407c459e972cb9912a4a3cbfeebb93d9e", "tree": "7c361a17c153b09bf9da9ea685e29b4648118218", "parents": [ "aac81424ebb8234b54cbab8fe47350b562b84fae" ], "author": { "name": "Lubomir Rintel", "email": "lkundrak@v3.sk", "time": "Mon Oct 30 07:57:53 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jan 02 20:15:45 2018 +0000" }, "message": "vt_vx: check whether the chipset\u0027s MMIO range is configured\n\nAvoid attempting to read the SPI bases from the location 0x00000000, all\nzeroes mean that the chipset\u0027s MMIO area is not enabled.\n\nChange-Id: I5d3a1ba695153e854e0979ae634f8ed97e6b6293\nSigned-off-by: Lubomir Rintel \u003clkundrak@v3.sk\u003e\nReviewed-on: https://review.coreboot.org/23029\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "aac81424ebb8234b54cbab8fe47350b562b84fae", "tree": "2806be52075a5a3a46c5e7be2ccdb6d69b6e1a0f", "parents": [ "fe34d2af28bd81aaa1e23ba38febaa98ec4bb90c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 10 22:54:13 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jan 02 20:15:35 2018 +0000" }, "message": "flashchips: Revise all 4BA chips\n\nAdvertise all 4BA features that are currently supported by flashrom,\nplus add a new feature flag for the 4BA fast-read instruction. Also,\nlist all supported 3BA and 4BA erase-block functions.\n\nAs this adds a lot of new code paths that could be taken for these\nchips, mark them all as untested again.\n\nChange-Id: I0598496ee7058e3b170684d366f58e4014e0e871\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22423\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "fe34d2af28bd81aaa1e23ba38febaa98ec4bb90c", "tree": "53bda4d3445a94505455ffb12a96da602ba97af6", "parents": [ "1cf407b4f8d56035816efaf936a40553441eca46" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 10 21:10:20 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jan 02 20:15:30 2018 +0000" }, "message": "spi25: Revise decision when to enter/exit 4BA mode\n\nInstead of arbitrarily deciding whether to enter 4BA mode in the flash\nchip\u0027s declaration, advertise that entering 4BA mode is supported and\nonly enter it if the SPI master supports 4-byte addresses. If not, exit\n4BA mode (the chip might be in 4BA mode after reset). If we can\u0027t assure\nthe state of 4BA mode, we bail out to simplify the code (we\u0027d have to\nensure that we don\u0027t run any instructions that can usually be switched\nto 4BA mode otherwise).\n\nTwo new feature flags are introduced:\n\n* FEATURE_4BA_ENTER:\n Can enter/exit 4BA mode with instructions 0xb7/0xe9 w/o WREN.\n* FEATURE_4BA_ENTER_WREN\n Can enter/exit 4BA mode with instructions 0xb7/0xe9 after WREN.\n\nFEATURE_4BA_SUPPORT is dropped, it\u0027s completely implicit now.\n\nAlso, draw the with/without WREN distinction into the enter/exit\nfunctions to reduce code redundancy.\n\nChange-Id: I877fe817f801fc54bd0ee2ce4e3ead324cbb3673\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22422\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "1cf407b4f8d56035816efaf936a40553441eca46", "tree": "c8e41e1172aaeb567af161a9763521c53073bdc4", "parents": [ "ed098d62d66d91cf7330a37f9b83e303eb7f56d8" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 10 20:18:23 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jan 02 20:14:34 2018 +0000" }, "message": "spi_master: Introduce SPI_MASTER_4BA feature flag\n\nAdd a feature flag SPI_MASTER_4BA to `struct spi_master` that advertises\nprogrammer-side support for 4-byte addresses in generic commands (and\nread/write commands if the master uses the default implementations). Set\nit for all masters that handle commands address-agnostic.\n\nDon\u0027t prefer native 4BA instructions if the master doesn\u0027t support them.\n\nChange-Id: Ife66e3fc49b9716f9c99cad957095b528135ec2c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22421\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "ed098d62d66d91cf7330a37f9b83e303eb7f56d8", "tree": "639b6233e588fd8b4150b42112da36e239ba7fa4", "parents": [ "7e3c81ae7122120fe10d43fcba61a513e2461de9" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Apr 21 23:47:08 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:49:05 2017 +0000" }, "message": "spi: Move ICH BBAR quirk out of the way\n\nGet rid of the layering violations around ICH\u0027s BBAR. Move all the weird\naddress handling into (surprise, surprise) `ichspi.c`. Might fix writes\nfor the `BBAR !\u003d 0` case by accident.\n\nBackground: Some ICHs have a BBAR (BIOS Base Address Configuration\nRegister) that, if set, limits the valid address range to [BBAR, 2^24).\nCurrent code lifted addresses for REMS, RES and READ operations by BBAR,\nnow we do it for all addresses in ichspi. Special care has to be taken\nif the BBAR is not aligned by the flash chip\u0027s size. In this case, the\nlower part of the chip (from BBAR aligned down, up to BBAR) is inacces-\nsible (this seems to be the original intend behind BBAR) and has to be\nleft out in the address offset calculation.\n\nChange-Id: Icbac513c5339e8aff624870252133284ef85ab73\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22396\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7e3c81ae7122120fe10d43fcba61a513e2461de9", "tree": "f505342cd2879b9cc77c2cbf66dda0231869ee9c", "parents": [ "0ee2dc06839d2f4f3197dd0ef51202e51e945bea" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 18:56:50 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:48:28 2017 +0000" }, "message": "spi25: Merge remainder of spi4ba in\n\nChange-Id: If581e24347e45cbb27002ea99ffd70e334c110cf\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22388\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0ee2dc06839d2f4f3197dd0ef51202e51e945bea", "tree": "6eb5e8b7e9f16767ed5b63ea909ecb5b7001414c", "parents": [ "7a077222566c84546dca4a56c1a509626036e429" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 18:27:13 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:47:05 2017 +0000" }, "message": "spi4ba: Drop now obsolete, redundant functions\n\nChange-Id: I1d04448fd1acbfc37b8e17288f497a4292dfd6d6\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22387\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7a077222566c84546dca4a56c1a509626036e429", "tree": "b4cd487275dd4ffc92ad6ac885268842efbe9eb3", "parents": [ "a1672f829328e877d9b8dea7777f25e2eba52d0e" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 18:18:30 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:46:54 2017 +0000" }, "message": "spi25: Remove now obsolete `four_bytes_addr_funcs` path\n\nChange-Id: Idb7c576cb159630da2268813388b497cb5f46b43\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22386\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a1672f829328e877d9b8dea7777f25e2eba52d0e", "tree": "8f90cab7e18bc875241ff66eef153b80e7c4a71b", "parents": [ "f43c654ad0dcb11b2738bbfac9246d09bb1949e5" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 18:00:20 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:45:46 2017 +0000" }, "message": "spi25: Enable native 4BA read and write using feature bits\n\nPrefer the native 4BA instruction when they are supported. In this\ncase, override our logic to decide to use a 4BA address.\n\nChange-Id: I2f6817ca198bf923671a7aa67e956e5477d71848\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22385\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" } ], "next": "f43c654ad0dcb11b2738bbfac9246d09bb1949e5" }