)]}' { "log": [ { "commit": "edf174f0c456ab5d6da1d8bff7e6b9ad719ee532", "tree": "f091dd3f382d18102fde06f436a5e6e797b1df75", "parents": [ "c3eaa9525d474faee3109bfc280c7b6cd2fc579d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 07 23:32:30 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 28 09:29:37 2026 +0000" }, "message": "flashchips: Remove .probe\n\nThere\u0027s only probe_buses() left. We can even bypass it\nby calling chip_on_bus() directly.\n\nChange-Id: I3bca7ad6f264f3b1a4ad887a941605525e432291\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/451\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "f1411ba8b9a7b7961c59c293e79be1a2feeede95", "tree": "7fb4fbc87b9a4264b4c7cecc39a026d4fd9449bb", "parents": [ "3a3533716c10bd9aa5fd7960a916292503bcf3fa" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 08 15:37:37 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 28 09:29:37 2026 +0000" }, "message": "Join PREPARE_PROBE/_POST_PROBE steps\n\nNow that all the probing procedures handle flash mapping by them-\nselves, there\u0027s nothing to be prepared before probing anymore. We\nwill, however, map the flash after probing for later register ac-\ncess (e.g. printlock()).\n\nChange-Id: I23833aaba9402858ab14b8835b747b0c27b2278b\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/447\n" }, { "commit": "dae9022046be147c87c32d56678053b2f85cdb1a", "tree": "2b4551057e1e770283b71b180b29738a49215bc1", "parents": [ "2ae63016844097ae1046c861e88b4d8bfb0ff43e" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Mar 09 20:36:56 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 28 09:29:37 2026 +0000" }, "message": "probing: Pass full struct flashchip into probes\n\nIn case we want to probe for a particular chip, we can filter the\nactual probing sequences by its properties.\n\nWe\u0027ll use `struct flashchip` internally and `struct flashprog_chip`\nwill be used only close to the libflashprog API. This way, we can\nseparate the two later again if necessary.\n\nChange-Id: Id8b13d28fcaefee62746c9391fe86b4b3b09a428\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/441\n" }, { "commit": "2ae63016844097ae1046c861e88b4d8bfb0ff43e", "tree": "522d3b5599e7ea9142f08ac3cc29c931498f7a2d", "parents": [ "3d6bd5a35f94d06837e2ec6533eb3179a44bda11" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Mar 04 21:06:45 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 28 09:29:37 2026 +0000" }, "message": "memory_bus: Add infrastructure for per-bus probing\n\nAll the probing functions for the traditional memory-mapped chips,\nparallel, LPC and FWH, are parameterized by additional chip proper-\nties like the chip size and feature bits like FEATURE_ADDR_SHIFTED.\nHence, we match against an extended `id_info\u0027 with chip size and\nfeature bits. For a match, all the feature bits assumed during\nprobing, need to be set for a given chip as well.\n\nChange-Id: Id5c3d8933cd6aeaf87a090b6f0798d2a5746ee17\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/440\n" }, { "commit": "84914db6304ccd0f6f41ba7b4f6c0a83ef66e5d0", "tree": "3aa266ba80786f3927d253e1d8ef9334c3b7c632", "parents": [ "4374ba1e696c9f0d18ee86188f0a389634fd2c94" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 07 17:11:28 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 28 09:29:37 2026 +0000" }, "message": "Make FEATURE_LONG_RESET a proper feature bit\n\nThis will make it possible to see at runtime if a chip\nactually supports both reset methods.\n\nChange-Id: Id5fb5af743215435dfc289105bdfcc5fd739eabb\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/435\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "be42cf24728907ace7db5c572b097288485dca5c", "tree": "deeeaebe268b862f7fa21e2d044bafb6499f406f", "parents": [ "006d08d64ba33d5400dc87e458727df615c381ef" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Feb 21 17:40:44 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 28 09:29:37 2026 +0000" }, "message": "Make flash-size limiting of atapromise a general --force feature\n\nTo allow accessing at least part of flash chips behind this size-limited\ncontroller, the `atapromise\u0027 driver used a local function that adjusted\na chip description. As flashprog would have bailed out earlier already,\nthis was only ever usable with the `--force\u0027 flag.\n\nThe same adjustment can be used with other programmers. Making it a glo-\nbal feature also gets rid of a driver peculiarity and removes the depen-\ndency on `flashctx` in the `atapromise\u0027 driver.\n\nThe logic enforces a complete chip erase if any erase is necessary. So,\nwhile this should make part of the chip fully read/writable, content of\nthe inaccessible area will be lost on write.\n\nChange-Id: I6bce8ff7781f683b001f76154621f22bd03687bc\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/431\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "fbc41d2a932ede9c02aa7803472c31f39ec200f2", "tree": "8b72b78abfd99bf8737b90cc2fece11f2dbe93d3", "parents": [ "966dc9b776c2897d1245937639ab41fc834d7cb9" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 22 23:04:01 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 22 09:47:02 2026 +0000" }, "message": "spi: Move SPI related things into new chipdrivers/spi.h\n\nA few things that rely heavily on `flash.h` are moved there instead:\n* function signatures containing `erasefunc_t`,\n* the inline default_wrsr_target() that needs to know struct flashctx.\n\nThis allows to keep the new header file free of a transitive `flash.h`\ninclude.\n\nChange-Id: Ib215821feeb822ea3fc11bf9f48c0328f9a394d4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/416\n" }, { "commit": "af9d738a66a885f19fdb0659455834f114d9d1e0", "tree": "e3596a537af16f3d9a0aee3dbe7bfc668fc5ce34", "parents": [ "0069440fb0905b7ff3bf5184ffae34673be2e35d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon May 01 13:33:26 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 22 09:47:02 2026 +0000" }, "message": "Add infrastructure to probe per bus\n\nAdd some infrastructure around per-bus probing functions. Each function\nis provided a private parameter, e.g. the expected length of an ID. This\nwill allow us to implement probing functions that are only called as of-\nten as necessary. The results will be stored in the `registered_master`\nstructure, to be compared to database entries later.\n\nThe probe_buses() wrapper can be used for chip entries, and allows us to\ntransition the existing probing functions one by one. Once all functions\nhave been ported, probe_flash() can be adapted as well and the wrapper\nwill become obsolete.\n\nChange-Id: I6e82b6d61df50234096ac39acab58a4014203933\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74899\n" }, { "commit": "11136c210e382258a72df44ffe625260a6394a45", "tree": "376f66e9e7a826dcf13f833e90291db7663205a4", "parents": [ "610c1aad71bfa118c4f49ac01761f586b8dede69" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon May 01 12:00:09 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 15 14:27:20 2026 +0000" }, "message": "flashchips: Add a type enum to the chip identification\n\nWe used to imply what kind of ID (e.g. RES, REMS, RDID) a chip entry\nprovides, based on the given probing function. This works well as long\nas we call the respective probing function for every single chip entry.\nWith our ever growing chip database, however, this slows probing signi-\nficantly down. Especially with external programmers with a long command\nround-trip.\n\nWith the type of identification information stored in the chip entries\nexplicitly, we\u0027ll be able to implement bus-specific probing functions.\nThese would be called only once and their results would be used to look\na matching chip up in the chip database. Instead of looking for every\npossible chip on the buses, we can turn it around and search for the\nactually present chips in the database.\n\nChange-Id: Ie658ebf58f21c8994b9b66f7683f9490e8d12267\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74898\n" }, { "commit": "5469c15550be12b4da9d2fbf48f16137895e07ba", "tree": "d3a0fbf038e01141a02a3b49a19be4fc3ee92136", "parents": [ "89e6818a8e60e6e2ddc7d09da0e79b615ea36629" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Feb 12 22:56:52 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 15 14:27:20 2026 +0000" }, "message": "Add common master API to adapt voltage\n\nWe start by setting the voltage in prepare_flash_access() and, if we\nwere told to probe for a specific chip, before the probing. For now,\nwe leave the programmer driver\u0027s default voltage during the probing,\notherwise.\n\nOnce the probing is more bus centric, we can implement a more elabo-\nrate scheme. For instance, we can probe at the lowest voltage first\nand only increase it if there was no response at all.\n\nChange-Id: I6689813f83abe654ba7a18f2e0537314047bf15f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/414\n" }, { "commit": "b89c4524d978d3104ce3346894503e8d7b3fce51", "tree": "7ca1917a0b9dc17d0707ec40c57fae4f51136204", "parents": [ "db90cf7a9da5b0acc04952865c5c1bbc09ccd38d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Dec 04 23:30:13 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Feb 14 22:42:55 2026 +0000" }, "message": "Add new flash-chip preparation step after probing\n\nChange-Id: I57fd63ddc4c8ccd07b0744df33d6a499bfeae9ff\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/321\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "32fa50845240a8ba3ed9dfa4e860d799cdd768b7", "tree": "35fe5f8e28389fb0060ddff00c10c31e51066614", "parents": [ "82834c95ef1d16519d0f114692bfb4cd5e47c461" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jan 26 18:26:49 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Feb 09 20:38:18 2026 +0000" }, "message": "Extract chip selfcheck into new selfcheck_chip() function\n\nWe\u0027re going to call it from the SFDP parser, too.\n\nChange-Id: Ib526d005b84717d4be69cc2dff46cf628af4c9cd\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/392\n" }, { "commit": "4e6155afd4b0e1f5cf190cdd21fa83a656c4088a", "tree": "395a5592506087f34ec696887eb965ec335f8b5d", "parents": [ "9512c9c16c73e46b6190c9c9fd9ea0555a4d7e24" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 02 23:05:09 2025 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 17:23:14 2025 +0000" }, "message": "spi25: Add SPI25_EEPROM enum and handle \u003c 3-byte addresses\n\nChange-Id: I043f6ea987a07853b8c50e34b3cd63faf995ecbc\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/314\n" }, { "commit": "46e42096032e85265b0740b47c86f4975cf365ef", "tree": "c4d77e4da37ec5b45fc3aafdff84c5c5a76c8095", "parents": [ "6bc88e72d97a140cf657571a2f4a4f3e1c643954" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 20 18:21:43 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Add XTX Tech. XT25F02E/04D/08B 3.3V parts\n\nThese are old chips with rather limited capabilities. Their\nblock-protection ranges are rather special, hence not added\nat the moment.\n\nDatasheets used:\nhttps://en.xtxtech.com/download/?AId\u003d118\nhttps://en.xtxtech.com/download/?AId\u003d136\nhttps://en.xtxtech.com/download/?AId\u003d51\n\nChange-Id: I28ec5087be63b394b0f387ca01e2391823680272\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/283\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "b82aadcbbf173fcaf6c93c7d8cc664bf33b0dd21", "tree": "f2038c52d252f78ee97adaf56d614b10eb92884f", "parents": [ "a705043179ab641794f497c2ebf6a60d7f3d9b3e" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Feb 11 18:27:30 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 03 17:54:48 2024 +0000" }, "message": "cli: Move some declarations into `cli.h`\n\nThis will help to keep new CLIs clean from internal headers.\n\nChange-Id: I3e5515ae5645fcdce56c13df1ff23de829bbbdb9\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72989\n" }, { "commit": "55e788491607997ca93c86e58a38f2ac5dc73afe", "tree": "90be6d93bedff5fc983054de1e474d31aff6f559", "parents": [ "fbba4545dd9ec5ea7f3416370d6b71ccc85e3f7e" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 21 00:46:19 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 03 17:54:48 2024 +0000" }, "message": "Introduce FLASHPROG_FLAG_NON_VOLATILE_WRSR\n\nAdd a new flag to our flash context that tells us if we should use\nvolatile or non-volatile status-register writes by default. Use it\nin the write-protection API. The logic to disable block protection\nautomatically stays as is for now, until we have established tools\nto manually control the protection.\n\nChange-Id: Ie9a41b6404991075e2bf76bcffbd4e9887c62c79\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/193\n" }, { "commit": "2862011212da1745e4238381bfe16f0dab3fd7c1", "tree": "c650132ba159d9fa5693afd667768f86956645e4", "parents": [ "4ac536bde43a1d64e11034cab34aabd7a6efd5dc" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 21 15:43:59 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "spi25: Try to set volatile quad-enable (QE) automatically\n\nSome chips have a volatile QE bit. Setting this won\u0027t wear the status/\nconfiguration register, so we\u0027ll try to do so automatically.\n\nChange-Id: I6a4b864d7af1f3ecedd95524f127b5486f999933\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/191\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "1b1deda80bbd7f56b8047fad32badb749eeefffb", "tree": "e7058d9d175d08ed2542f6e34be0842a7ade8f57", "parents": [ "a1b7f3521f66a19a2d4c9a6a373c5a7ab36e1473" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Apr 18 00:35:48 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "Implement QPI support\n\nWith the quad-i/o support in place, this is actually straight-\nforward:\n* we check for compatibility of the flash chip and programmer,\n* select an appropriate fast-read function, and\n* always set the respective io-mode when passing a SPI command\n to the programmer.\n\nTested with FT4222H + W25Q128FV and linux_gpio_spi + MX25L25645G.\n\nChange-Id: I2287034f6818f24f892d66d1a505cb719838f75d\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/165\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "4760b6ec1f7fbcee1bf238a25e3df56a86327a5a", "tree": "a4c3762b1228f901f62d40b53ed1a953b25926b4", "parents": [ "0c9af0a639bf9180839d548f91547b58de921ca9" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jan 06 23:45:28 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "spi25: Implement multi-i/o reads\n\nWe describe a read operation in a new `struct spi_read_op`. It\u0027s\ncomprised of the i/o mode, its opcode, an optional mode byte, and\nthe number of dummy bytes.\n\nBased on this information about the various read operations, and\nthe flash and master feature flags, we select the read operation\nwith the highest throughput.\n\nThe following assumption is made about 4BA chips: When it supports\nnative-4BA fast reads and a multi-i/o version of the regular fast\nread, then it should also support the respective native-4BA, multi-\ni/o version (yes, JEDEC, there are too many read commands!). So far\nthis seems to hold for the chips in our database.\n\nChange-Id: I3c93e71d85f769831d637c14d3571f7ddb54d8b2\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/49\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "930d421385aae5ca93d5963fba7926970d7702e8", "tree": "199e15c17260fabb8e422075230621a21e064531", "parents": [ "8d0f4650c73eb7bcda0b71e514c0effdf37d90b5" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat May 04 18:59:15 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "spi25: Introduce generic spi_prepare_io()/spi_finish_io()\n\nIntroduce two new functions to be hooked up in the chip database:\n* spi_prepare_io(), and\n* spi_finish_io().\n\nThese will be used to prepare multi-i/o and QPI operations. Hence,\nhook them up to all the chips that support those. spi_prepare_4ba()\nis wrapped to account for overlaps with 4BA support.\n\nChange-Id: I444f6322b6d6a26a040cb0ca972b2c411838d702\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/163\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "f7e2d9739b8ccbc841081337c1d7c46407b5f0cf", "tree": "0bd800c641b7930e096e74408e292df2017a51b1", "parents": [ "1412d9f435ead84d612086bf0051a4c3464bd079" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 18 20:28:34 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "spi: Allow to define a quad-enable (QE) configuration bit\n\nChange-Id: Ia6c927aeaab8de6e81313e285351ba14b3c6aa25\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/111\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "1412d9f435ead84d612086bf0051a4c3464bd079", "tree": "7d1e2050d97f8e12b280d267fac9a49dbab7939e", "parents": [ "d518563f197241cc72f5da4b2108b2df10f00372" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jan 06 18:25:49 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "spi: Rework FEATURE_QPI\n\nAlas, a single feature flag is not enough. QPI requires enter/exit\ncommands and there are at least two competing sets of opcodes. More-\nover, the current flag was sometimes accidentally used for chips\nthat can only do quad-i/o for address/data phases but not full QPI.\n\nSo, add a lot of new flags and go through all the entries that have\ncurrently FEATURE_QPI set. Additionally, note the amount of dummy\ncycles required by read commands in QPI mode, and whether and how\nthese can be configured.\n\nChange-Id: Id7310af07b2fdbedb7b051e9395ea967cb345d16\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/45\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "d518563f197241cc72f5da4b2108b2df10f00372", "tree": "8ec807be43adf3b5c9f66a2701b7bf0ea3a4a11f", "parents": [ "bd72a470b9b58386b52ca4568313be71b4d2c472" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 05 18:44:41 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "spi: Prepare for multi i/o and dummy bytes\n\nMulti-i/o commands split SPI transactions into multiple phases that\ncan be transferred over 1, 2 or 4 wires. For this, we adapt `struct\nspi_command` with a new enum, specifying the transfer mode, and ad-\nditional size fields. While we are at it, move everything related\ninto a new header file `spi_command.h` so we won\u0027t further clutter\n`flash.h`.\n\nOn the master side, we add respective feature flags for the multi-\ni/o modes.\n\nSee also the comment in `spi_command.h` about multi-i/o commands.\n\nChange-Id: I79debb845f1c8fec77e0556853ffb01735e73ab8\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/44\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "bd72a470b9b58386b52ca4568313be71b4d2c472", "tree": "078afe70db3836ef41b37ce2c64fb6de67c38747", "parents": [ "3d728e7524fe086e90779ea76bf2f9bd02cdf6de" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Sun Jul 24 17:11:05 2022 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "spi25_statusreg: support reading/writing configuration register\n\nOne more variation of registers.\n\nThis one is read via a separate RDCR command, but written as if it\u0027s\nSR2 using WRSR_EXT2.\n\nPorted to flashprog w/o the FEATURE_CFGR flag, we\u0027ll already have that\ninformation in the register description.\n\nChange-Id: I45f9afcc31f1928ef6263a749596380082963de4\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOrignal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66211\nOrignal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOrignal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/71007\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "3d728e7524fe086e90779ea76bf2f9bd02cdf6de", "tree": "74d3bec50d87ac2fc45c1c2beaf5d780e6acda4a", "parents": [ "a358b14d2e7e93e317499a687223ada2d221a36a" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Sat Nov 27 15:14:27 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "spi25_statusreg.c: support reading security register\n\nNot to be confused with \"secure registers\" of OTP.\n\nSecurity register is a dedicated status register for security-related\nbits. You don\u0027t write its value directly, issuing special write commands\nwith no data set separate OTP bits to 1 automatically (WRSCUR, WPSEL\ncommands). No WREN is necessary, but at least some datasheets indicate\nBUSY state after those write commands.\n\nUnlike cases where OTP bit is part of SR and can only be written while\nin OTP mode, security register can only be written outside of the mode.\n\nThe register is found in at least these chips by Macronix:\n * MX25L6436E\n * MX25L6445E\n * MX25L6465E\n * MX25L6473E\n\nPorted to flashprog w/o the FEATURE_SCUR flag, we\u0027ll already have that\ninformation in the register description.\n\nChange-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59709\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/71006\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "7679b5ccf987e4999fefed6c6100a7a8f50d4350", "tree": "d904cf0a8e68feb831380054ce5956cb3b96fdca", "parents": [ "ca1c7fdd6bd6f61029492fb7a194bd47119e465f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Apr 28 21:48:53 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Mar 27 08:32:15 2024 +0000" }, "message": "spi25: Replace spi_read_chunked() with more abstract version\n\nThe new flashprog_read_chunked() takes a low-level reading function as\nargument. This allows us to make use of the chunking with non-SPI read\nfunctions.\n\nChange-Id: Ica1b616e75e4e7682120928588e231c82cf4cf70\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74865\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "842d678f07439e133e69fc775a848dcd66369446", "tree": "c01716fbc4220c1211749772d6a566e6d70701d7", "parents": [ "aa714dd3dd7090e1fa7175f3a32a252b04817261" ], "author": { "name": "Richard Hughes", "email": "richard@hughsie.com", "time": "Fri Jan 15 09:48:12 2021 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Mar 27 08:32:15 2024 +0000" }, "message": "libflashrom: Return progress state to the library user\n\nProjects using libflashrom like fwupd expect the user to wait for the\noperation to complete. To avoid the user thinking the process has\n\"hung\" or \"got stuck\" report back the progress complete of the erase,\nwrite and read operations.\n\nAdd a new --progress flag to the CLI to report progress of operations.\n\nInclude a test for the dummy spi25 device.\n\nTested: ./test_build.sh; ./flashrom -p lspcon_i2c_spi:bus\u003d7 -r /dev/null --progress\n\nflashrom-stable:\n* Closer to original libflashrom API.\n* Split update_progress() into progress_start/_set/_add/_finish:\n Simplifies progress calls scattered through the code base. We let\n the core code in `flashprog.c` handle the total progress. Only API\n is flashprog_progress_add(). Erase progress is completely handled\n in `flashprog.c`. Fine grained read/write progress can be reported\n at the chip/programmer level.\n* Add calls to all chip read/write paths and opaque programmers\n except for read_memmapped() (which is handled in follow ups).\n* At least one wrinkle left: Erasing unaligned regions will slightly\n overshoot total progress.\n\nChange-Id: I7197572bb7f19e3bdb2bde855d70a0f50fd3854c\nSigned-off-by: Richard Hughes \u003crichard@hughsie.com\u003e\nSigned-off-by: Daniel Campello \u003ccampello@chromium.org\u003e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/49643\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74731\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "9a11cbf21a5078bcdb8db7584c44a9ee17020db4", "tree": "e67a9eadfdb7a71f81df36c7e97180474a8c59df", "parents": [ "aabb3e0ff54e87c0136c91f105e506ed19184cc6" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 13 01:19:07 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:40:04 2024 +0000" }, "message": "Let the flash context directly point to the used master\n\nWe used to have a pointer to a full `registered_master` struct in\nour flash context. Beside the used master, this contained a bit\nmask of supported buses. Oddly convenient, this bit mask invited\nto bypass the chip driver and break the abstraction. It allowed\nto place bus-specific details virtually anywhere in flashprog,\nmaking it harder to find a good place for them.\n\nSo, get rid of the `buses_supported` bit mask by pointing directly\nto the master. Only the chip driver will implicitly know which type\nof master is used.\n\nChange-Id: I9ce13d8df0e7ccc67519d888dd9cb2e2ff8d6682\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72533\n" }, { "commit": "aabb3e0ff54e87c0136c91f105e506ed19184cc6", "tree": "d53c2df274e9550b1f251a94b80add2d7285c5c4", "parents": [ "89569d60e3aeeec651496b2e7a2e6064d782ab3b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 13 00:22:30 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "writeprotect: Hook wp functions into the chip driver\n\nChange-Id: I17a06210ec329aba337cf459d581463827182108\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72532\n" }, { "commit": "b197402042a065554234700b69057e9b6eedc39a", "tree": "62e4b15dff887d157ad18dd09b3d47dd2d7f8c1a", "parents": [ "0e76d99a7c0eda11515923c5457f0b5a4af9893f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 12 13:13:12 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "memory_bus: Split register mapping into own function\n\nNow that we have a hook for the memory mapping, we don\u0027t need\nFEATURE_REGISTERMAP anymore and can clean up around it.\n\nChange-Id: If11ece9ce81ddf214b75764007a1006d271dc8af\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72523\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "0e76d99a7c0eda11515923c5457f0b5a4af9893f", "tree": "c914d5266909dad441bece2705593131f032c19c", "parents": [ "9eec40780207a110f3ba7ea70d11c042c6d86abf" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 12 20:22:55 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "memory_bus: Move (un)map_flash_region into par master\n\nNow that the map/unmap_flash functions are only called from memory-\nmapped chip drivers, we can safely move the hooks into the parallel\nmasters.\n\nThis also allows us to move the code away from the globals in\n`flashprog.c` into a new `memory_bus.c`.\n\nChange-Id: Ic476cf4d96200232900537b997e1d07bb4e8b809\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72522\nReviewed-by: Riku Viitanen \u003criku.viitanen@protonmail.com\u003e\n" }, { "commit": "9eec40780207a110f3ba7ea70d11c042c6d86abf", "tree": "f48e0860e967bd720901e9cf12faaa82363bf2c8", "parents": [ "56b53dd4c892c6f400f6b05797eb6ed4b96179db" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 12 01:17:30 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "Perform default mapping only for respective chips\n\nThe default memory mapping for the whole flash chip only makes sense\nfor chips that are directly connected to a bus serving memory cycles,\ni.e. parallel, LPC and FWH chips. Use the new `.prepare_access` and\n`.finish_access` hooks to map/unmap respective chips.\n\nGoing through the chip driver for this allows us to free the core\nflashprog code from this peculiarity.\n\nChange-Id: I54d1554b44b7e21fc18ef066103a9a26a2783b36\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72521\n" }, { "commit": "901fb957742edef9307948c397bdd28c8b5ebfac", "tree": "c69fc13d64764e08ce22df9a08772cb4eb9cde20", "parents": [ "a96aaa3c716e13c62e1a7d93b5e6580e817cd2f5" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jan 11 23:24:23 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "Add prepare/finish_access() hooks for chip drivers\n\nSome of the arrangements we perform in prepare_flash_access()\nare actually specific to the flash chip. Allow to clean that\nup by adding respective hooks into `struct flashchip`.\n\nChange-Id: Iff79ba3d190dba04ecf58c5c53faa428bf592bdf\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72516\n" }, { "commit": "5455786bfb4b09af11f4354a6bb4842d37d78419", "tree": "4444295adb9d0e6f9e13e08a16bc5c88a0b14352", "parents": [ "c3b02dce51aad2766512d1939a1b7447c2d526b8" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon May 15 12:01:04 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 08 19:56:50 2023 +0000" }, "message": "spi95: Avoid automatic probing\n\nIt turned out that the read ID command for the ST/M95 family (0x83)\nis a write command for AT45DB chips. We\u0027ll tag respective chips as\nusing a SPI95 command set, like we did for EDI, to avoid automatic\nprobing.\n\nChange-Id: Ibdf364424ac9cd8a734507a05fe769f008f8178e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/75218\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "c3b02dce51aad2766512d1939a1b7447c2d526b8", "tree": "58069f464bb8a777ef06e93767813a4c5a042cb0", "parents": [ "a02df33fbf1c196395a61049e60895d4ae0e0a5b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Aug 12 01:13:45 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Sep 18 19:24:39 2023 +0000" }, "message": "Rebrand to flashprog and update URLs\n\nMostly automated `sed` work. As of now, URLs to the old wiki are broken\neither way, so changing them shouldn\u0027t hurt. Other URLs (e.g. to mailing\nlist archives) were hopefully filtered correctly.\n\nChange-Id: I9d43bfd0e675eff2fcbad05f304b9ce9f5006b08\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashrom-stable/+/21\n" }, { "commit": "3ac761c3c47a6476b8b0f9ce613b32914b163c46", "tree": "146db2e06439bf76f4c66fd48facb10ec3c0bf79", "parents": [ "b77607f048e5cdfbf8fb1e9ad3b110c9a67e80e0" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jan 16 02:43:17 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 04 10:12:02 2023 +0000" }, "message": "layout: Verify that regions to be written are granularity aligned\n\nThis will be important with the new erase/write strategy when we don\u0027t\nwrite per erase block anymore.\n\nChange-Id: Ie3c74ff4313c9d72ac92d3226804e0407088c17d\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72546\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3b64d8107b56dc437cde606e17abaae435d7ba35", "tree": "3971e382111e87d2dc6d00e38e4198d78ec46eb7", "parents": [ "23b2b864777a09b4d9a9024675670a7d694c1e06" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Fri Aug 12 13:07:51 2022 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "flashrom.c: Move print logic to print.c\n\nThis free\u0027s up flashrom.c from namespace pollution.\n\nChange-Id: I2724f7910fa3e01bcf49b8093260a4f1643df777\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66652\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72351\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "63f6a37984cf361229b433343ea9146c57a87f18", "tree": "0ebdaca6bbf8168b6bbb93da3b3be9dcc0336fe3", "parents": [ "ee3fbd7c7c05efbdea2ded8484bcfe96238f0124" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Fri Aug 12 12:56:43 2022 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "parallel.c: Consoldiate parallel master registration logic\n\nThis is analogous to spi.c and opaque.c however parallel\nlogic was previously never consoldiated.\n\nThis free\u0027s up flashrom.c from namespace pollution.\n\nTested: builds with both make and meson.\n\nChange-Id: Ie08e2e6c51ccef5281386bf7e3df439b91573974\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66651\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72349\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "dd9d0c58d601a003ebc1918c53edc16aab607080", "tree": "2daac025bb07ce348b414cb9c6e7957419ca3102", "parents": [ "4bd966c8099b64ebb665b6f40786bb21d59a9363" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Sat Jun 04 20:23:57 2022 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "tree: Consolidate BIT() macro\n\nChange-Id: I7e61f7671b70ca5ed751d99405714436bcd18d5a\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64962\nOriginal-Reviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nOriginal-Reviewed-by: Elyes Haouas \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72338\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "2d17041c5e170b42785e99d2aaedb98abb9bf040", "tree": "b60bbb992860f4c8d5bca7ff2c67ebcba2f26647", "parents": [ "f6a273b353355fd3817a00135019fd71e3543683" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Mon Nov 15 15:47:15 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "flashrom: Drop read_flash_to_file() usage\n\nAspire towards a goal of making cli_classic more of just\na user of libflashrom than having quasi-parallel paths in\nflashrom.c\n\nThis converts remaining read_flash_to_file() usage to the\ndo_read() provider wrapper around libflashrom.\n\nTested: `\nsudo ./flashrom -p ft2232_spi:type\u003d232H,divisor\u003d1000 -f -r out -c W25X05\nFlashrom output:\n\nNo EEPROM/flash device found.\nForce read (-f -r -c) requested, pretending the chip is there:\nAssuming Winbond flash chip \"W25X05\" (64 kB, SPI) on ft2232_spi.\nPlease note that forced reads most likely contain garbage.\nBlock protection could not be disabled!\nReading flash... done.\nData read:\n\nxxd out-1khz\n00000000: 0000 07ff ffff e000 0000 7fff fffe 0000 ................\n00000010: 0007 ffff ffe0 0000 007f ffff fe00 0000 ................\n00000020: 07ff ffff e000 0000 7fff fffe 0000 0007 ................\n00000030: ffff ffe0 0000 007f ffff fe00 0000 0fff ................\nxxd out-100khz\n00000000: b6db 6db6 db6d b6db 6db6 db6d b6db 6db6 ..m..m..m..m..m.\n00000010: db6d b6db 6db6 db6d b6db 6db6 db6d b6db .m..m..m..m..m..\n00000020: 6db6 db6d b6db 6db6 db24 9249 2492 4924 m..m..m..$.I$.I$\n00000030: 9249 2492 4924 9249 2492 4924 9249 2492 .I$.I$.I$.I$.I$.\n`\n\nChange-Id: I4b690b688acf9d5deb46e8642a252a2132ea8c73\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Tested-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59291\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72336\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "58015c25eb05fa77966d1c53261a83b56a3cf6b3", "tree": "a1df11881a074c8c66de756f846be9030ce0443a", "parents": [ "e276765eca031c6900d37b22b89e686283f39c91" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Thu Apr 14 13:50:55 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "Introduce an `include` directory for header files\n\nMove all header files to the new `include` directory.\nAdapt include directives and build systems to the new directory.\n\nChange-Id: Iaddd6bbfa0624b166d422f665877f096983bf4cf\nSigned-off-by: Felix Singer \u003cfelix.singer@secunet.com\u003e\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58622\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72322\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "e276765eca031c6900d37b22b89e686283f39c91", "tree": "97c22e96f45e7e7cb0520941a2d7d292d716fa18", "parents": [ "17affdcd24896b6bb7e73137e9d026ad66a36dfd" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Thu Apr 07 17:48:53 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "Drop STANDALONE mode\n\nSTANDALONE mode was used to build flashrom without having support for\nfile handling. This was relevant to build libflashrom on top of\nlibpayload. For a while now, the code which is covered by STANDALONE has\nmoved to cli_*.c and is not used for libflashrom. Therefore we can drop\nSTANDALONE mode.\n\nChange-Id: I58fb82270a9884a323d9850176708d230fdc5165\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/63469\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72321\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "98cfa69207c6558fce9b71f8d0510b3130afd67e", "tree": "82a951c69051eb9d9491cf4a87dbf0a9de4e3ce0", "parents": [ "306c8b76f7fd6326371b2208f516d5090cdb8370" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Mon Dec 13 12:46:12 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "flashrom.c: Move do_*() helpers into cli_classic.c\n\nThese helpers are only used by the CLI logic and so we localise\nthem here to move towards cli_classic being a pure libflashrom\nuser.\n\nChange-Id: If1112155e2421e0178fd73f847cbb80868387433\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60070\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72290\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "c72d20aa8f6a05dda4e0d0a616cdeccc897736e2", "tree": "5e2166c061b70a2b6e653e8fd9f5f616295c0513", "parents": [ "83aa6afc09f89d78b27f02d1005847b17128e81e" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Mon Dec 13 12:30:03 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "cli_classic.c: Convert do_erase() to libflashrom call\n\nInline emergency_help_message() to cli_classic call site.\nThis leaves do_erase() a redudant wrapper and moves us a step\ncloser to cli_classic as a pure libflashrom user by using\nflashrom_flash_erase().\n\nTested: `flashrom -E`\n\nChange-Id: I8566164e7dbad69cf478b24208014f10fb99e4d0\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60068\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72287\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3d5be0b5f65fe191839b567cfc3bc8b76abeeef5", "tree": "e49001b4796c9a0e54b21a6eda49dd8a0308ea50", "parents": [ "433dc1c647f0601dd5c7aa5d0c0584dc6ef80c96" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.de", "time": "Tue Oct 12 20:31:45 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "hwaccess: replace flashrom specific macros by compiler defines\n\nReplace the remaining IS_* macros with the associated compiler defines\n\nChange-Id: Ia0f022d12390722816066d292e1878824adc613c\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58280\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72248\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "345f65aac482e813d36e74ad7508254cf8f58c4d", "tree": "289105d2e073651d36913820997db11550a2b612", "parents": [ "d9b57717471346b89da335bdf14ade85426efbfe" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri May 14 01:11:08 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "layout: Tidy up the include-args API\n\nMove all forward declarations into `layout.h`, use consistent naming.\n\nChange-Id: I0e87c9d91b9bc4d78f9cee98caff6985803f7be7\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54287\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72223\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d9b57717471346b89da335bdf14ade85426efbfe", "tree": "13901f46bcd8b00d33ceb1eb881e101f914ac323", "parents": [ "e0ed4120f70c9642951c74ba6698405fbec75c08" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri May 14 01:07:28 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "layout: Kill the global layout\n\nChange-Id: Ic302e9c5faf1368e5ca244ce461e55e14f916ab8\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54286\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72222\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e0ed4120f70c9642951c74ba6698405fbec75c08", "tree": "fad22f015b4c60157d85214aef0eeae99be93b82", "parents": [ "efe96a939e08bad88890531a7961925e03c5196e" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri May 14 00:48:28 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "layout: Rework normalize_romentries() API\n\nRename it to layout_sanity_checks() as that is what it does and\nlet it work on the currently active layout instead of the global\nlayout.\n\nChange-Id: Ifae3480d4bd68c939c291f05734544e93f00306c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54285\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72221\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5bd990c2ab8ceb263d598a2348d7020ce774784f", "tree": "0ee2bdd6b6aa9af15becf68d7afd4142df0bf99c", "parents": [ "92e0b62fc37a6d89975ced41f5ec3c3715404f33" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 16 19:46:46 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "layout: Introduce flashrom_layout_new()\n\nIt initializes an empty layout. Currently the maximum number of entries\nhas to be specified, which will vanish once we use dynamic allocation\nper entry.\n\nWe replace the two special cases `single_layout` and `ich_layout` with\ndynamically allocated layouts. As a result, we have to take care to\nrelease the `default_layout` in a flashctx once we are done with it.\n\nChange-Id: I2ae7246493ff592e631cce924777925c7825e398\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/33543\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72214\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a1805097309f7d230f3596550fc673b109d5b19d", "tree": "1a2772c9df3563a3ec5dc167dd900501b665744e", "parents": [ "2fc70dcfe988928e97e69e98d91e7e3999ecd352" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Mon May 16 11:10:36 2022 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "flashrom.c: Make need_erase() helper static local\n\nThe need_erase() helper is only used within flashrom.c\n\nChange-Id: Ic0946bb109fca2fc18e15eefa11cccea284ded0b\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64369\nOriginal-Reviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71460\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "f6c1cb1a856e67b8cf7eaf7a90b09bc3923a3718", "tree": "9776b733a8f851fe90b582068baae97e64425e40", "parents": [ "137f02f887144eae222e44adb675cb299fd00337" ], "author": { "name": "Martin Roth", "email": "gaumless@gmail.com", "time": "Tue Mar 15 10:55:25 2022 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "Global cleanup: Fix a few spelling errors\n\nJust a trivial patch to fix a few errors found by codespell.\n\nHere\u0027s the command I used:\ncodespell -S subprojects,out \\\n-L fwe,dout,tast,crate,parms,claus,nt,nd,te,truns,trun\n\nSigned-off-by: Martin Roth \u003cgaumless@gmail.com\u003e\nChange-Id: I4e3b277f220fa70dcab21912c30f1d26d9bd8749\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62840\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Elyes Haouas \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71455\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d75e1b1fda75e3573140912cb0af246ccf86c8ee", "tree": "0b20aa11090ab199fe70055e964f78aa5a0fe096", "parents": [ "f55ca20fcf7fcc8a8c95d034c7126217a117e88e" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Wed Jul 14 15:06:04 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "flashrom.c: Make extract_param() static local\n\nThe function is only ever used within flashrom.c.\n\nChange-Id: I81f1cdb9df98c151201390edeb69c74defe7881f\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/56295\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71414\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "c720b6e8fbe9245e670f1424c5d24143b22a4c72", "tree": "82c71b6415f8583d331ea7fc88ce73e2705f6071", "parents": [ "590525835ab9f8b9471c17f859e0e18245008c08" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Thu Oct 06 15:17:52 2022 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:54 2022 +0100" }, "message": "flash.h: extend `struct tested` with .wp field\n\nUsing \"B\" letter for \"block protection\" in TEST_* macros.\n\nTicket: https://ticket.coreboot.org/issues/377\nChange-Id: I791400889159bc6f305fb05f3e2dd9a90dbe18a4\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/68179\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71000\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "9bb8a322e991b899a6faff4ec14d2f4c6dba447d", "tree": "466f98faf8e1f425b5c3144e399008bf14ac8b35", "parents": [ "542b1f04869e7ac42b84800675f08f617ddf3f2d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue May 24 15:07:34 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:52 2022 +0100" }, "message": "flashchips,spi25: Replace `.wrea_override` with FEATURE_4BA_EAR_1716\n\nThere are two competing sets of instructions to access the extended\naddress register of 4BA SPI chips. Some chips even support both sets.\n\nSo far, we assumed the 0xc5/0xc8 instructions by default and allowed\nto override the write instructions with the `.wrea_override` field.\nThis has some disadvantages:\n\n* The additional field is easily overlooked. So when adding a new\n flash chip, one might assume only 0xc5/0xc8 are supported.\n\n* We cannot describe flash chips completely that allow both\n instructions (and some programmers may be picky about which\n instructions can be used).\n\nTherefore, replace the `.wrea_override` field with a feature flag.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: I6d82f24898acd0789203516a7456fd785907bc10\nTicket: https://ticket.coreboot.org/issues/357\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64636\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70993\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "542b1f04869e7ac42b84800675f08f617ddf3f2d", "tree": "9516bc3f06c3fc5d67203328e524b967b5d36901", "parents": [ "a8258d76aa2fb7c5f2e2085a0d1bab6804bf7a7c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue May 24 14:30:12 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:52 2022 +0100" }, "message": "flashchips: Rename FEATURE_4BA_EXT_ADDR -\u003e _EAR_C5C8\n\nThere are two competing sets of instructions to access the extended\naddress register of 4BA SPI chips. Some chips even support both sets.\nTo prepare for other instructions than the default 0xc5/0xc8, rename\nthe original feature flag.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: Iacb7b68a9e3444fe28873ff0fe5e3fab16643c8c\nTicket: https://ticket.coreboot.org/issues/357\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64635\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70992\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3f3c1f3238dcede30d0d15d36da6326b428b8b12", "tree": "9adc4f207793fe401c9ffd28e2f7c60460766533", "parents": [ "478e179f2d5ecf6a8b82984444b9111913a8f50f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat May 28 16:48:26 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:50 2022 +0100" }, "message": "spi25_statusreg: Allow WRSR_EXT for Status Register 3\n\nSpansion flash chips S25FL128L and S25FL256L use the WRSR instruction to\nwrite more than 2 registers. So align SR2 and SR3 support: The current\nFEATURE_WRSR_EXT is renamed to FEATURE_WRSR_EXT2 and FEATURE_WRSR_EXT3\nis added. Also, WRSR3 needs a separate flag now.\n\nVerified that FEATURE_WRSR_EXT2 still works using the `dummy_flasher`.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: Ibdfc6eb3d2cfecbf8da0493d067031ddb079a094\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64746\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70988\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "801fcd0123af9a253d68089e2728d0f51a64b749", "tree": "71351110f1e02733565e415bf6ec322e11958d8d", "parents": [ "0b2e7dd80847f19f30db35e6e0d47f3c7b02ffbf" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Sun Dec 19 18:45:16 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:48 2022 +0100" }, "message": "writeprotect: add WPS bit and always set it to zero\n\nWPS bit controls use of individual block protection which is mutually\nexclusive with protection based on ranges. Proper support requires\nextension of the API as well as implementation, so here we\u0027re just\nmaking sure that range-based protection is enabled and our WP\nconfiguration is not ignored by the chip.\n\nChange-Id: I2c26ec65d64a3b6fb1f1a73690bc771415db2744\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60231\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70981\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0b2e7dd80847f19f30db35e6e0d47f3c7b02ffbf", "tree": "020dea176939135afa15e8f328088e808b6c812a", "parents": [ "9bf829d9a0b08323ca0ef8f2b52737f3eafbfe21" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Sun Dec 19 18:37:51 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:48 2022 +0100" }, "message": "spi25_statusreg.c: add SR3 read/write support\n\nAdds support for reading and writing the third status register.\n\nFeature flag is not needed because it would never on its own control\nwhether SR3 access occurs. If added, it would be in one of three\npossible states: wrong, useless or redundant.\n\nChange-Id: Id987c544c02da2b956e6ad2c525265cac8f15be1\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60230\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70980\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "c9feb1bdfa96745a200b9a62dc4234446db8ddb6", "tree": "b532df293904cb48d7efa7b127a0072f48801835", "parents": [ "da1c834e9899e5094377a33d19daa53c0d88640b" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Oct 21 01:35:13 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:45 2022 +0100" }, "message": "flashchips,writeprotect_ranges: add range decoding function\n\nAllow chips to specify functions that map status register bits to\nprotection ranges. These are used to enumerate available ranges and\ndetermine the protection state of chips. The patch also adds a range\ndecoding function for the example chips. Many other chips can also be\nhandled by it, though some will require different functions (e.g.\nMX25L6406 and related chips).\n\nAnother approach that has been tried in cros flashrom is maintaining\ntables of range data, but it quickly becomes error prone and hard to\nvalidate.\n\nUsing a function to interpret the ranges allows compact encoding with\nmost chips and is flexible enough to allow chips with less predictable\nranges to be handled as well.\n\nTested: dumped range tables, checked against datasheets\n\nChange-Id: Id163ed80938a946a502ed116e48e8236e36eb203\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58480\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70969\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "c6c3f28c66e0ad792274ca05029a120925e21be6", "tree": "0df6153a2d812235b3defe835f40b9ed08684c92", "parents": [ "9de3f8710d5c46d35cd9869018c85e5aa51483b0" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Wed Oct 20 23:34:15 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:44 2022 +0100" }, "message": "flash.h,flashchips.c: add writeprotect bit layout map to chips\n\nThis patch adds a register bit map `struct reg_bit_info`, with fields\nfor storing the register, bit index, and writability of each bit that\naffects the chip\u0027s write protection. This allows writeprotect code to be\nindependent of the register layout of any specific chip. The new fields\nhave been filled out for example chips.\n\nThe representation is centered around describing how bits can be\naccessed and modified, rather than the layout of registers. This is\ngenerally easier to work with in code that needs to access specific bits\nand typically requires specifying the locations of fewer bits overall.\n\nTested: flashrom --wp-{enable,disable,range,list,status} at end of patch series\n\nChange-Id: Id08d77e6d4ca5109c0d698271146d026dbc21284\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58477\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70966\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "9de3f8710d5c46d35cd9869018c85e5aa51483b0", "tree": "b742b7c1631b89e1cfa18a5553fc3da57ed2b8df", "parents": [ "0167522794a2e66f00248347122c1bb8ce3b001d" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Wed Oct 20 22:32:25 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:44 2022 +0100" }, "message": "spi25_statusreg,flashchips: add SR2 read/write support\n\nThis patch adds support for reading and writing the second status\nregister and enables it on a limited set of flash chips.\n\nChip support for RDSR2/WRSR2/extended WRSR is represented using feature\nflags to be consistent with how other SPI capabilities are represented.\n\nTested: flashrom -{r,w,E}\nTested: flashrom --wp-{enable,disable,range,list,status} at end of patch series\nTested: logged SR2 read/write values during wp commands\n\nChange-Id: I34a503b0958e8f2f22a2a993a6ea529eb46b41db\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58570\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70965\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0167522794a2e66f00248347122c1bb8ce3b001d", "tree": "ac01ed9312b2946bdcdbe1abf1078b69f6117183", "parents": [ "236a38cc46ac810d0be679402bb21e83aebcb8b9" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Wed Oct 20 22:30:41 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:43 2022 +0100" }, "message": "spi25_statusreg: make register read/write functions generic\n\nThis patch adds new spi_{read,write}_register() functions that take the\nsource/destination register as an argument. Currently they can only\naccess SR1, support for other registers will be added in another patch.\n\nSince we\u0027re refactoring things, this commit also makes\nspi_read_register() return an error code, making it possible to identify\nerror conditions that spi_read_status_register() concealed.\n\nThis also removes the initial 100ms delay between writing a register and\nthe first attempt to check the chip\u0027s status. An initial delay was added\nto avoid needing to read the status register multiple times, but that is\nunlikely to cause problems on modern flash chips.\n\nTested: flashrom -{r,w,E}\nTested: flashrom --wp-{enable,disable,range,list,status} at end of patch series\n\nChange-Id: I0a3951bbf993f2d8d830143b29d3ce16cc6901d7\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58475\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70964\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "4ad486465ccceedce372c498ad19ac84edbc0078", "tree": "b278a2499ed1ac3101b4e74f48a8a622640c15d3", "parents": [ "73ae5efbc36e8523d1f2fce1258a9ab2eef02e5e" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Nov 05 13:54:27 2020 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:36 2022 +0100" }, "message": "flashrom.c: implement chip restore callback registration\n\nAllows drivers to register a callback function to reset the\nchip state once programming has finished. This is used by\nthe s25f driver added in a later patch, which needs to change\nthe chip\u0027s sector layout to be able to write to the entire flash.\n\nAdapted from cros flashrom at\n`9c4c9a56b6a0370b383df9c75d71b3bd469e672d`.\n\nChange-Id: I2a522dc1fd3952793fbcad70afc6dd43850fbbc5\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/47276\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70940\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "5eca427ae64519b70d1c4ccfb427305ca9974ba0", "tree": "1ca22ef1e0072a76650fdd182206844f8ebddd7d", "parents": [ "1bbc501f79319cc6c8d839bc44fa55e96afab33a" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Sun Apr 12 17:27:53 2020 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:34 2022 +0100" }, "message": "const\u0027ify flashctx to align signatures with cros flashrom\n\nThe ChromiumOS flashrom fork has since const\u0027ify flashctx\nin a few places. This aligns the function signatures to\nmatch with downstream to ease forward porting patches\nout of downstream back into mainline flashrom.\n\nThis patch is minimum viable alignment and so feedback is\nwelcome.\n\nChange-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70933\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "8900d6c8e1438ee2a4a77c8e4d3feab81ee261e2", "tree": "5664d15b2f3ca63f9f96ef3284cbbf5c46499179", "parents": [ "7d6b526ef5b7b11f89eee37062e91590f5fa7f43" ], "author": { "name": "Miklós Márton", "email": "martonmiklosqdev@gmail.com", "time": "Tue Jul 30 00:03:22 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 04 11:03:46 2019 +0000" }, "message": "helpers: Implement strndup() for MinGW\n\nProvide strndup implementation if compiled with MinGW because\nit is a POSIX only method\n\nSigned-off-by: Miklós Márton \u003cmartonmiklosqdev@gmail.com\u003e\nChange-Id: If418080bffff1f5961cacf2a300ea9c666682458\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34621\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "519be66fc59558971dd653afe69ccaf1a633b492", "tree": "74f0912de156a86d56111f377db080246e5205e9", "parents": [ "ef78de4a21323b8c459337356289218211f2c5ce" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 23 20:03:35 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jul 31 08:26:59 2019 +0000" }, "message": "Fix -Wsign-compare trouble\n\nMostly by changing to `unsigned` types where applicable, sometimes\n`signed` types, and casting as a last resort.\n\nChange-Id: I08895543ffb7a48058bcf91ef6500ca113f2d305\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30409\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\n" }, { "commit": "d8b2e808cd46986f945ba9cf3b90c70fe58de9c6", "tree": "4094be4996c4ae32a78e0e13c558ee78bcdd85dc", "parents": [ "0373ce31fe5b11dcf23b27fbc221ba019a1cf7f1" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 18 23:39:56 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 21 11:54:19 2019 +0000" }, "message": "spi: Move 16MiB partitioning up into spi_chip_read()\n\nWe enforced a 16MiB limit in spi_read_chunked() for multi-die flash\nchips that can\u0027t be fully read at once. The same limit can be useful\nfor dediprog programmers. So move it into a more generic place.\n\nChange-Id: Iab1fd5b2ea550b4b3ef3e8402e0b6ca218485a51\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33613\nReviewed-by: Ryan O\u0027Leary\nReviewed-by: ron minnich \u003crminnich@gmail.com\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "b04fef91c100d815265bc1948e61a62f284c42ef", "tree": "9446fe01e60f38fde4dd777602a1e8dab2cce8cd", "parents": [ "ee13d0c8fa365455002b109ded7f94f990be8347" ], "author": { "name": "Arthur Heymans", "email": "arthur@aheymans.xyz", "time": "Tue Feb 05 17:35:05 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jun 17 08:03:12 2019 +0000" }, "message": "layout.c: Don\u0027t use global variables for included regions\n\nThis removes the use of global variables for included region arguments\nand also uses a linked list to store the arguments.\n\nChange-Id: I6534cc58b8dcc6256c2730c809286d8083669a6c\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/31247\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "86bddb5d52659f23531282db137350cbf7fb5992", "tree": "2f2b2da3f475065c9e86218b79ded18547c6b2c3", "parents": [ "57dbd64b33143964bb8eb91d33d72a2147f0091c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Mar 13 18:14:52 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 13:14:57 2018 +0000" }, "message": "Enable 4BA mode for Spansion 25FL256S\n\n4BA mode is entered by setting bit 7 for the extended address register.\n\nChange-Id: I807bf55d65763a9f48a6a3377f14f4e5288a7a4c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: Michael Fuckner \u003cmichael@fuckner.net\u003e\nReviewed-on: https://review.coreboot.org/25133\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "57dbd64b33143964bb8eb91d33d72a2147f0091c", "tree": "1606d103406bf36144602971ca2ac970d3a61482", "parents": [ "3eb5a8c82c00769bffc95c2c6c479de6d20dbd09" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Mar 13 18:01:05 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 13:10:17 2018 +0000" }, "message": "flashchips: Add Spansion 25FL256S......0\n\nThe Spansion 25SFL256S supports 4BA through an extended address register,\na 4BA mode set by bit 7 of that register, or native 4BA instructions.\nEnable the former only for now.\n\nUnfortunately the S25SF256S uses another instruction to write the exten-\nded address register. So we add an override for the instruction byte.\n\nChange-Id: I0a95a81dfe86434f049215ebd8477392391b9efc\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: Michael Fuckner \u003cmichael@fuckner.net\u003e\nReviewed-on: https://review.coreboot.org/25132\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "7ecfe48b19c3e97341a3f2b0d85e7367ab92f2b6", "tree": "8114881424b47ca6c3044e39da8e16615001887b", "parents": [ "af499198a49fe342a0bb3dbbfa362b8788a8fb4e" ], "author": { "name": "Marc Schink", "email": "flashrom-dev@marcschink.de", "time": "Thu Mar 17 16:07:23 2016 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 30 09:55:57 2018 +0000" }, "message": "helpers: Add reverse_byte() and reverse_bytes()\n\nChange-Id: I9d2e1e2856c835d22eed3b3a34bc0379773dd831\nSigned-off-by: Marc Schink \u003cflashrom-dev@marcschink.de\u003e\nReviewed-on: https://review.coreboot.org/28086\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f9a30554803a670f9b95a7794be00f03929d6ecd", "tree": "46da1dafce0c76ab5730540540aaf4093463f551", "parents": [ "291764a70e6d8b212680e311bfb0825abf2b9a2f" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Sat May 23 20:30:30 2015 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Thu May 17 16:49:16 2018 +0000" }, "message": "linux_mtd: Import driver from ChromiumOS\n\nThis imports a series of patches from chromiumos for MTD support.\nThe patches are squashed to ease review and original Change-Ids have\nbeen removed to avoid confusing Gerrit.\n\nThere are a few changes to integrate the code:\n- Conflict resolution\n- Makefile changes\n- Remove file library usage from linux_mtd. We may revisit this and use\n it for other Linux interfaces later on.\n- Switch to using file stream functions for reads and writes.\n\nThis consolidated patch is\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\n\nThe first commit\u0027s message is:\nInitial MTD support\n\nThis adds MTD support to flashrom so that we can read, erase, and\nwrite content on a NOR flash chip via MTD.\n\nBUG\u003dchrome-os-partner:40208\nBRANCH\u003dnone\nTEST\u003dread, write, and erase works on Oak\n\nSigned-off-by: David Hendricks \u003cdhendrix@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/272983\nReviewed-by: Shawn N \u003cshawnn@chromium.org\u003e\n\nThis is the 2nd commit message:\n\nlinux_mtd: Fix compilation errors\n\nThis fixes compilation errors from the initial import patch.\n\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\n\nThis is the 3rd commit message:\n\nlinux_mtd: Suppress message if NOR device not found\n\nThis just suppresses a message that might cause confusion for\nunsuspecting users.\n\nBUG\u003dnone\nBRANCH\u003dnone\nTEST\u003dran on veyron_mickey, \"NOR type device not found\" message\nno longer appears under normal circumstances.\nSigned-off-by: David Hendricks \u003cdhendrix@chromium.org\u003e\n\nReviewed-on: https://chromium-review.googlesource.com/302145\nCommit-Ready: David Hendricks \u003cdhendrix@chromium.org\u003e\nTested-by: David Hendricks \u003cdhendrix@chromium.org\u003e\nReviewed-by: Shawn N \u003cshawnn@chromium.org\u003e\n\nThis is the 4th commit message:\n\nlinux_mtd: Support for NO_ERASE type devices\n\nSome mtd devices have the MTD_NO_ERASE flag set. This means\nthese devices don\u0027t require an erase to write and might not have\nimplemented an erase function. We should be conservative and skip\nerasing altogether, falling back to performing writes over the whole\nflash.\n\nBUG\u003db:35104688\nTESTED\u003dZaius flash is now written correctly for the 0xff regions.\n\nSigned-off-by: William A. Kennington III \u003cwak@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/472128\nCommit-Ready: William Kennington \u003cwak@google.com\u003e\nTested-by: William Kennington \u003cwak@google.com\u003e\nReviewed-by: Brian Norris \u003cbriannorris@chromium.org\u003e\n\nThis is the 5th commit message:\n\nlinux_mtd: do reads in eraseblock-sized chunks\n\nIt\u0027s probably not the best idea to try to do an 8MB read in one syscall.\nTheoretically, this should work; but MTD just relies on the SPI driver\nto deliver the whole read in one transfer, and many SPI drivers haven\u0027t\nbeen tested well with large transfer sizes.\n\nI\u0027d consider this a workaround, but it\u0027s still good to have IMO.\n\nBUG\u003dchrome-os-partner:53215\nTEST\u003dboot kevin; `flashrom --read ...`\nTEST\u003dcheck for performance regression on oak\nBRANCH\u003dnone\n\nSigned-off-by: Brian Norris \u003cbriannorris@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/344006\nReviewed-by: David Hendricks \u003cdhendrix@chromium.org\u003e\n\nThis is the 6th commit message:\n\nlinux_mtd: make read/write loop chunks consistent, and documented\n\nTheoretically, there should be no maximum size for the read() and\nwrite() syscalls on an MTD (well, except for the size of the entire\ndevice). But practical concerns (i.e., bugs) have meant we don\u0027t quite\ndo this.\n\nFor reads:\nBug https://b/35573113 shows that some SPI-based MTD drivers don\u0027t yet\nhandle very large transactions. So we artificially limit this to\nblock-sized chunks.\n\nFor writes:\nIt\u0027s not clear there is a hard limit. Some drivers will already split\nlarge writes into smaller chunks automatically. Others don\u0027t do any\nsplitting. At any rate, using *small* chunks can actually be a problem\nfor some devices (b:35104688), as they get worse performance (doing an\ninternal read/modify/write). This could be fixed in other ways by\nadvertizing their true \"write chunk size\" to user space somehow, but\nthis isn\u0027t so easy.\n\nAs a simpler fix, we can just increase the loop increment to match the\nread loop. Per David, the original implementation (looping over page\nchunks) was just being paranoid.\n\nSo this patch:\n * clarifies comments in linux_mtd_read(), to note that the chunking is\n somewhat of a hack that ideally can be fixed (with bug reference)\n * simplifies the linux_mtd_write() looping to match the structure in\n linux_mtd_read(), including dropping several unnecessary seeks, and\n correcting the error messages (they referred to \"reads\" and had the\n wrong parameters)\n * change linux_mtd_write() to align its chunks to eraseblocks, not page\n sizes\n\nNote that the \"-\u003epage_size\" parameter is still somewhat ill-defined, and\nonly set by the upper layers for \"opaque\" flash. And it\u0027s not actually\nused in this driver now. If we could figure out what we really want to\nuse it for, then we could try to set it appropriately.\n\nBRANCH\u003dnone\nBUG\u003db:35104688\nTEST\u003dvarious flashrom tests on Kevin\nTEST\u003dReading and writing to flash works on our zaius machines over mtd\n\nChange-Id: I3d6bb282863a5cf69909e28a1fc752b35f1b9599\nSigned-off-by: Brian Norris \u003cbriannorris@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/505409\nReviewed-by: David Hendricks \u003cdhendrix@chromium.org\u003e\nReviewed-by: Martin Roth \u003cmartinroth@chromium.org\u003e\nReviewed-by: William Kennington \u003cwak@google.com\u003e\nReviewed-on: https://review.coreboot.org/25706\nTested-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Philipp Deppenwiese \u003czaolin.daisuki@gmail.com\u003e\n" }, { "commit": "e083880279119677e443fc16b4694f8c81bf2c40", "tree": "03413b996779bc4c86ec41590f3e7bcdd97d0ef5", "parents": [ "124ef38f7afc61ad7c713c22aad7c5c7f79bdb9b" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Mon Apr 02 11:14:02 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 24 20:21:41 2018 +0000" }, "message": "Remove address from GPLv2 headers\n\nChange-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/25381\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "b6e3d257f97fd4e3998e0743968d17010047b4c1", "tree": "6932c164c28e36b00788b35db201dbe40660e058", "parents": [ "22418428ed28d803bfca151623bbf017d1ba6bfc" ], "author": { "name": "Antonio Ospite", "email": "ao2@ao2.it", "time": "Sat Mar 03 18:40:24 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Mar 23 14:31:49 2018 +0000" }, "message": "Fix compilation with older MinGW versions\n\nThe __MINGW_PRINTF_FORMAT constant has been defined back in 2012\nhttps://sourceforge.net/p/mingw-w64/mingw-w64/ci/77bc5d6103b5fb9f59fbddab1583e69549913312/\n\nHowever older toolchains are still around and some user reported the\nfollowing compilation failure:\n\n flash.h:336:1: error: \u0027__MINGW_PRINTF_FORMAT\u0027 is an unrecognized format function  type [-Werror\u003dformat\u003d]\n  __attribute__((format(__MINGW_PRINTF_FORMAT, 2, 3)));\n\nFix this by defining the constant when it isn\u0027t already; the change does\nnot affect other compilers because it\u0027s guarded by \"#ifdef __MINGW32__\".\n\nSetting __MINGW_PRINTF_FORMAT to gnu_printf is exactly what newer MinGW\nversions do when __USE_MINGW_ANSI_STDIO is defined, which it is in\nflashrom Makefile.\n\nChange-Id: I48de3e4303b9a389c515a8ce230282d9210576fd\nTested-by: Miklos Marton \u003cmartonmiklosqdev@gmail.com\u003e\nSigned-off-by: Antonio Ospite \u003cao2@ao2.it\u003e\nReviewed-on: https://review.coreboot.org/25130\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f701f343117270b4373320eb25ae259b8e513b7d", "tree": "2749940aec9f2b1dc0ad53069079b78f225d76cf", "parents": [ "3a826043dbd389b4be2f5783c1b984ba297b8179" ], "author": { "name": "Paul Kocialkowski", "email": "contact@paulk.fr", "time": "Mon Jan 15 01:10:36 2018 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 11 16:54:14 2018 +0000" }, "message": "Add support for reading the current flash contents from a file\n\nWhen developing software that has to be flashed to a flash chip to be\nexecuted, it often takes a long time to read the current flash contents\n(for flashrom to know what pages to erase and reprogram) each time\nwhen writing the new image. However, when the flash was just reprogrammed,\nits current state is known to be the previous image that was flashed\n(assuming it was verified).\n\nThus, it makes sense to provide that image as a file for the flash contents\ninstead of wasting valuable time read the whole flash each time.\n\nChange-Id: Idf153b6955f37779ae9bfb228a434ed10c304947\nSigned-off-by: Mike Banon \u003cmikebdp2@gmail.com\u003e\nSigned-off-by: Paul Kocialkowski \u003ccontact@paulk.fr\u003e\nReviewed-on: https://review.coreboot.org/23263\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "80ae14e5105bb938679193906d1ee43b7a51c094", "tree": "629130fad3e6b0b731429bb90dc8e285a91ea8ab", "parents": [ "995f755ff569cbf6ed8d4eec5920b41628aa8ac9" ], "author": { "name": "Paul Kocialkowski", "email": "contact@paulk.fr", "time": "Mon Jan 15 01:07:46 2018 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 11 16:53:34 2018 +0000" }, "message": "Add support for the ENE Embedded Debug Interface EDI and KB9012 EC\n\nThe ENE Embedded Debug Interface (EDI) is a SPI-based interface for\naccessing the memory of ENE embedded controllers.\n\nThe ENE KB9012 EC is an embedded controller found on various laptops\nsuch as the Lenovo G505s. It features a 8051 microcontroller and\nhas 128 KiB of internal storage for program data.\n\nEDI can be accessed on the KB9012 through pins 59-62 (CS-CLK-MOSI-MISO)\nwhen flash direct access is not in use. Some firmwares disable EDI at runtime\nso it might be necessary to ground pin 42 to reset the 8051 microcontroller\nbefore accessing the KB9012 via EDI.\n\nThe example of flashing KB9012 at Lenovo G505S laptop could be found here:\nhttp://dangerousprototypes.com/docs/Flashing_KB9012_with_Bus_Pirate\n\nChange-Id: Ib8b2eb2feeef5c337d725d15ebf994a299897854\nSigned-off-by: Mike Banon \u003cmikebdp2@gmail.com\u003e\nSigned-off-by: Paul Kocialkowski \u003ccontact@paulk.fr\u003e\nReviewed-on: https://review.coreboot.org/23259\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "995f755ff569cbf6ed8d4eec5920b41628aa8ac9", "tree": "8bf525250f29a35eac59e1140da8c039790842cd", "parents": [ "31b5e3bfe6c01180d9a079813ecd199b4808315d" ], "author": { "name": "Paul Kocialkowski", "email": "contact@paulk.fr", "time": "Mon Jan 15 01:06:09 2018 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 11 16:52:48 2018 +0000" }, "message": "Add support for selecting the erased bit value with a flag\n\nMost flash chips are erased to ones and programmed to zeros. However, some\nother chips, such as the ENE KB9012 internal flash, work the opposite way.\n\nChange-Id: Ia7b0de8568e31f9bf263ba0ad6b051e837477b6b\nSigned-off-by: Mike Banon \u003cmikebdp2@gmail.com\u003e\nSigned-off-by: Paul Kocialkowski \u003ccontact@paulk.fr\u003e\nReviewed-on: https://review.coreboot.org/23258\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "31b5e3bfe6c01180d9a079813ecd199b4808315d", "tree": "3acefe04a94524cf9f3fdd47d4136f7c5b137b60", "parents": [ "305a2b3ed36ce87663aea177a806c6f435a4ceec" ], "author": { "name": "Mike Banon", "email": "mikebdp2@gmail.com", "time": "Mon Jan 15 01:10:00 2018 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 11 16:52:30 2018 +0000" }, "message": "Add a SPI command class to `struct flashchip`\n\nBy default, we want to probe for SPI25 chips only. Other SPI use cases,\nlike the ENE/EDI protocol, might use commands that can confuse these\ncommon chips.\n\nNow, flashrom will probe for a chip only if one of these conditions is\ntrue:\n1) no chip has been specified AND the chip uses the SPI25 commands\n2) this chip has been specified by -c | --chip \u003cchipname\u003e\n\nThe CLI can later be extended to probe for a specific class of chips.\n\nChange-Id: I89a53ccaef2791a2ac32904d7ab813da7478a6f0\nSigned-off-by: Mike Banon \u003cmikebdp2@gmail.com\u003e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/23262\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Kocialkowski \u003ccontact@paulk.fr\u003e\n" }, { "commit": "aac81424ebb8234b54cbab8fe47350b562b84fae", "tree": "2806be52075a5a3a46c5e7be2ccdb6d69b6e1a0f", "parents": [ "fe34d2af28bd81aaa1e23ba38febaa98ec4bb90c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 10 22:54:13 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jan 02 20:15:35 2018 +0000" }, "message": "flashchips: Revise all 4BA chips\n\nAdvertise all 4BA features that are currently supported by flashrom,\nplus add a new feature flag for the 4BA fast-read instruction. Also,\nlist all supported 3BA and 4BA erase-block functions.\n\nAs this adds a lot of new code paths that could be taken for these\nchips, mark them all as untested again.\n\nChange-Id: I0598496ee7058e3b170684d366f58e4014e0e871\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22423\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "fe34d2af28bd81aaa1e23ba38febaa98ec4bb90c", "tree": "53bda4d3445a94505455ffb12a96da602ba97af6", "parents": [ "1cf407b4f8d56035816efaf936a40553441eca46" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 10 21:10:20 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jan 02 20:15:30 2018 +0000" }, "message": "spi25: Revise decision when to enter/exit 4BA mode\n\nInstead of arbitrarily deciding whether to enter 4BA mode in the flash\nchip\u0027s declaration, advertise that entering 4BA mode is supported and\nonly enter it if the SPI master supports 4-byte addresses. If not, exit\n4BA mode (the chip might be in 4BA mode after reset). If we can\u0027t assure\nthe state of 4BA mode, we bail out to simplify the code (we\u0027d have to\nensure that we don\u0027t run any instructions that can usually be switched\nto 4BA mode otherwise).\n\nTwo new feature flags are introduced:\n\n* FEATURE_4BA_ENTER:\n Can enter/exit 4BA mode with instructions 0xb7/0xe9 w/o WREN.\n* FEATURE_4BA_ENTER_WREN\n Can enter/exit 4BA mode with instructions 0xb7/0xe9 after WREN.\n\nFEATURE_4BA_SUPPORT is dropped, it\u0027s completely implicit now.\n\nAlso, draw the with/without WREN distinction into the enter/exit\nfunctions to reduce code redundancy.\n\nChange-Id: I877fe817f801fc54bd0ee2ce4e3ead324cbb3673\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22422\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "ed098d62d66d91cf7330a37f9b83e303eb7f56d8", "tree": "639b6233e588fd8b4150b42112da36e239ba7fa4", "parents": [ "7e3c81ae7122120fe10d43fcba61a513e2461de9" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Apr 21 23:47:08 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:49:05 2017 +0000" }, "message": "spi: Move ICH BBAR quirk out of the way\n\nGet rid of the layering violations around ICH\u0027s BBAR. Move all the weird\naddress handling into (surprise, surprise) `ichspi.c`. Might fix writes\nfor the `BBAR !\u003d 0` case by accident.\n\nBackground: Some ICHs have a BBAR (BIOS Base Address Configuration\nRegister) that, if set, limits the valid address range to [BBAR, 2^24).\nCurrent code lifted addresses for REMS, RES and READ operations by BBAR,\nnow we do it for all addresses in ichspi. Special care has to be taken\nif the BBAR is not aligned by the flash chip\u0027s size. In this case, the\nlower part of the chip (from BBAR aligned down, up to BBAR) is inacces-\nsible (this seems to be the original intend behind BBAR) and has to be\nleft out in the address offset calculation.\n\nChange-Id: Icbac513c5339e8aff624870252133284ef85ab73\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22396\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7a077222566c84546dca4a56c1a509626036e429", "tree": "b4cd487275dd4ffc92ad6ac885268842efbe9eb3", "parents": [ "a1672f829328e877d9b8dea7777f25e2eba52d0e" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 18:18:30 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:46:54 2017 +0000" }, "message": "spi25: Remove now obsolete `four_bytes_addr_funcs` path\n\nChange-Id: Idb7c576cb159630da2268813388b497cb5f46b43\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22386\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a1672f829328e877d9b8dea7777f25e2eba52d0e", "tree": "8f90cab7e18bc875241ff66eef153b80e7c4a71b", "parents": [ "f43c654ad0dcb11b2738bbfac9246d09bb1949e5" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 18:00:20 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:45:46 2017 +0000" }, "message": "spi25: Enable native 4BA read and write using feature bits\n\nPrefer the native 4BA instruction when they are supported. In this\ncase, override our logic to decide to use a 4BA address.\n\nChange-Id: I2f6817ca198bf923671a7aa67e956e5477d71848\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22385\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "f43c654ad0dcb11b2738bbfac9246d09bb1949e5", "tree": "1d1f74d771dc2e8e8a67dab985945c00f68e0097", "parents": [ "0ecbacbfca7f919f1780f5062c775d94c7869d81" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 17:47:28 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:44:17 2017 +0000" }, "message": "spi25: Integrate 4BA support\n\nAllow 4-byte addresses for instructions usually used with 3-byte\naddresses. Decide in which way the 4th byte will be communicated\nbased on the state of the chip (i.e. have we enabled 4BA mode)\nand a new feature bit for an extended address register. If we\nare not in 4BA mode and no extended address register is available\nor the write to it fails, bail out.\n\nWe cache the state of 4BA mode and the extended address register\nin the flashctx.\n\nChange-Id: I644600beaab9a571b97b67f7516abe571d3460c1\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22384\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a3140d0b18058610a2694fc3592031a849b0c92a", "tree": "194083a9889bb76a70cb447a14660d6ec449506c", "parents": [ "c8801734727e1e510cbd99e305007b73f9f57e93" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 11:20:58 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:41:38 2017 +0000" }, "message": "spi25: Introduce spi_simple_write_cmd()\n\nspi_simple_write_cmd() executes WREN plus a single byte write and polls\nWIP afterwards. It\u0027s used to replace current spi_erase_chip_*() imple-\nmentations.\n\nChange-Id: Ib244356fa471e15863b52e6037899d19113cb4a9\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22382\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "f268d8b2d6fe5ea5ab0e0e2c5eec02c16d023ce5", "tree": "e1bc61384072608248941a03ed03b1c0507816be", "parents": [ "e1a960e0a520263b380d898459b6909a8d7f59c5" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Thu Oct 26 18:45:00 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 03 16:50:17 2017 +0000" }, "message": "Fix standalone ich_descriptor_tool compilation with MinGW and DJGPP\n\nTARGET_OS as well as EXEC_SUFFIX were only set when called via the\nmain makefile and even then __USE_MINGW_ANSI_STDIO was not set\nfor MinGW.\n\nWhile at it, also replace the hardcoded gnu_printf printf format\nattribute with __MINGW_PRINTF_FORMAT which is set according to\n__USE_MINGW_ANSI_STDIO respectively.\n\nChange-Id: Id146f5ba06a0e510397c6f32a2bd7c819a405a25\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21838\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "cc20a9b08e849437a58402f4a64d63d3710684af", "tree": "01975202af6298ab6c357532b0e1d6e1d77715b8", "parents": [ "d94d254262594b912c65511b5d0675c6ab900d60" ], "author": { "name": "Ed Swierk", "email": "eswierk@skyportsystems.com", "time": "Mon Jul 03 13:17:18 2017 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 12:37:03 2017 +0000" }, "message": "4BA: Allow disabling 4-byte address mode for SPI flash\n\nThis allows us to support flash chips in any of the following\nconfigurations, regardless of whether the chip powers up in 3-byte or\n4-byte address mode.\n\n- standard commands with extended address register (*_4ba_ereg) or\n direct commands (*_4ba_direct) in 3-byte address mode (.set_4ba \u003d\n spi_exit_4ba_*)\n- standard commands (*_4ba) or direct commands (*_4ba_direct) in\n 4-byte address mode (.set_4ba \u003d spi_enter_4ba_*)\n- direct commands (*_4ba_direct) in either address mode (.set_4ba \u003d\n NULL)\n\nChange-Id: I0b25309d731426940fc50956b744b681ab599e87\nSigned-off-by: Ed Swierk \u003ceswierk@skyportsystems.com\u003e\nReviewed-on: https://review.coreboot.org/20510\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7fe85694c4a597abb2a83c2f0f3a62a1a22e130e", "tree": "0da033666d79e9b3dc471762d1b02ee41a7a7a8d", "parents": [ "5de3b9b7263196b1d2bf41659ca44c7ea386b8ab" ], "author": { "name": "Boris Baykov", "email": "dev@borisbaykov.com", "time": "Sat Jun 11 18:29:03 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 12:35:08 2017 +0000" }, "message": "4BA: Support for new direct-4BA instructions + W25Q256.V update\n\nLarge flash chips usually support special instructions to work with\n4-bytes address directly from 3-bytes addressing mode and without\ndo switching to 4-bytes mode. There are 13h (4BA Read), 12h (4BA Program)\nand 21h,5Ch,DCh (4BA Erase), correspondingly. However not all these\ninstructions are supported by all large flash chips. Some chips\nsupport 13h only, some 13h,12h,21h and DCh, but not 5Ch. This depends\non the manufacturer of the chip.\n\nThis patch provides code to use direct 4-bytes addressing instructions.\n\nThis code should work but it tested partially only. My W25Q256FV has\nsupport for 4BA_Read (13h), but doesn\u0027t have support 4BA_Program (12h)\nand 4BA_Erase instructions. So, direct 4BA program and erase\nshould be tested after.\n\nPatched files\n-------------\nchipdrivers.h\n+ added functions declarations for spi4ba.c\n\nflash.h\n+ feature definitions added\n\nflashchips.c\n+ modified definition of Winbond W25Q256BV/W25Q256FV chips\n\nflashrom.c\n+ modified switch to 4-bytes addressing for direct-4BA instructions\n\nspi4ba.h\n+ definitions for 4-bytes addressing JEDEC commands\n+ functions declarations from spi4ba.c (same as in chipdrivers.h, just to see)\n\nspi4ba.c\n+ functions for read/write/erase directly with 4-bytes address (from any mode)\n\nChange-Id: Ib51bcc5de7826b30ad697fcbb9a5152bde2c2ac9\nSigned-off-by: Boris Baykov \u003cdev@borisbaykov.com\u003e, Russia, Jan 2014\n[clg: ported from\n https://www.flashrom.org/pipermail/flashrom/2015-January/013198.html ]\nSigned-off-by: Cédric Le Goater \u003cclg@kaod.org\u003e\nReviewed-on: https://review.coreboot.org/20508\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5de3b9b7263196b1d2bf41659ca44c7ea386b8ab", "tree": "f3480e7191c83965a9ab97d429f090e07f30a552", "parents": [ "aa6c37444c1d1a5944ea8bb3912bb0efe27dffce" ], "author": { "name": "Boris Baykov", "email": "dev@borisbaykov.com", "time": "Sat Jun 11 18:29:02 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 12:33:37 2017 +0000" }, "message": "4BA: Support for 4-bytes addressing via Extended Address Register\n\nOn some flash chips data with addresses more than 24-bit field\ncan address may be accessed by using Extended Address Register.\nThe register has 1-byte size and stores high byte of 32-bit address.\nThen flash can be read from 3-bytes addressing mode with writing\nhigh byte of address to this Register. By using this way we have\naccess to full memory of a chip. Some chips may support this method\nonly.\n\nThis patch provides code use Extended Address Register.\n\nPatched files\n-------------\nchipdrivers.h\n+ added functions declarations for spi4ba.c\n\nflash.h\n+ feature definitions added\n\nflashrom.c\n+ modified switch to 4-bytes addressing to support extended address register\n\nspi4ba.h\n+ definitions for 4-bytes addressing JEDEC commands\n+ functions declarations from spi4ba.c (same as in chipdrivers.h, just to see)\n\nspi4ba.c\n+ functions for write Extended Address Register\n+ functions for read/write/erase with Extended Address Register\n\nChange-Id: I09a8aa11de2ca14901f142c67c83c4fa0def4e27\nSigned-off-by: Boris Baykov \u003cdev@borisbaykov.com\u003e, Russia, Jan 2014\n[clg: ported from\n https://www.flashrom.org/pipermail/flashrom/2015-January/013200.html ]\nSigned-off-by: Cédric Le Goater \u003cclg@kaod.org\u003e\nReviewed-on: https://review.coreboot.org/20507\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "9912718de18e455e16d26458aca4eac37f792aa2", "tree": "d447b47feb1d0f497c17ab6941e0b4c9afbed5cb", "parents": [ "b1f88360fc806ee69d7cf1b9404b3977bc53aace" ], "author": { "name": "Boris Baykov", "email": "dev@borisbaykov.com", "time": "Sat Jun 11 18:29:00 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 12:30:26 2017 +0000" }, "message": "4BA: Flashrom integration for the 4-bytes addressing extensions\n\nThis patch integrates code of the previous patch into Flashrom\u0027s code.\nAll the integrations is around 3 functions spi_nbyte_read, spi_nbyte_program\nand spi_byte_program. After this patch then are not static and can be called\nby their pointers saved in flashchips array. Also I added to flashrom.c some\ncode to switch a chip to 4-bytes addressing mode. And one error message is\ncorrected in spi.c because it\u0027s not suitable for 32-bit addresses.\n\nPatched files\n-------------\nflash.h\n+ added set of 4-bytes address functions to flashchip structure definition\n\nflashrom.c\n+ added switch to 4-bytes addressing more for chips which support it\n\nserprog.c\n+ added 4-bytes addressing spi_nbyte_read call to serprog_spi_read\n\nspi.c\n+ fixed flash chip size check in spi_chip_read\n\nspi25.c\n+ added 4-bytes addressing spi_nbyte_read call to spi_read_chunked\n+ added 4-bytes addressing spi_nbyte_program call to spi_write_chunked\n+ added 4-bytes addressing spi_byte_program call to spi_chip_write_1\n\nConflicts:\n\tserprog.c\n\nChange-Id: Ib051cfc93bd4aa7580519e0e6206d025f3ca8049\nSigned-off-by: Boris Baykov \u003cdev@borisbaykov.com\u003e, Russia, Jan 2014\n[clg: ported from\n https://www.flashrom.org/pipermail/flashrom/2015-January/013205.html ]\nSigned-off-by: Cédric Le Goater \u003cclg@kaod.org\u003e\nReviewed-on: https://review.coreboot.org/20505\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b1f88360fc806ee69d7cf1b9404b3977bc53aace", "tree": "9c2b6aac3c378702d1596b8eb506f87b180638a0", "parents": [ "50a5660c9c11c77c794783cd9a3343bc3ff07b6e" ], "author": { "name": "Boris Baykov", "email": "dev@borisbaykov.com", "time": "Sat Jun 11 18:28:59 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 10:10:17 2017 +0000" }, "message": "fixup! 4BA: Basic support for 4-bytes addressing mode extensions\n\nFix some whitespace, and braces. Remove sector size from comments that I\ncould not verify.\n\nChange-Id: I4faaa036fea744135fa37f405686fb9fd0882806\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/21947\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "50a5660c9c11c77c794783cd9a3343bc3ff07b6e", "tree": "7095a74f39788084a14c3657bc3b868f923f5340", "parents": [ "f4d7772cee806d68a06db5394ab85a6e76904e88" ], "author": { "name": "Boris Baykov", "email": "dev@borisbaykov.com", "time": "Sat Jun 11 18:28:59 2016 +0200" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sat Oct 14 00:46:41 2017 +0000" }, "message": "4BA: Basic support for 4-bytes addressing mode extensions\n\nIf flash chip is switched to 4-bytes addressing mode then all\nread/erase/program instructions will be switched from 3-bytes mode\nto 4-bytes mode. Then well known instructions like 03h (Read),\n02h (Program) and 20h,52h,D8h (Erase) will become one byte longer\nand accept 4-bytes address instead of 3-bytes.\n\nThis patch provides support for well known instructions in 4-bytes\naddressing mode. Also here is the code to enter 4-bytes addressing\nmode by execute the instruction B7h (Enter 4-bytes mode).\n\nPatched files\n-------------\nchipdrivers.h\n+ added functions declarations for spi4ba.c\n\nflash.h\n+ feature definitions added\n\nMakefile\n+ added spi4ba.c\n\nAdded files\n-----------\nspi4ba.h\n+ definitions for 4-bytes addressing JEDEC commands\n+ functions declarations from spi4ba.c (same as in chipdrivers.h, just to see)\n\nspi4ba.c\n+ functions for enter 4-bytes addressing mode\n+ functions for read/write/erase in 4-bytes addressing mode\n\nChange-Id: Ie72e2a89cd75fb4d09f48e81c4c1d927c317b7a7\nSigned-off-by: Boris Baykov \u003cdev@borisbaykov.com\u003e, Russia, Jan 2014\n[clg: ported from\n https://www.flashrom.org/pipermail/flashrom/2015-January/013199.html ]\nSigned-off-by: Cédric Le Goater \u003cclg@kaod.org\u003e\nReviewed-on: https://review.coreboot.org/20513\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d152fb95e2b7fda62a85f6c8e4112ba9f353a8d6", "tree": "cfd2ea28b75cb90db72f488ee237a068d0cb52a4", "parents": [ "731316a9128c4015bc0facd1743afeb3a080129e" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Jun 19 12:57:10 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jul 13 16:27:55 2017 +0000" }, "message": "Drop redundant `enum msglevel`\n\nUse `enum flashrom_log_level` instead to avoid further confusion.\n\nChange-Id: I1895cb8f60da3abf70c9c2953f52414cd2cc10a9\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/20268\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cf4bug@amsat.org\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "2d62572d1dd0c37eb626fd8faa17b26690f20b15", "tree": "c76d5035e6fe7b8f9ca841c7030a7f44712f3d16", "parents": [ "8d494992176abe0877c88f06fdbc9c8d8826ae87" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Tue May 03 10:48:02 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 22 10:34:51 2017 +0000" }, "message": "Fix linking with libpayload\n\no Move flashbuses_to_text() to flashrom.c, it\u0027s not a cli function.\no Guard `!defined(HAVE_STRNLEN)`. This guard was introduced in\n 23e10b87 (Add a bunch of new/tested stuff and various small\n changes 24) to support older BSDs. It\u0027s probably completely\n broken because HAVE_STRNLEN is presumably a GNU autotools\n thing. But we can\u0027t fix it without retesting these older BSDs.\n\nChange-Id: I561135209b819361d125eeaeef9ff886d6bae987\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18738\nReviewed-by: Philippe Mathieu-Daudé \u003cf4bug@amsat.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "305f417ea565a18c1e87dcf5d97307369b721c6c", "tree": "75fd4a1087415f99a64d0a5f26eaddcb54969883", "parents": [ "ad18631b59d814b38bb6757df93fac17937a6bc9" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Jun 14 11:55:26 2013 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jun 14 11:43:32 2017 +0200" }, "message": "Add option to read ROM layout from IFD\n\nAdd an option --ifd to read the ROM layout from an Intel Firmware\nDescriptor (IFD). Works the same as the -l option, if given, -i\nspecifies the images to update.\n\nv2: o Rebased on libflashrom, use libflashrom interface.\n o Use functions from ich_descriptors.c.\n\nv3: o Move ich_descriptors.o to LIB_OBJS, thus build it independent\n of arch and programmers.\n o Bail out if we aren\u0027t compiled for little endian.\n o Update flashrom.8.tmpl.\n\nv4: o Incorporated David\u0027s comments.\n o Removed single-character `-d` option.\n\nv5: Changed region names to match the output of `ifdtool --layout ...`\n\nChange-Id: Ifafff2bf6d5c5e62283416b3269723f81fdc0fa3\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/17953\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n" }, { "commit": "899e4ec810a1e2f3d377bc2095ba3d25b234a797", "tree": "270ac1d7101251d95a295effcbe5cf01ce2250f4", "parents": [ "1878110848f36c53667c9855f0a413c43e64597f" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Apr 29 18:39:01 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jun 03 20:19:30 2017 +0200" }, "message": "Kill doit()\n\nNo words can describe this feeling.\n\nv2: Rejoice while removing more, orphaned code (layout.c).\n\nChange-Id: Id81177c50b4410e68dcf8ebab48386a94cd9b714\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/17949\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "1878110848f36c53667c9855f0a413c43e64597f", "tree": "66bacd63991be932b3d031dfe280576449b3280e", "parents": [ "a9fc4f4ebf335f3f20a47a48f2b9c2b00a4de696" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Dec 10 13:34:12 2012 +0000" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sat Jun 03 20:15:56 2017 +0200" }, "message": "Adapt CLI to use new libflashrom interface\u0027 print callback\n\nThis renames CLI\u0027s print() to flashrom_print_cb() and registers it\nthrough the new libflashrom interface.\n\nv2: Add libflashrom.o to LIB_OBJS now that everything can be linked\n together.\n\nChange-Id: Idf19978eb8e340d258199193d2978f37409e9983\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/17948\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "454f61338213f73ca74fda54c0bf86afb01947de", "tree": "5c981a1a181c130467d3c37b99cdeaf686ff49c8", "parents": [ "7af0e79b44bdc86497a992a90855f284e74d73f1" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Dec 10 13:34:10 2012 +0000" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sat Jun 03 20:13:06 2017 +0200" }, "message": "Add a convenient libflashrom interface\n\nThis adds a minimal libflashrom interface based on the draft in the\nwiki. While the glue code in libflashrom.c is build on top of the\nexisting code instead on overhauling it, the interface in libflashrom.h\nis supposed to be stable. So we can keep the interface and adapt\ninternals later if favoured, without breaking clients.\n\nA new make target, libinstall, is also added. It installs libflashrom.a\nand libflashrom.h in lib/ and include/ dirs respectively.\n\nHooking this into the build would break linking of the CLI and is post-\nponed until that got fixed.\n\nv2: Rebase and fixes by Anton Kochkov.\n\nv3: o fl_image_*() rewritten with layout support (touch only included regions).\n o Moved read/erase/write/verify operations to flashrom.c.\n o Added layout pointer and flags to the flash context.\n\nv4: Removed libflashrom.o from LIB_OBJS until CLI is adapted.\n\nv5: o Incorporated David\u0027s comments.\n o Added `fl_flashprog_t` as dummy parameter to hide the fact that\n we have global state all around, and for future-proofness ofc.\n\nv6: o Change namespace prefix to flashrom_.\n o Remove typedefs.\n\nChange-Id: I00f169990830aa17b7dfae5eb74010d40c476181\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/17946\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "7af0e79b44bdc86497a992a90855f284e74d73f1", "tree": "df4c2b5d2776597d14b459f9c5e8430a55c7c075", "parents": [ "3a9939b952e614cd8e9e0530c22453f8f91c4e3a" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Apr 29 16:40:15 2016 +0200" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sat Jun 03 20:07:39 2017 +0200" }, "message": "Add functions to read/erase/write/verify by layout\n\nInspired by Lynxis\u0027 related work, this implements a foundation for\nlayout based flash access.\n\nAll operations iterate over the given layout regions. Erase and write\nthen walk, per region, over all erase blocks in an inner loop (which\nmight not be what we want, see note on optimization below). Special care\nhas been taken that flash content is merged properly, in case an erase\nblock is only partially covered by a layout region or even affects mul-\ntiple regions.\n\nA note on performance: In the case an erase block affects multiple\nregions, it will probably be read, erased and written for each region.\nAnother approach would be to walk all erase blocks once and check for\neach erase block which regions it touches (i.e. for each erase block,\nmerge data pontentially from the flash and all layout regions, then\nflash the combined data). That might result in cleaner code. I haven\u0027t\ntried it yet, though.\n\nChange-Id: Ic6194cea4c4c430e0cf9d586052508a865b09c86\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/17945\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "3a9939b952e614cd8e9e0530c22453f8f91c4e3a", "tree": "615a0ccb696f08e7761204b35eff57150c4858aa", "parents": [ "9e14aeda6464b2ecb391186e5b21bf5985141499" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Apr 27 15:56:14 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jun 03 12:18:02 2017 +0200" }, "message": "Give layouts their own type\n\nIntroduce `struct flashrom_layout` and refactor layout.c a little, so\nwe can reuse the layout from there and have other sources of layouts\nbeside it.\n\nI didn\u0027t want to clutter up flash.h any more. So things went into a new\nlayout.h.\n\nChange-Id: Icea1a58c283131cc9c5fde6f16d783538dc1a4c7\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/17944\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilippe.mathieu.daude@gmail.com\u003e\n" } ], "next": "23e10b87801c22f34642895de8b0b726265eb016" }