)]}' { "log": [ { "commit": "af9d738a66a885f19fdb0659455834f114d9d1e0", "tree": "e3596a537af16f3d9a0aee3dbe7bfc668fc5ce34", "parents": [ "0069440fb0905b7ff3bf5184ffae34673be2e35d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon May 01 13:33:26 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 22 09:47:02 2026 +0000" }, "message": "Add infrastructure to probe per bus\n\nAdd some infrastructure around per-bus probing functions. Each function\nis provided a private parameter, e.g. the expected length of an ID. This\nwill allow us to implement probing functions that are only called as of-\nten as necessary. The results will be stored in the `registered_master`\nstructure, to be compared to database entries later.\n\nThe probe_buses() wrapper can be used for chip entries, and allows us to\ntransition the existing probing functions one by one. Once all functions\nhave been ported, probe_flash() can be adapted as well and the wrapper\nwill become obsolete.\n\nChange-Id: I6e82b6d61df50234096ac39acab58a4014203933\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74899\n" }, { "commit": "610c1aad71bfa118c4f49ac01761f586b8dede69", "tree": "8ad4cfd904cf909526b32b03561ad369f42720d9", "parents": [ "b95fe9b9751746b269a3bbd7021cf731d8553715" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Feb 15 02:56:05 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 15 14:27:20 2026 +0000" }, "message": "spi: Pass master instead of flash to .send_command\n\nIn the SPI-master API, `.send_command` should only forward commands to\nthe SPI bus. All details about the commands and the SPI slave should be\nhandled in the chip driver. Hence, replace the `flashctx` pointer with\none to the `spi_master` to enforce proper separation.\n\nChange-Id: I50934a1294217794b7e23cc98ade7e4279c059a1\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74897\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "5469c15550be12b4da9d2fbf48f16137895e07ba", "tree": "d3a0fbf038e01141a02a3b49a19be4fc3ee92136", "parents": [ "89e6818a8e60e6e2ddc7d09da0e79b615ea36629" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Feb 12 22:56:52 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 15 14:27:20 2026 +0000" }, "message": "Add common master API to adapt voltage\n\nWe start by setting the voltage in prepare_flash_access() and, if we\nwere told to probe for a specific chip, before the probing. For now,\nwe leave the programmer driver\u0027s default voltage during the probing,\notherwise.\n\nOnce the probing is more bus centric, we can implement a more elabo-\nrate scheme. For instance, we can probe at the lowest voltage first\nand only increase it if there was no response at all.\n\nChange-Id: I6689813f83abe654ba7a18f2e0537314047bf15f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/414\n" }, { "commit": "e3f648c3146be28c642782b11187011dfd6f258d", "tree": "272af33324401b45fc68bef0e1d697bf502998c1", "parents": [ "32f1ea8df501b41362058bb699a7ea96482e4db3" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Feb 15 02:55:23 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Feb 14 22:42:55 2026 +0000" }, "message": "spi: Implement top-aligned to avoid BBAR hassle\n\nThe BBAR quirk in `ichspi\u0027 is the only case left where we need a flash\ncontext in the SPI `.send_command\u0027 functions. Our Git history suggests\nthat the elaborate calculation there was not added for an encountered\nsetup but rather all possible settings of BBAR [1]. There are only few\nsettings that make sense, however.\n\nBBAR sets a simple address boundary. Reads for any flash address below\nthe BBAR setting will be rejected. This was originally the only read-\nprotection mechanism, introduced with ICH7. The ICH7 datasheet states\nthat upper bits, above the flash chip\u0027s size, should be set to all 1s.\nThis makes sense, as otherwise the read-protection could be circumven-\nted by setting a higher address above BBAR, where the flash chip would\nsimply ignore the most significant bits. Conversely, this requires us\nto \"lift\" the flash addresses when the BBAR is configured properly. We\ncan achieve this by top-aligning all addresses.\n\nNewer chipsets have protected-range registers (PRx) now, that allow to\nconfigure read protection. Also the descriptor mode was introduced. So\nflash addresses have to match the descriptor regions, and lifting them\nisn\u0027t feasible. The BBAR register was still around until Wilcat Point\n(PCH9), though, probably useless, and without the note about upper ad-\ndress bits. Odd though, since [2], we only consider the BBAR on newer\nchipsets when in descriptor mode.\n\nAs the BBAR protection seems unlikely on newer chipsets, and the quirk\nhandling error-prone, we\u0027ll only change addresses on ICH7 and similar\nold chipsets. We don\u0027t want the dependency on the flash context, hence\nlet the generic `spi25\u0027 code top align the addresses.\n\n[1] commit ed098d62d66d (spi: Move ICH BBAR quirk out of the way)\n[2] commit 4095ed797f87 (Add support for Intel Silvermont: Bay Trail,\n Rangeley and Avoton)\n\nChange-Id: Ic6f6f5a24d89d4a1ebe2b99f08aabfcd65df129f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74896\n" }, { "commit": "f4d5f3294fd470830f2ec81d4bc803dccaeb9ae3", "tree": "a5408f9f92da87e86756af0b8951132dac22667b", "parents": [ "9c6b35f03ca30c60ee6d9d90b0a0309945e2714b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 08 18:42:55 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 10 15:56:47 2026 +0000" }, "message": "ichspi: Add Intel Panther Lake support\n\nPTL looks much like Lunar Lake. The only noticed differences so far are\na reserved frequency value that means 80MHz now, and that only 1.8V are\nsupported.\n\nTested `ich_descriptors_tool\u0027 output for the BIOS of an MSI Prestige 14\nFlip AI+ (D3MTG).\n\nDocuments used:\n * Intel® Core™ Ultra Processors (Series 3) Datasheet, Volume 1 of 2\n * Panther Lake H External Design Specification (EDS) Volume 2 of 2\n * Panther Lake-H Client Platform\n SPI Programming Guide\n\nChange-Id: Ifec90975cefc26bb7109d69fcdabcfe480516732\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/397\n" }, { "commit": "a193983b9647f1364e30bba56a1eef72726ccbc0", "tree": "ffefc51cc344409cede664cc45ba79a7df03aad1", "parents": [ "1926900454166df3de18a1fa584e79dab8a48d75" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 07 21:58:02 2025 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Feb 09 20:21:46 2026 +0000" }, "message": "amd: Fall back to reading rom3 range in case of ROM Armor\n\nAMD is pushing ROM Armor forward, which leaves the SPI handling to\nthe PSP and only a mailbox interface (guarded by SMM) for the main\nCPU. With the current ROM Armor 3, there is no opt-out in the BIOS\nsetup anymore.\n\nOnly access left for the main CPU is the read-only memory mapping.\nWe make this available when active ROM Armor is detected (SPI BAR\nregister reads all ff). Probing of the flash size is peculiar, we\ncan only try to guess it when memory contents look repetitive.\n\nTo not pollute the `amd_spi100` driver, we start a new one.\n\nStory: https://icon.sourcearcade.org/posts/amd_firmware_reading/\nChange-Id: Ib4866084fe80853fd66501176dbc6b766750062f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/350\n" }, { "commit": "612519b2c54a008744891540407f2c8ff251083d", "tree": "f264bf5339ab332436dfd9acaa86d76b7492c1cf", "parents": [ "d5a61efe4e73675570eba7d537b4ec7e476946cb" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Nov 06 23:37:11 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "ichspi: Add Intel Arrow Lake support\n\nARL looks much like a desktop version of Meteor Lake. Hardware registers\nseem to be the same, and the descriptor mostly differs in strap settings\n(as far as we are concerned).\n\nOdd enough, the old (pre 500 series) format for processor straps is used\nagain. For the descriptor detection, we shuffle the old default for Ibex\nPeak around, and make Arrow Lake the default for everything with over 80\nPCH traps.\n\nTested `ich_descriptors_tool\u0027 output for a GIGABYTE Z890M GAMING X BIOS.\n\nDocuments used:\n * Intel® Core™ Ultra 200S Series Processors Datasheet, Volumes 1 and 2\n * Arrow Lake-S and Arrow Lake-HX Client Platform\n SPI Programming Guide\n\nChange-Id: Ibaaeb896273eed3806561ba8c01d89770d27ff18\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/270\n" }, { "commit": "d5a61efe4e73675570eba7d537b4ec7e476946cb", "tree": "615c8bc476cf847c2d0bea4f7f1f154eede67e5a", "parents": [ "5e0d9b04a07f5646038020e1a45dd04c0b14e8f3" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Nov 06 23:55:44 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "ichspi: Add Intel Lunar Lake support\n\nHardware looks much the same as Meteor Lake. The descriptor, however,\nknows 7 masters and regions are named a bit differently. Hence, add a\nnew enum entry for Lunar Lake.\n\nTested `ich_descriptors_tool\u0027 output for an MSI Prestige 13 A2VMG BIOS.\n\nDocuments used:\n * Intel® Core™ Ultra 200V Series Processors Datasheet, Volumes 1 and 2\n * Lunar Lake Client Platform\n SPI Programming Guide\n\nChange-Id: Ia377872cba56a3db6d853b7ce1bd495e5a03a868\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/271\n" }, { "commit": "5e0d9b04a07f5646038020e1a45dd04c0b14e8f3", "tree": "70386babe868ba7282cbbb0d8bc53880286025e8", "parents": [ "0ef2eb8f041ad6918dd41f4837d39be8811889c9" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 19 21:44:52 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "ichspi: Add Intel Meteor Lake SoC\n\nHardware looks the same as C740 series / Emmitsburg. The descriptor\nis somewhere between the latter and latest desktop platforms.\n\nOutput of `ich_descriptors_tool\u0027 with an image from Google/Rex looks\nreasonable.\n\nTested probing and reading on a Lenovo L16 ThinkPad.\n\nDocuments used:\n * Intel® Core™ Ultra Processor Datasheet, Volumes 1 and 2\n * Meteor Lake/Arrow Lake-U / H Client Platform\n SPI Programming Guide\n\nChange-Id: I7f1d162622a141fadcad715b064f92b1ccf7c72a\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/189\n" }, { "commit": "0ef2eb8f041ad6918dd41f4837d39be8811889c9", "tree": "978d212a6cc5031e589162c49a36e4353e91c937", "parents": [ "42daab10a7704bfbe4a0af1a07748b8858649301" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 19 21:38:17 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "ichspi: Add Intel Snow Ridge SoC\n\nHardware looks the same as C740 series / Emmitsburg. The descriptor,\nhowever, has very different frequency settings and different regions\nand masters.\n\nThe output of `ich_descriptors_tool\u0027 tested with an image from Intel\nlooks reasonable.\n\nChange-Id: I9f9dc4414af63cbe48d22ef2955df28e297d7e4c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/188\n" }, { "commit": "42daab10a7704bfbe4a0af1a07748b8858649301", "tree": "9a9aa5465db9f58aa9d0c55f9807a2f694a98e05", "parents": [ "af26008fbabdd780bc6966acca4ad2481520b304" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jul 16 00:27:27 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "ichspi: Properly add Emmitsburg PCH\n\nThe Emmitsburg or C740 series PCH is actually ahead of all the other,\ncurrently supported chipsets. Finally, Intel added new registers that\ncarry the read and write access permissions for all 16 regions.\n\nThe old FRAP register seems to be still around, so we print both new\nand old registers. For the detailed report we use the new registers,\nthough.\n\nWe also adapt the descriptor detection slightly: We check for `NM \u003d\u003d 6`\njust like we did for Lewisburg. This way we won\u0027t treat a huge range of\nISL (ICH/PCH strap length) values as Emmitsburg, which should result in\nless false positives.\n\nThe output of `ich_descriptors_tool\u0027 tested on some Supermicro firmware\nlooks reasonable. Also tested read/erase/write in `swseq\u0027 and `hwseq\u0027\nmodes with 7 series PCH, reading with ADL-P. All logs still report FRAP\nsettings correctly.\n\nChange-Id: Ibf5ebe2e2edfe5e5ae26bf1136648bf6354b0aa9\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/187\n" }, { "commit": "dfd064759b416463244aafea80a5b7120ef8e4e1", "tree": "b1b636199d652391f66e7af12b306877d77b1aee", "parents": [ "b2ad9fd9186a0f6fea3e5b64415c1e5d1a19baa4" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 14 23:45:05 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 28 15:02:49 2024 +0000" }, "message": "ich_descriptors: Refactor component density handling\n\nIntroduce a new marker CHIPSET_HAS_NEW_COMPONENT_DENSITY and order\nthe actual chipset values around it. This move Bay Trail up before\nall 8-series PCHs.\n\nChange-Id: I1f4d724e2e2ef038aa6a56feb1578208afbbcd99\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/181\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "fda324bfc3c09cce47fe1947f6a2883b357d7f1d", "tree": "f2411a115e7d4a7d8222aa9c90aba3243c80921e", "parents": [ "a1f6476a65bda5262d46430724a3af4b49bcd9e7" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 14 20:36:21 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 28 15:02:49 2024 +0000" }, "message": "ichspi: Introduce SPI_ENGINE_PCH100 marker\n\nUse a new SPI_ENGINE_PCH100 marker in ich9_spi_init(). Suddenly this\nfunctions becomes more readable again.\n\nTested read/erase/write in `swseq\u0027 and `hwseq\u0027 modes with 7 series \u0026\nreading with ADL-P. Log output stays consistent.\n\nChange-Id: Iff03354ee886eb1ea80e37e50914b8afff08a29e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/174\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "a1f6476a65bda5262d46430724a3af4b49bcd9e7", "tree": "4c03ecc180e60864fcbf59952c01c58390921eed", "parents": [ "3f75d4476da015ae1ee033c1de1ad4dc08f66b0d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 14 20:23:28 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 28 15:02:49 2024 +0000" }, "message": "ichspi: Split ICH7 init out\n\nThe original, ICH7 init only shared about three lines with the newer,\never growing ICH9+ init. That\u0027s not worth an indentation level in an\nendlessly long function, so split it out.\n\nWe introduce a kind of \"breakpoint\" into the `ich_chipset\u0027 enum:\n\n SPI_ENGINE_ICH9\n\nThis marks all chipset entries below it as supporting this code path\nand should help to avoid long `case\u0027 lists.\n\nTested read/erase/write on ThinkPad T60 (ICH7).\n\nChange-Id: I41e46d12e02c1343e636b47b2378db86e76af95e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/173\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "1b1deda80bbd7f56b8047fad32badb749eeefffb", "tree": "e7058d9d175d08ed2542f6e34be0842a7ade8f57", "parents": [ "a1b7f3521f66a19a2d4c9a6a373c5a7ab36e1473" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Apr 18 00:35:48 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "Implement QPI support\n\nWith the quad-i/o support in place, this is actually straight-\nforward:\n* we check for compatibility of the flash chip and programmer,\n* select an appropriate fast-read function, and\n* always set the respective io-mode when passing a SPI command\n to the programmer.\n\nTested with FT4222H + W25Q128FV and linux_gpio_spi + MX25L25645G.\n\nChange-Id: I2287034f6818f24f892d66d1a505cb719838f75d\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/165\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "0c9af0a639bf9180839d548f91547b58de921ca9", "tree": "a0656e015b5a647cb81d8a85d427687b03a2f246", "parents": [ "930d421385aae5ca93d5963fba7926970d7702e8" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun May 05 12:20:22 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "spi25: Check quad-enable (QE) bit\n\nWhen a chip has a quad-enable bit, check its status and disable\nquad i/o if the bit isn\u0027t set. Note, some chips have a volatile\nQE bit that we could set/reset automatically without wear. This\nwould require more work on the register infrastructure and chip\ndatabase, though.\n\nChange-Id: I8a0b9b3dee14f344d4794c91d7d6fb962a8bea87\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/164\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "044c9dc9290565ab7b9866bb26a8d077d9c3a5d7", "tree": "b0d6ab8fc2df6d8ff7a91a3d197e213a7ca2a320", "parents": [ "fc7c13c882067b3ad7f2f5d3846d64164b8c8c87" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 29 23:26:57 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "Add FT4222H support\n\nThe FT4222H features a very different engine compared to what we are\nused to from other FTDI USB/serial chips. It doesn\u0027t do UART (at least\nnot officially), doesn\u0027t have the MPSSE engine, but has a quad-SPI\nmaster, and SPI/I2C slave support.\n\nA few similarities exist, though, so this could probably make use of\nlibftdi in the future.\n\nThere are two config-mode straps that select one of four modes:\n0. 1 data interface + 1 GPIO interface\n1. 3 data interfaces + 1 GPIO interface\n2. 4 data interfaces\n3. 1 data interface\n\nWith multiple data interfaces, GPIO pins are muxed as additional CS\nlines. The advantage of mode 0 and 3 is that apparently a bigger buffer\nis available for the data interface. Only in these modes, it gets to\nits full speed (52.8MBps according to the datasheet[1]). The CS line is\nautomatically selected based on the USB interface used. No test using\nmultiple interfaces at once were performed, though.\n\nAll the USB commands and transfer protocols were derived from traces\ngathered with the proprietary LibFT4222. The results are summarized\nin the flashprog wiki[2].\n\n[1] https://www.ftdichip.com/old2020/Support/Documents/DataSheets/ICs/DS_FT4222H.pdf\n[2] https://flashprog.org/wiki/FT4222H\n\nChange-Id: I9ee1287e13113ccf8b5ea2be4a25866413a94844\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/50\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "d16a911a77220d7cd600c749675070d204543b5d", "tree": "4fd0c463d1f352b79bac82d2bb84ab99e887532b", "parents": [ "226bb87b96c21fbd54061d043aca67e9a02f0aca" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 07 00:11:44 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "bitbang_spi: Move API into its own header file\n\nWe\u0027re going to extent it for multi-i/o.\n\nChange-Id: Ifead97d7a8f848b82a4d21c557f5d364066d5d6a\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/81\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "d518563f197241cc72f5da4b2108b2df10f00372", "tree": "8ec807be43adf3b5c9f66a2701b7bf0ea3a4a11f", "parents": [ "bd72a470b9b58386b52ca4568313be71b4d2c472" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 05 18:44:41 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "spi: Prepare for multi i/o and dummy bytes\n\nMulti-i/o commands split SPI transactions into multiple phases that\ncan be transferred over 1, 2 or 4 wires. For this, we adapt `struct\nspi_command` with a new enum, specifying the transfer mode, and ad-\nditional size fields. While we are at it, move everything related\ninto a new header file `spi_command.h` so we won\u0027t further clutter\n`flash.h`.\n\nOn the master side, we add respective feature flags for the multi-\ni/o modes.\n\nSee also the comment in `spi_command.h` about multi-i/o commands.\n\nChange-Id: I79debb845f1c8fec77e0556853ffb01735e73ab8\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/44\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "9a11cbf21a5078bcdb8db7584c44a9ee17020db4", "tree": "e67a9eadfdb7a71f81df36c7e97180474a8c59df", "parents": [ "aabb3e0ff54e87c0136c91f105e506ed19184cc6" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 13 01:19:07 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:40:04 2024 +0000" }, "message": "Let the flash context directly point to the used master\n\nWe used to have a pointer to a full `registered_master` struct in\nour flash context. Beside the used master, this contained a bit\nmask of supported buses. Oddly convenient, this bit mask invited\nto bypass the chip driver and break the abstraction. It allowed\nto place bus-specific details virtually anywhere in flashprog,\nmaking it harder to find a good place for them.\n\nSo, get rid of the `buses_supported` bit mask by pointing directly\nto the master. Only the chip driver will implicitly know which type\nof master is used.\n\nChange-Id: I9ce13d8df0e7ccc67519d888dd9cb2e2ff8d6682\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72533\n" }, { "commit": "89569d60e3aeeec651496b2e7a2e6064d782ab3b", "tree": "bf0c3951886de60086d32ff6e1a850adad926da6", "parents": [ "929d2e1b17a448d3352dbecb6a620ee0c1e65a58" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 12 23:31:40 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "memory_mapped: Reduce `decode_sizes` to a single `max_rom_decode`\n\nWe used to store the maximum decode size, i.e. the maximum memory-mapped\nrange of the flash chip, per bus type (Parallel, LPC, FWH, SPI). There\nwas no programmer in the tree that really made use of it, though:\n* The chipset drivers usually focus on a single bus type. And even if\n they advertise the whole default set (PAR, LPC, FWH), they only pro-\n vide a maximum decode size for one of them. The latter is probably\n wrong, should really more than one bus type be supported.\n* PCI and external programmers all support only a single bus type, with\n the exception of `serprog` which doesn\u0027t set a maximum decode size.\n\nWhat made the distinction even less useful is that for some chips that\nsupport multiple bus types, i.e. LPC+FWH, we can\u0027t even detect which\ntype it is. The existing code around this also only tried to provide\nthe best possible warning message at the expense of breaking the pro-\ngrammer abstraction.\n\nHence, unify the set of sizes into a single `max_rom_decode` property.\nWe store it inside the `registered_master` struct right away, to avoid\nany more use of globals.\n\nChange-Id: I2aaea18d5b4255eb843a625b016ee74bb145ed85\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72531\n" }, { "commit": "929d2e1b17a448d3352dbecb6a620ee0c1e65a58", "tree": "dcbad4698ce5741a1080fc7ba89d4bd5c5804417", "parents": [ "7c717c36c533f56ddc7fbac2ff944870fa0249f8" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 12 00:47:05 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "internal: Pass programmer context down into chipset enables\n\nChipset enables potentially need access to programmer data, e.g.\nto process parameters, register masters etc.\n\nChange-Id: Iad211ff97e92d1973f981156bfa3154d1ba71d45\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72528\n" }, { "commit": "7c717c36c533f56ddc7fbac2ff944870fa0249f8", "tree": "b91afaf1498cde1de33e7222632ec05999bf0b73", "parents": [ "e3a26888e14d16592c2c79d1516828d3d32961a4" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 12 00:28:15 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "internal: Pass programmer context down into board enables\n\nBoard enables potentially need access to programmer data, e.g. to\nprocess parameters, register masters etc.\n\nChange-Id: I1531a6e1be9866adc5dce74c6f62bbbeae1bd274\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72527\n" }, { "commit": "e3a26888e14d16592c2c79d1516828d3d32961a4", "tree": "02d401e60defd27fe7bee194978bac782284cb39", "parents": [ "2b66ad9c4465432e6f2aff2e95f1e7a556bfc3f0" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jan 11 21:45:51 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "Pass programmer context to programmer-\u003einit()\n\nChange-Id: I064eb4e25c3d382e4e5bde802306698fafe5e1d0\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72526\n" }, { "commit": "2b66ad9c4465432e6f2aff2e95f1e7a556bfc3f0", "tree": "187edbfe8e16593df21b2c4cb9c392e1011fd339", "parents": [ "4517e9242e8d871db5159ff8afd215f015832c7d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jan 11 20:15:15 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "Start implementing struct flashprog_programmer\n\nOur libflashprog API was already prepared for a programmer level context\nstored in an opaque `struct flashprog_programmer`. We start filling this\nstruct with a pointer to the programmer driver (entry in the programmer\ntable) and a mutable copy of the parameter string.\n\nChange-Id: If9a795627b1e50ea6006569e723f400ff337be20\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72525\n" }, { "commit": "0e76d99a7c0eda11515923c5457f0b5a4af9893f", "tree": "c914d5266909dad441bece2705593131f032c19c", "parents": [ "9eec40780207a110f3ba7ea70d11c042c6d86abf" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 12 20:22:55 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "memory_bus: Move (un)map_flash_region into par master\n\nNow that the map/unmap_flash functions are only called from memory-\nmapped chip drivers, we can safely move the hooks into the parallel\nmasters.\n\nThis also allows us to move the code away from the globals in\n`flashprog.c` into a new `memory_bus.c`.\n\nChange-Id: Ic476cf4d96200232900537b997e1d07bb4e8b809\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72522\nReviewed-by: Riku Viitanen \u003criku.viitanen@protonmail.com\u003e\n" }, { "commit": "46449b4d17c549a68d0b8ce287f20e4b46f13333", "tree": "14b936a26e05bd97eb60223dd1f9c1bec94b4899", "parents": [ "ab6b18f0e0d4f4b2b8348306576b701b63372bd2" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 12 23:58:19 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "spi25: Drop stale `bus \u003d\u003d SPI` guards\n\nThese guards were necessary workarounds because we used to call\nthe functions from core flashprog code. Now that the related code\nis contained in the chip driver, we can drop them.\n\nChange-Id: Ib06044a716e2d1c295d902877d0342deb2d78908\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72518\n" }, { "commit": "c3b02dce51aad2766512d1939a1b7447c2d526b8", "tree": "58069f464bb8a777ef06e93767813a4c5a042cb0", "parents": [ "a02df33fbf1c196395a61049e60895d4ae0e0a5b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Aug 12 01:13:45 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Sep 18 19:24:39 2023 +0000" }, "message": "Rebrand to flashprog and update URLs\n\nMostly automated `sed` work. As of now, URLs to the old wiki are broken\neither way, so changing them shouldn\u0027t hurt. Other URLs (e.g. to mailing\nlist archives) were hopefully filtered correctly.\n\nChange-Id: I9d43bfd0e675eff2fcbad05f304b9ce9f5006b08\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashrom-stable/+/21\n" }, { "commit": "2f75379fa20f5415c70b837001473ff8ba070ab7", "tree": "0f549c33c16f70f1c619926d91ce217e95eccd6a", "parents": [ "b1d4b1d6b8a7876496af6b8af422d1c8058d5f4e" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Mar 28 00:46:50 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 04 09:59:35 2023 +0000" }, "message": "internal: Don\u0027t try linux_mtd on x86\n\nWe assume that the first MTD device found represents the \"internal\"\nfirmware flash. This is true on many architectures, and assumed to\nbe working. On x86, however, there is traditionally no MTD device.\nOne exception is the `spi-intel` driver, but this one is tagged\n\"DANGEROUS\" and often makes trouble if a Linux distribution enabled\nit nevertheless.\n\nSo, let\u0027s disable the internal/MTD automatism on x86. Flashrom has\nbetter drivers, and if somebody runs into a situation where the MTD\ndriver would work but the internal one doesn\u0027t, they can still use\n`linux_mtd` explicitly.\n\nChange-Id: I813980786a09fe64f541906e1963b0abd8b93cb5\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73987\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\n" }, { "commit": "618994707d5ba556704ad9555191379cf46df6ae", "tree": "ad771fb01ca88cbf4ed3e93da0576f4a831a3929", "parents": [ "28790a23f71d942f7ec9aa03c5ec90fb90503d0f" ], "author": { "name": "Steve Markgraf", "email": "steve@steve-m.de", "time": "Mon Jan 09 23:06:52 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 04 12:33:03 2023 +0000" }, "message": "programmer: Add bitbanging programmer driver for Linux libgpiod\n\nWith this driver, any single board computer, old smartphone, etc. with\na few spare GPIOs can be used for flashrom.\n\nTested by reading of a 2048 kB flash chip on a Qualcomm MSM8916 SoC\n@800 MHz, ran the following command:\n\ntime flashrom -p linux_gpiod:gpiochip\u003d0,cs\u003d18,sck\u003d19,mosi\u003d13,miso\u003d56 -r test.bin\n\nThis command uses /dev/gpiochip0 with the specified GPIO numbers for the\nSPI lines. All arguments are mandatory.\n\nOutput:\n[...]\nFound GigaDevice flash chip \"GD25LQ16\" (2048 kB, SPI) on linux_gpiod.\n[...]\nreal 1m 33.96s\n\nChange-Id: Icad3eb7764f28feaea51bda3a7893da724c86d06\nSigned-off-by: Steve Markgraf \u003csteve@steve-m.de\u003e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73290\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0e78818c2c818aa860a976524cfdf552792cfeba", "tree": "0bd2c0ba9086639ba4c49259bfef7777ce95a82a", "parents": [ "a447c12ecf71954f40a2b07817b3933b7bd3e495" ], "author": { "name": "Anastasia Klimchuk", "email": "aklm@chromium.org", "time": "Wed May 26 09:54:08 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 04 12:33:03 2023 +0000" }, "message": "bitbang: Extend bitbang_spi_master functions to accept spi data\n\nThis way every bitbang spi master has access to its own spi data,\nand can use this data in all its functions.\n\nThis patch only changes the signatures of functions.\n\nflashrom-stable: Adapted new function signatures in `nicintel_spi`.\n\nChange-Id: Id5722a43ce20feeed62630ad80e14df7744f9c02\nSigned-off-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54991\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73268\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a447c12ecf71954f40a2b07817b3933b7bd3e495", "tree": "073037c43b3dc9b5f6c0204cc5ea8ef0161b7271", "parents": [ "cbc5ba049f7d6ce4744eae836221b0fb35a9ac69" ], "author": { "name": "Anastasia Klimchuk", "email": "aklm@chromium.org", "time": "Mon May 31 11:20:01 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 04 12:33:03 2023 +0000" }, "message": "bitbang: Extend register_spi_bitbang_master() API with spi data\n\nThis allows the users of register_spi_bitbang_master() API to pass\ntheir spi data into the API, and then the data can go further, into\nregister_spi_master() API.\n\nflashrom-stable: Removed unnecessary if.\n\nChange-Id: I13e83ae74dbc3a3e79c84d1463683d360ff47bc0\nSigned-off-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54990\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73267\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "4d51e07242459f86d00eaf522786695e46ec2511", "tree": "a513666f34cc601d6a9e9bf4f506383dbf69bcb2", "parents": [ "e3c305dfd234503faa23c5491962db8f52d0134c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 17:56:29 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 28 23:42:48 2023 +0000" }, "message": "amd_imc/sb600spi: Move handle_imc() into amd_imc.c\n\nMove handle_imc() to make it easier to share it with other drivers.\n\nChange-Id: I72dff5feda199e1d258c067e230abdf33c451249\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72575\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e3c305dfd234503faa23c5491962db8f52d0134c", "tree": "b86a019224a05586e18b98eae8ff0c9b51a1c701", "parents": [ "070587892b4af723bf8f1f423d0b26e12e061084" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 21:45:56 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 28 23:42:48 2023 +0000" }, "message": "amd_spi100: Implement memory-mapped reads\n\nQuery the RomRange2 register for the memory range (usually top below 4G)\nand try to map that. Reads outside this range will still be served via\nthe command engine.\n\nChange-Id: I21aa67d550ccda0f55a9cf3ff14545a881624d11\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72583\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "735b186eeffb997a957075d7e610b9700b53cbe1", "tree": "1e27f0dc7f2cae492459530df208859221a1d3ca", "parents": [ "197b7c7b03bc2bbfa6a706812fa69897a3eb7cdb" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 18:28:45 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 28 23:42:48 2023 +0000" }, "message": "amd_spi100: Add new driver for AMD SPI100 controllers\n\nStart with a very simple PIO driver. Reads are slow this way, but\nwe can optimize that later. A factor of 2 is possible simply by\naligning the FIFO reads, and another factor of 3 (at least) with\nmemory-mapped reads.\n\nWe override the SPI speed but choose a conservative value to be\non the safe side. Flashrom only supports normal read commands,\nhence we won\u0027t go over 33MHz. Also, if the firmware set a lower\nspeed for normal reads, we use that. We can\u0027t use dual/quad I/O\nwith the SPI command engine, and tests have shown that increasing\nthe SPI speed lifts the read speed only marginally. It seems to\nbe limited by the FIFO reads.\n\nChange-Id: I403d5f103b3ae72f3a91829d562984c54c2e2d00\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72577\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "197b7c7b03bc2bbfa6a706812fa69897a3eb7cdb", "tree": "bf6b57efe06c818f4dbec5d54466930930fa52c0", "parents": [ "dafd51e22b30b7e13e79567c065e55d30c788fa2" ], "author": { "name": "Nicholas Chin", "email": "nic.c3.14@gmail.com", "time": "Sun Oct 23 13:10:31 2022 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Feb 25 00:42:12 2023 +0000" }, "message": "ch347_spi: Add initial support for the WCH CH347\n\nAdd support for the WCH CH347, a high-speed USB to bus converter\nsupporting multiple protocols interfaces including SPI. Currently only\nmode 1 (vendor defined communication interface) is supported, mode 2\n(USB HID communication interface) support will be added later. The code\nis currently hard coded to use CS1 and a SPI clock of 15 MHz, though\nthere are 2 CS lines and 6 other GPIO lines available, as well as a\nconfigurable clock divisor for up to 60MHz operation. Support for these\nwill be exposed through programmer parameters in later commits.\n\nThis currently uses the synchronous libusb API. Performance seems to be\nalright so far, if it becomes an issue I may switch to the asynchronous\nAPI.\n\nTested with a MX25L1606E flash chip\n\nSigned-off-by: Nicholas Chin \u003cnic.c3.14@gmail.com\u003e\nChange-Id: I31b86c41076cc45d4a416a73fa1131350fb745ba\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73106\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "019810f3fd083df5f6f61d19dda2d252709d02fe", "tree": "d9f2f1e6f8e10b6bb1d4b7f56f431f9073942fbc", "parents": [ "6d98aece44f6f3458c79160adf4dddc7f8500378" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 17:11:24 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 21 22:52:42 2023 +0000" }, "message": "chipset_enable: Optionally check PCI revision field\n\nWe used to match compatible chipset devices by vendor and device ID\nonly. On some chipsets, e.g. AMD southbridges / SoCs, this is not\nenough, though, as the device IDs are rarely updated.\n\nIn the case of AMD chipsets, we can identify the chipset with the\nrevision ID of the SMBus device. So we add that field to the chipset\nenable list.\n\nChange-Id: I4021cf8e83c605fde4360c274b39481b1e0ff070\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72573\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e7a41e3cec25165b6564b62b6aa64f90bd2dab71", "tree": "a635e566992d379fa1acca5de7fd7517e5c13580", "parents": [ "b0be3200954bebf2431c4d7bd441096f157f621e" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Mon Nov 28 17:40:56 2022 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 19 13:50:18 2023 +0000" }, "message": "tree/: Make probe_opcode() flashctx argument const\n\nProbing an opcode generally shouldn\u0027t involve mutating the flashctx\nstate and currently no probe_opcode functions do that.\n\nMake the flashctx arg const so that call sites don\u0027t need to have a\nnon-const pointer.\n\nTested: ninja test\n\nChange-Id: I19e98be50d682de2d2715417f8b7b8c62b871617\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/70030\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72543\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0cea753aff33b78051febadf8786df83144b5ee7", "tree": "8972ea6cf44e249659ddad7ea3d9aa2dedffc0b6", "parents": [ "ab9f25893f1fa87cbbaf656869e346391eccdb31" ], "author": { "name": "Aarya Chaumal", "email": "aarya.chaumal@gmail.com", "time": "Mon Jul 04 18:21:50 2022 +0530" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 19 13:50:18 2023 +0000" }, "message": "spi: Add function to probe erase command opcode for all spi_master\n\nAdd a field, probe_opcode, to struct spi_master which points to a\nfunction returning a bool by checking if a given command is supported by\nthe programmer in use. This is used for getting a whitelist of commands\nsupported by the programmer, as some programmers like ichspi don\u0027t\nsupport all opcodes.\n\nMost programmers use the default function, which just returns true.\nICHSPI and dummyflasher use their specialized function.\n\nflashrom-stable: Added `.probe_opcode` for `dirtyjtag_spi`, `ich7`.\n\nChange-Id: I6852ef92788221f471a859c879f8aff42558d36d\nSigned-off-by: Aarya Chaumal \u003caarya.chaumal@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/65183\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72539\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "aba3658513da245a61ba59cfab9dba5facdb1054", "tree": "5924d8009154e6b59aa2e10a2f66a263fcf2d358", "parents": [ "00ea3898669aa35bb3f208c1d17f34e3a5c50795" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Mon Sep 05 11:09:28 2022 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "flashrom.c: Move count_max_decode_exceeding() to cli\n\nThe count_max_decode_exceeding() function is only ever called\nwithin the cli_classic logic so move it there and make it\nstatic. This further cleans up the flashrom.c symbol namespace.\n\nChange-Id: If050eab7db8560676c03d5005a2b391313a0d642\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/68438\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72362\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b8db74a9b2bc91bb43942f7487c151bd598483b1", "tree": "8e2fdcf8c3bb95124ae1870bd7830fab6f415ee1", "parents": [ "f2a1e073434485d54172e95fc88845a2bd917636" ], "author": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Fri Aug 19 00:19:26 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "internal.c: Retype appropriate variables with bool\n\nUse the bool type instead of an integer for the variables\n`force_laptop`, `not_a_laptop`, `force_boardenable` and\n`force_boardmismatch` since this represents their purpose much better.\n\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nChange-Id: I159d789112d7a778744b59b45133df3928b8445e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66870\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72353\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "63f6a37984cf361229b433343ea9146c57a87f18", "tree": "0ebdaca6bbf8168b6bbb93da3b3be9dcc0336fe3", "parents": [ "ee3fbd7c7c05efbdea2ded8484bcfe96238f0124" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Fri Aug 12 12:56:43 2022 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "parallel.c: Consoldiate parallel master registration logic\n\nThis is analogous to spi.c and opaque.c however parallel\nlogic was previously never consoldiated.\n\nThis free\u0027s up flashrom.c from namespace pollution.\n\nTested: builds with both make and meson.\n\nChange-Id: Ie08e2e6c51ccef5281386bf7e3df439b91573974\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66651\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72349\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "58015c25eb05fa77966d1c53261a83b56a3cf6b3", "tree": "a1df11881a074c8c66de756f846be9030ce0443a", "parents": [ "e276765eca031c6900d37b22b89e686283f39c91" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Thu Apr 14 13:50:55 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "Introduce an `include` directory for header files\n\nMove all header files to the new `include` directory.\nAdapt include directives and build systems to the new directory.\n\nChange-Id: Iaddd6bbfa0624b166d422f665877f096983bf4cf\nSigned-off-by: Felix Singer \u003cfelix.singer@secunet.com\u003e\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58622\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72322\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "17affdcd24896b6bb7e73137e9d026ad66a36dfd", "tree": "4d09ab543ef7867c7f6a2fa2910be951d1e2f906", "parents": [ "4925d02f2b128d5fa79a00d434fb9298fcb6180a" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Mar 15 12:55:40 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "NEED_PCI: remove macro\n\nThe NEED_PCI macro is only used to guard prototypes. This is not needed.\n\nChange-Id: I6895b795bc96b3e251700bff4b0054407aac789a\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62834\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72320\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "19ce50d3746fb1d9e5238bac49cf88ffe654848e", "tree": "90852ac71da4bc563f5bda33dd2954cd990f1d4b", "parents": [ "6c73e27aa68e0e100f6573cd0910f6f54bff271d" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Sat Nov 13 17:59:18 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "pcidev: Move pci_dev_find() from internal to canonical place\n\nAlso rename to `pcidev_find()` in fitting with pcidev.c helpers.\n\nTested: ```sudo ./flashrom -p internal -r /tmp/bios\n\u003csnip\u003e\nFound Programmer flash chip \"Opaque flash chip\" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000.\nReading flash... done.\n```\n\nChange-Id: Ie21f87699481a84398ca4450b3f03548f0528191\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59280\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72310\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "6c73e27aa68e0e100f6573cd0910f6f54bff271d", "tree": "1aaa6f7595791fc24ee9601245607786ffd6c66d", "parents": [ "4c39c439cbe3bf1e17ca115a8571e7cfc3d8bec9" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Sat Nov 13 17:56:20 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "pcidev: Move pci_card_find() from internal to canonical place\n\nAlso rename to `pcidev_card_find()` in fitting with pcidev.c helpers.\n\nTested: ```sudo ./flashrom -p internal -r /tmp/bios\n\u003csnip\u003e\nFound Programmer flash chip \"Opaque flash chip\" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000.\nReading flash... done.\n```\n\nChange-Id: I026bfbecba114411728d4ad1ed8969b469fa7d2d\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59279\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72309\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "48a946673fa770a9224c2b79a8f8440c51b109ed", "tree": "62f3bd1fee1f4e6cf45d42011d2dcbb435ca028e", "parents": [ "15004ba11d6c3b86c7824bb30a630c81e94cc9a4" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Sat Feb 26 11:36:17 2022 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "pcidev: Move scandev_inclass logic from internal to pcidev\n\nTested: ```sudo ./flashrom -p internal -r /tmp/bios\n\u003csnip\u003e\nFound Programmer flash chip \"Opaque flash chip\" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000.\nReading flash... done.\n```\n\nChange-Id: I1978e178fb73485f1c5c7e732853522847267cee\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59277\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72302\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "15004ba11d6c3b86c7824bb30a630c81e94cc9a4", "tree": "8b6e88754b57846124a67a8d171d7bfa9647e68b", "parents": [ "d58496b41eec27f52804c0dc6573a8612f2f0ec6" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Sat Nov 13 13:14:06 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "pcidev: Avoid internal programmer relying on pacc global\n\nMake progress towards the goal of removing pacc from global\nstate as noted in the FIXME of programmer.h\n\nTested: ```sudo ./flashrom -p internal --flash-size\n\u003csnip\u003e\nFound Programmer flash chip \"Opaque flash chip\" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000.\n16777216\n```\n\nChange-Id: Id83bfd41f785f907e52a65a6689e8c7016fc1b77\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59275\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72300\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "74b4aa0b15439a2ab2474889a7abed978439757a", "tree": "a3e6d01052b04bbae7c71af7c1148d3619ba1ab1", "parents": [ "b3287b43dc2fc90913686eb7ca9adfdedac2fdb4" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Dec 14 17:52:30 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "physmap: rename to hwaccess_physmap, create own header\n\nLine up physmap with the other hwaccess related code.\n\nChange-Id: Ieba6f4e94cfc3e668fcb8b3c978de5908aed2592\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60113\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72267\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b3287b43dc2fc90913686eb7ca9adfdedac2fdb4", "tree": "5432e2d6675b9f389ad95bf47f4e2e7decd5807f", "parents": [ "a065520a7c7eedcca961de1fc891cc0b04e6df77" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Dec 14 17:25:49 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "hwaccess physmap: move x86 msr related code into own files\n\nAllow x86 msr related code to be compiled independent from memory\nmapping functionality. This enables for a better selection of needed\nhardware access types.\n\nflashrom-stable: Squashed fixup for FreeBSD\n\nChange-Id: Idc9ce9df3ea1e291ad469de59467646b294119c4\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60111\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72266\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a065520a7c7eedcca961de1fc891cc0b04e6df77", "tree": "f7a4c280f6d3114b98a52e147f988c4ae293271b", "parents": [ "d96c97c77309f1cf1ff1cbe9fa521a75fc9d5698" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Dec 14 16:36:05 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "hwaccess: move x86 port I/O related code into own files\n\nAllow port I/O related code to be compiled independent from memory\nmapping functionality. This enables for a better selection of needed\nhardware access types.\n\nChange-Id: I372b4a409f036da766c42bc406b596bc41b0f75a\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60110\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72265\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e6953e56ffd5149c721a9bfcae01bf978d8b2d51", "tree": "4811713ce12d2e608852f005aba5631a3bf41d2b", "parents": [ "c63d9184aaef45d5a970f045ae901bf9f7221108" ], "author": { "name": "Anastasia Klimchuk", "email": "aklm@chromium.org", "time": "Thu Aug 26 10:10:32 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "par_master: Add shutdown function in par_master struct\n\nWith this, register_par_master can take care of register_shutdown\nas well, and every par master only needs to call\nregister_par_master instead of calling both register_par_master\nand register_shutdown.\n\nNext patches in the chain convert par masters to use new API.\n\nTested: builds and ninja test\n\nChange-Id: I0fee15d548cdd16678e551eeb351e659812ddf76\nSigned-off-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/57154\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72232\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a1fed9ffe3bf81d7a605c2be9e979b0e0804d28b", "tree": "62c1523995763a4c1705ad8e21141a2033dd2bce", "parents": [ "fd3a225fa747f56402a942c1111db2d379df4421" ], "author": { "name": "Anastasia Klimchuk", "email": "aklm@chromium.org", "time": "Tue Aug 03 14:08:02 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "opaque_master: Add shutdown function in opaque_master struct\n\nWith this, register_opaque_master can take care of register_shutdown\nas well, and every opaque master only needs to call\nregister_opaque_master instead of calling both register_opaque_master\nand register_shutdown.\n\nNext patches in the chain convert opaque masters to use new API.\n\nTested: builds and ninja test from CB:56413\n\nChange-Id: I34183e6bafc787eec54ee4a26b73a40803f3ce99\nSigned-off-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/56823\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72229\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7783f2f39397cc3fad701f6bc5eaf8fa80e2e3ca", "tree": "e6334627f11526c27e3e1d77da367e7e2caf5e69", "parents": [ "f48ede4eb133f9cd44b3a2a4a98ea821611d74ae" ], "author": { "name": "Anastasia Klimchuk", "email": "aklm@chromium.org", "time": "Mon Jul 05 09:18:06 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "spi_master: Add shutdown function in spi_master struct\n\nWith this, register_spi_master can take care of register_shutdown\nas well, and every spi master only needs to call register_spi_master\ninstead of calling both register_spi_master and register_shutdown.\n\nTesting:\nIn dummyflasher, comment out free(data) in shutdown. Test fails with error:\n../dummyflasher.c:949: note: block 0x55e0727a6e40 allocated here\nERROR: dummy_init_and_shutdown_test_success leaked 1 block(s)\nMeans, shutdown function is invoked for drivers with \"old\" API\n(so, transitioning from old to new API is not breaking anything).\n\nNext patches in the chain converts spi masters to use new API.\n\nTested: builds and ninja test\n\nChange-Id: I2dc80dceca2f8204bcd0dad1f51753d7e79f1af5\nSigned-off-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55932\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72226\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "21b20218a6128c1880eceb634101df176b56692d", "tree": "84402bf4e4ac933b023ac6e1c56f4a693ef522bc", "parents": [ "b91a203091fc43824bc57f3c8e2db0bcc311da59" ], "author": { "name": "Anastasia Klimchuk", "email": "aklm@chromium.org", "time": "Thu May 13 12:28:47 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "programmer: Smoothen register_opaque_master() API\n\nIt was impossible to register a const struct opaque_master that would\npoint to dynamically allocated `data`. Fix that so that we won\u0027t\nhave to create more mutable globals.\n\nChange-Id: Id3adb4cf04ae04dbe87ddb96f30871cb5f7c8ff0\nSigned-off-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54170\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72202\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b91a203091fc43824bc57f3c8e2db0bcc311da59", "tree": "8fffff062afae6b9ce853c69a6636bc33bcabbbc", "parents": [ "03f3a6d13e8bd62ef84ef6a4a6f21d6fb8b2a7b8" ], "author": { "name": "Anastasia Klimchuk", "email": "aklm@chromium.org", "time": "Fri May 21 09:40:58 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "programmer: Smoothen register_par_master API\n\nIt was impossible to register a const struct par_master that would\npoint to dynamically allocated `data`. Fix that so that we won\u0027t\nhave to create more mutable globals.\n\nChange-Id: I95bc92f6c54c5bcdac1c522ca87054aaffed0f40\nSigned-off-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54169\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72201\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5e08e3e829e3f736e18cef7b8f4a8929c9e06257", "tree": "cfe9483275582e2ff2a50628824cf8e842c1feef", "parents": [ "6c33185c81f4aab0d048be7c4b68dca1a91800c2" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue May 11 17:38:14 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "programmer: Smoothen register_spi_master() API\n\nIt was impossible to register a const struct spi_master that would\npoint to dynamically allocated `data`. Fix that so that we won\u0027t\nhave to create more mutable globals.\n\nChange-Id: I0c753b3db050fb87d4bbe2301a7ead854f28456f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54066\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72179\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e28d8e4e2332054fb4b7f61e8ce03f316e3a63f3", "tree": "dcd1df2c485d8da20c2845e584bd157e0e4f63fb", "parents": [ "6a2ebebfabff9ae72f8f03076b015a6b21bf8b90" ], "author": { "name": "Jean THOMAS", "email": "virgule@jeanthomas.me", "time": "Tue Oct 11 17:54:30 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "dirtyjtag: Add DirtyJTAG programmer\n\nAdd a new programmer driver for the DirtyJTAG project (a USB-JTAG\nfirmware for STM32 MCUs).\n\nSuccessfully tested with DirtyJTAG 1.4 running on an Olimex STM32-H103\ndevelopment board and a SST25VF020B SPI flash chip.\n\nChange-Id: Ic43e9a014ed7d04e429e73b30c9dcfdde1a78913\nSigned-off-by: Jean THOMAS \u003cvirgule@jeanthomas.me\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/67878\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71492\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d1ab7d2bb0c4ea7be2e251caa564ab91d27ee7ea", "tree": "905816b92fb3759fcb82767cb94b49d6e0f02594", "parents": [ "8cfc7377ffa880659660b344e97333986aba9130" ], "author": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Fri Aug 19 03:03:47 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "tree: Retype variable `laptop_ok` with bool\n\nUse the bool type instead of an integer for the variable `laptop_ok`,\nsince this represents its purpose much better.\n\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nChange-Id: I5d9fc3516bc2d29f11b056e35b3e5e324ce93423\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66891\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71485\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "980d6b8d712d26711dcd5a71007e4626c7198cd5", "tree": "38e926243e6a10734971066fd1602d373fd04784", "parents": [ "f25447e5724bd8664338b69b12399f101abed76b" ], "author": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Fri Aug 19 02:48:15 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "tree: Retype variable `programmer_may_write` with bool\n\nUse the bool type instead of an integer for the variable\n`programmer_may_write`, since this represents its purpose much better.\n\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nChange-Id: I69958527ae018a92f1c42734a7990d0c532dee0c\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66885\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71483\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "2ab6bba5602a8a2f7e0a99cc94ccc9fe6a412723", "tree": "65cb4b8a6c7de64b6dbf1a41cc333ac4259831a1", "parents": [ "43040f297e68cd4d826d58f57566581ef902d179" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Fri Jun 24 16:48:09 2022 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "it85spi: EOL support\n\nThis code was originally introduced by ITE for now exceedingly old\nChromebooks. The code has had very little attention to maintain it,\nunlikely tested for a long time and now seems to be just a technical\nburden to the flashrom project.\n\nIf someone is later interested it could be resurrected for reference\nfrom git history. However, it needs quite a bit of work to bring it back\ninto maintainable order.\n\nTested: tree builds under meson+make and unit tests pass.\n\nChange-Id: I5e8cafd73db837941c518f0e2d72d8192274fd79\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/65378\nOriginal-Reviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71467\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e57d4e49fd2556f0fe267833d35cc57b7e252c06", "tree": "ef260430367f0d2025fd6c5c12c101f37639613e", "parents": [ "672bdcfd4ffeb065b7056042769e3cc512d87c06" ], "author": { "name": "Werner Zeh", "email": "werner.zeh@siemens.com", "time": "Mon Jan 03 09:44:29 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "Add Elkhart Lake support\n\nElkhart Lake has a chipset called Mule Creek Canyon which is quite\ncompatible with 300 series chipsets. There are a few differences though,\ne.g. different encoding for the SPI clock values for read and write in\nthe FLCOMP register. In addition Elkhart Lake has a new PCI device ID\nfor the SPI controller which is added, too.\n\nTested: Read and flash complete flash on Siemens MC EHL1\n\nChange-Id: I711e39a3ec9cd7098389231eaa1cb864d615a475\nSigned-off-by: Werner Zeh \u003cwerner.zeh@siemens.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60711\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71443\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5c9f542bf8ce514c628c59e42e35fbcb615d8937", "tree": "bcc2215bccd5a34f07460ff0f680aa7fba224744", "parents": [ "cce1e5b8636ebef59dd509680594e17b0a207857" ], "author": { "name": "Michał Żygowski", "email": "michal.zygowski@3mdeb.com", "time": "Wed Jun 16 15:13:54 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "Add Tiger Lake U Premium support\n\nTiger Lake has very low ICCRIBA (TGL\u003d0x11, CNL\u003d0x34 and CML\u003d0x34) and\ndetects as unknown chipset compatible with 300 series chipset. Add a\nnew enum CHIPSET_500_SERIES_TIGER_POINT and treat it identically to\nCHIPSET_400_SERIES_COMET_POINT. There are some exceptions though,\nICCRIBA is no longer present n descriptor content so a new union has\nbeen defined for new fields and used in descriptor guessing.\nfreq_read field is not present on Tiger Lake, moreover in CannonPoint\nand Comet Point this field is used as eSPI/EC frequency, so a new\nfunction to print read frequency has ben added. Finally Tiger lake\nboot straps include eSPI, so a new bus has been added for the new\nstraps.\n\nTested: Flash BIOS region on Intel i5-1135G7\n\nSigned-off-by: Michał Żygowski \u003cmichal.zygowski@3mdeb.com\u003e\nChange-Id: I28f3b6fe9f8ce9e976a6808683f46b6f4ec72bdd\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55578\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71437\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "cce1e5b8636ebef59dd509680594e17b0a207857", "tree": "5f50e5444c3d46b785af7e086ff60159bdf72250", "parents": [ "fa959bacf06a1db31cc82b5d601cc208faf11859" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Nov 02 20:33:35 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "hwaccess.c: move function declarations from programmer.h to hwaccess.h\n\nMove declarations for functions implemented in hwaccess.c from\nprogrammer.h to hwaccess.h.\n\nChange-Id: I075fd86211c766ae3d5f29c76adbd7c5b9bdbd80\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58865\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71436\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "1535db44bdc06e6cf52defc519af86197ca414e5", "tree": "a7dc07bfbbf2236cab7941ebb5e7909fae124de9", "parents": [ "8a03c90f41a6ca79c7bf183ad07e2b30702bfd46" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.de", "time": "Mon Jun 14 13:20:09 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "programmer.h: sort programmer entries alphabetically\n\nChange-Id: Ie419eac2719aceb3aea803fac8ce85de294c88e5\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55495\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71387\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "40d3233e17e07f7616702b9968468816f4db9520", "tree": "b6b11594742374e50aee4b6afe45a4492c7fa904", "parents": [ "ab69629daab4c091870b3f7d27f80085a415b286" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.de", "time": "Thu Jun 10 15:17:53 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "programmer.h: remove compile guard from programmer drivers\n\nThe definition of external structs doesn\u0027t have to be guarded.\nSee discussion under review.coreboot.org/52946.\n\nChange-Id: I01e6a785269c3e0bd648eeaee217a7a855ab0853\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55387\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71383\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3795c9d43d0b6ea71fb7ec499f6fdbb5e5bf0960", "tree": "95c8c787f2e7010cd2c293767b8ffe94b7f259f1", "parents": [ "84e9c913082ce2d243593e3659ec3a0af22ea9cd" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.de", "time": "Tue Jun 01 16:25:52 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "enum programmer: not needed anymore. Remove\n\nChange-Id: I53cdb160616911a4beea6b5e8e56d582621818a4\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55124\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71381\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e0e93cf59fe2fb45f1e325e0dcc939cc054cbfa8", "tree": "38f1faaae8d2a12dba5a80bad703e3d2c8d68c9e", "parents": [ "9163b814032c566b224ee8e58742448a99a3b73d" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.de", "time": "Tue Jun 01 14:37:12 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "programmer_init: use struct programmer_entry*\n\nChange-Id: Iacf0f25abc94a84c5d52c8d69a3e8640817b060a\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55121\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71378\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "cc853d84ed2f8ecafc1f6daa443f8baa4c871805", "tree": "8e5f3e0b7a75d272a109e20af5aeeeec11dfebf7", "parents": [ "7e1345602641114c8eeb5cfef992bf1da8d7fa6a" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.de", "time": "Tue May 04 15:32:17 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "programmer_table: move each entry to the associated programmer source\n\nChange-Id: I3d02bd789f0299e936eb86819b3b15b5ea2bb921\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52946\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71373\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "633d6db1b5718305cf4daf87cf4a93d17bc3821e", "tree": "59ec962a28ab34ea99554db9b44ec804fead7e2d", "parents": [ "bbfacffca88042d7f85d910b732bf88253573c76" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.de", "time": "Wed Mar 31 19:09:44 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "programmer_table: convert entries to pointers\n\nAllows us to move the individual entries into their respective\ndriver files.\n\nChange-Id: Ifbb0ee4db5a85b1cd2afeafe4dca838579f79878\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52945\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71369\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d0fcce2507d7a5ada93902cc7522ee06e91c4872", "tree": "52643af250240e68608a311a51b54cd8cc4b91fb", "parents": [ "b7076368df57398d36146d0234f924b0be9db881" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.de", "time": "Wed May 19 13:53:34 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "programmer_table: add table size constant\n\nMakes the array size known to other compilation units.\n\nChange-Id: Idacb4b7b0dd98af8bc7cbecf567d33daafb4b24d\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55116\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71367\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "4db0fdfdcb59f94e41c0967375c899e2d274e113", "tree": "5866347a6c5e63477f8e05cc32443085319c2df3", "parents": [ "771bb7952a91722d2d9f100e19b0566f06298126" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Fri Jul 10 17:04:10 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "Add Gemini Lake support\n\nThe SPI hardware is pretty much unchanged from Apollo Lake. However, the\nIFD differs significantly enough to require special handling.\n\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nChange-Id: Ib5dcdf204166f44a8531c19b5f363b851d2ccd77\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54276\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71354\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0b1fb92b5e6e3a057709ab3b82032f81f2b564ec", "tree": "3609203b1b63c9c38c3b32a6e87a4e95344b39f4", "parents": [ "c14e3f6bd806c193741bb17815ad8d5d98b7ee38" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Fri Jan 08 09:08:54 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "programmer: remove unused noop_shutdown function\n\nFunction appears to be vestigial.\n\nflashrom-stable: Squashed fixup\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I1b67223aed8be54b60771aa1b2d498836ed28060\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/49631\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71337\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "0a84d0d6950fef06ea0c0b0d220f9a97d2a958f0", "tree": "71dd9f05f2cd069305f7d2cb1877ad5ba9f8ed5d", "parents": [ "3b3fc9344d6cfd29007545826ecaf1e483b4bed4" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Tue Nov 24 18:05:02 2020 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "programmer.h,c: Drop dead noop_chip_writeb() fn\n\nDrop dead code.\n\nTested: `git grep noop_chip_writeb`\n\nChange-Id: I160406df903b3b0a49a5ff3ec78a030e10fa60a0\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/47894\nOriginal-Reviewed-by: Sam McNally \u003csammc@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71331\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "13f90e64821fb8af412c7d692c72d2663dc9ce04", "tree": "9093a2c7001756fb3d5fde006f6fddfbb1664867", "parents": [ "e19a41b5411c1a693ad81e9b138ac7d474bad495" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Wed Jan 06 14:10:52 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "tree/: Drop const from opaque data ptr in master definitions [alt]\n\nThe opaque data pointer need not necessarily have constant\ndata for the life-time of the specific master. This is because\nthe data field purpose is for the master to use as it sees fit\nfor managing its own internal state and therefore we should not\nconstrain this as being RO data at init time.\n\nflashrom-stable:\nAdd cast in bitbang_spi to avoid compiler warning.\n\nChange-Id: I686c3c79547e35d48f3fd0b524fc98c176dcea6e\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/49131\nOriginal-Reviewed-by: Sam McNally \u003csammc@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71336\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "5eca427ae64519b70d1c4ccfb427305ca9974ba0", "tree": "1ca22ef1e0072a76650fdd182206844f8ebddd7d", "parents": [ "1bbc501f79319cc6c8d839bc44fa55e96afab33a" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Sun Apr 12 17:27:53 2020 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:34 2022 +0100" }, "message": "const\u0027ify flashctx to align signatures with cros flashrom\n\nThe ChromiumOS flashrom fork has since const\u0027ify flashctx\nin a few places. This aligns the function signatures to\nmatch with downstream to ease forward porting patches\nout of downstream back into mainline flashrom.\n\nThis patch is minimum viable alignment and so feedback is\nwelcome.\n\nChange-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70933\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "324929c3d725ce264b2390525dbc9070f6029cc4", "tree": "73ee656c8bc1933329e4239214e4b0eaaadb36f8", "parents": [ "728062f7ff7c2dca31bc99fe45eb5cacd7cf2d53" ], "author": { "name": "Miklós Márton", "email": "martonmiklosqdev@gmail.com", "time": "Thu Aug 01 19:14:10 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Dec 31 17:25:41 2019 +0000" }, "message": "Add support for STLINK V3 debugger/programmer via its SPI bridge\n\nChange-Id: Icffab87ac8f2c570187ed753ec70f054541873a4\nSigned-off-by: Miklós Márton \u003cmartonmiklosqdev@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34661\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "2d20d6db39547f013b66230f378ceb8e21fa36e3", "tree": "7816f91833c2540ec74f97fe5de4ad4dd81165e0", "parents": [ "1a119498b43a8ed934bcfa0a16465aa4d6d2c74d" ], "author": { "name": "Miklós Márton", "email": "martonmiklosqdev@gmail.com", "time": "Tue Jan 30 20:20:15 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Nov 14 22:40:21 2019 +0000" }, "message": "Add support for National Instruments USB-845x devices\n\nChange-Id: I9477b6f0193bfdf20bbe63421a7fb97b597ec549\nSigned-off-by: Miklós Márton \u003cmartonmiklosqdev@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/25683\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "1c091d1aebb055149c89f88fd5766ca4e33b7b3e", "tree": "1ca7c754bcaaf1b9e8150af14af58a8a609838bf", "parents": [ "15f539c8c978e002f2b6397a7a74e1af817d5cb3" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Mon Aug 12 11:14:14 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Sep 24 19:02:48 2019 +0000" }, "message": "internal: Fix board vendor and model memory leaks\n\nThe board vendor and model are sometimes specified as arguments during\nan internal flash, so make sure they are freed at the end of\ninitialization.\n\nChange-Id: I9f43708f3b075896be67acec114bc6f390f8c6ca\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nFound-by: Coverity CID 1230664, 1230665\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34846\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "5ec84b3c096c9ace0bf3650206a0a9412e977c64", "tree": "473c877a4c2901830e7a8005aa45b07d50323e9d", "parents": [ "045b97ebd97426b70706db7338a7fd76790b8781" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Mar 19 17:00:03 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:29:24 2019 +0000" }, "message": "chipset_enable: Add support for discrete Cannon Lake PCHs\n\nThe Cannon Lake \"300 Series\" PCHs [1,2] share the register layout of the\nSkylake \"100 Series\". Mark them as BAD until `ichspi.c` is adapted.\n\n[1] Intel(R) 300 Series and Intel(R) C240 Series\n Chipset Family Platform Controller Hub\n Datasheet - Volume 1 of 2\n Revison 4 (Dec 2018)\n Document Number 337347\n\n[2] Intel(R) 300 Series Chipset Families Platform Controller Hub\n Datasheet - Volume 2 of 2\n Revision 2? (Oct 2018)\n Document Number 337348\n\nChange-Id: If0b54799d5b93169ee660409bad57ae14677340c\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34071\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\nReviewed-by: Jeremy Soller \u003cjackpot51@gmail.com\u003e\n" }, { "commit": "519be66fc59558971dd653afe69ccaf1a633b492", "tree": "74f0912de156a86d56111f377db080246e5205e9", "parents": [ "ef78de4a21323b8c459337356289218211f2c5ce" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 23 20:03:35 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jul 31 08:26:59 2019 +0000" }, "message": "Fix -Wsign-compare trouble\n\nMostly by changing to `unsigned` types where applicable, sometimes\n`signed` types, and casting as a last resort.\n\nChange-Id: I08895543ffb7a48058bcf91ef6500ca113f2d305\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30409\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\n" }, { "commit": "3750986348cb99b8f0d828b73972b545a2f9c878", "tree": "62b7c2d2a5b84561596fdbbeddc6111d27dfc315", "parents": [ "908adf4589d34eaf3bd8395afa52aed8c8887cfd" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Jan 18 14:23:02 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jul 06 17:15:58 2019 +0000" }, "message": "chipset_enable: Add Apollo Lake\n\nIt works the same as 100 series PCHs and on. The SPI device is at\n0:0d.2, though. Mark as BAD until `ichspi` is revised.\n\nChange-Id: I7b1ad402ba562b7b977be111f8cf61f1be50843a\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30994\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\n" }, { "commit": "deeac7e41a311a0806af0e65a2ce5c6673f9cf92", "tree": "2ff1082bf9ed049c2863deff9a6d66b6980b1812", "parents": [ "959aafa53eeae4f22766b9d098e5ca952af8c070" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Apr 22 00:09:42 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 27 10:25:15 2019 +0000" }, "message": "spi: Drop spi_controller type\n\nNot needed anymore. Drop it fast before it encourages anyone to\nviolate layers again!\n\nChange-Id: I8eda93b429e3ebaef79e22aba76be62987e496f4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33651\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "cb44eb7dad17522f47792dca4fc499310ff7d6f3", "tree": "026822102436ac0dcda8d8d007f16757ad73488b", "parents": [ "712ba3a0659a70c2e93a55d9e194b2fae6db28d1" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Apr 22 00:09:42 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 23 13:06:51 2019 +0000" }, "message": "bitbang_spi: Drop bitbang_spi_master_type\n\nIt only existed to make maintenance harder and waste our time.\n\nChange-Id: I7a3b5d9ff1e99d2d4f873c6f19fb318f93762037\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33638\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "2e50cdc494bf4e44c01e9e331b82a3633b1d9ef2", "tree": "78a7f9d9a0dd67f97d25e60c02a10e9785590fbf", "parents": [ "ba22411335f26601a76dbdf0d74a71e932b7cff8" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Sep 23 20:20:26 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 06 15:54:46 2019 +0000" }, "message": "Rework internal bus handling and laptop bail-out\n\nWe used to bail out on any unknown laptop. However, modern systems with\nSPI flashes don\u0027t suffer from the original problem. Even if a flash chip\nis shared with the EC, the latter has to expect the host to send regular\nJEDEC SPI commands any time.\n\nSo instead of bailing out, we limit the set of buses to probe. If we\nsuspect to be running on a laptop, we only allow probing of SPI and\nopaque programmers. The user can still use the existing force options\nto probe all buses.\n\nThis will obsolete some board-enables that could be moved to `print.c`\nin follow-up commits.\n\nChange-Id: I1dbda8cf0c10d7786106f14f0d18c3dcce35f0a3\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/28716\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\n" }, { "commit": "dc5af547df8b2f852deb5ddad86bb90ff0fc50c0", "tree": "3b23dcce1e43e520ca0a6db314d6920a89b1f72a", "parents": [ "3d7b1e3b5c04304d3680bd950e7672f6336b01d6" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 22 16:54:59 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 02 16:55:43 2019 +0000" }, "message": "dediprog: Disable 4BA completely\n\nThis is an interim solution. We\u0027ll have to enable 4BA step-by-step for\neach dediprog protocol version.\n\nChange-Id: I08efcbb09ab3499ef6902a698e9ce3d6232237c4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30386\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "3578ec6a3d7187438c4093f4bb7ac2bb6d4184cb", "tree": "53c7ccc03fa21dcd4664e6fb1b48a9ec1661e023", "parents": [ "9cecc7e25dc3fe27a801a745410825cfc2cfaac3" ], "author": { "name": "Marc Schink", "email": "flashrom-dev@marcschink.de", "time": "Thu Mar 17 16:23:03 2016 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jan 05 16:25:04 2019 +0000" }, "message": "Add initial J-Link SPI programmer\n\nTested with SEGGER J-Link EDU, Flasher ARM and flash chip W25Q16.V.\n\nChange-Id: Ie03a054a75457ec9e1cab36ea124bb53b10e8d7e\nSigned-off-by: Marc Schink \u003cflashrom-dev@marcschink.de\u003e\nReviewed-on: https://review.coreboot.org/c/28087\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "1d507a07a919f49e74aa05803bf37919ac95adb1", "tree": "24d460c41877990f4a6724c0e8b4513e2d679daa", "parents": [ "ccfa8f9d9a68b1e4238d2dbbc4e9c8bcf9bae8a6" ], "author": { "name": "Daniel Thompson", "email": "daniel.thompson@linaro.org", "time": "Thu Jul 12 11:02:28 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 30 09:53:58 2018 +0000" }, "message": "usbdev: Extract libusb1 device discovery into a separate file\n\nCurrently there is a TODO-like comment in the dediprog driver: \"Might be\nuseful for other USB devices as well\". Act on this comment by collecting\nall the device discovery code for libusb1 devices into a separate file.\n\nChange-Id: Idfcc79371241c2c1dea97faf5e532aa971546a79\nSigned-off-by: Daniel Thompson \u003cdaniel.thompson@linaro.org\u003e\nReviewed-on: https://review.coreboot.org/27443\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "45e91a278cd31019ad6ed5a465661001fbaee065", "tree": "c8cf0b31e69ff5efae8c283369fc67aeab4a6e5c", "parents": [ "455a6fc86e833d1165c68d9dbaef8b0188875bc5" ], "author": { "name": "Daniel Thompson", "email": "daniel.thompson@linaro.org", "time": "Mon Jun 04 13:46:29 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Aug 17 21:17:13 2018 +0000" }, "message": "programmer: Add Developerbox/CP2104 bit bang driver\n\nThe 96Boards Developerbox (a.k.a. Synquacer E-series) provides a CP2102\ndebug UART with its GPIO pins hooked up to the SPI NOR FLASH. The\ncircuit is intended to provide emergency recovery functions without\nrequiring any additional tools (such as a JTAG or SPI programmer). This\nwas expected to be very slow (and it is) but CP2102 is much cheaper than\na full dual channel USB comms chip.\n\nRead performance is roughly on par with a 2400 baud modem (between 60\nand 70 minutes per megabyte if you prefer) and write performance is 50%\nslower still. The full recovery process, with backup and verification of\n4MB data written takes between 14 and 15 hours. Thus it is only really\npractical as an emergency recovery tool, firmware developers will need\nto use an alternative programmer.\n\nChange-Id: I2547a96c1a2259ad0d52cd4b6ef42261b37cccf3\nSigned-off-by: Daniel Thompson \u003cdaniel.thompson@linaro.org\u003e\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/26948\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\n" }, { "commit": "b623f403a00a6ce796fe632d4c1ff3fc4f5a5e40", "tree": "a2f753c253a18afe6cb09134b9a15d26eca3233b", "parents": [ "9891b75d96a199d1740fbd7df805abf23ae8f347" ], "author": { "name": "Daniel Thompson", "email": "daniel.thompson@linaro.org", "time": "Tue Jun 05 09:38:19 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Aug 17 21:16:12 2018 +0000" }, "message": "bitbang_spi: Add functions to optimize xfers\n\nOn systems where the overhead of getting/setting pins is much greater\nthan the half period (for example, USB bit banging) it significantly\nboosts performance if we can bang more than one bit at the same time.\nAdd support for setting sck at the same time as mosi or miso activity.\n\nThe speed up varies depending on how much the overhead of\ngetting/setting pins dominates execution time. For a USB bit bang driver\nrunning on a 7th generation Core i5, the time to probe drops from ~9.2\nseconds to ~7.7 seconds when set_clk_set_mosi() is implemented.\n\nChange-Id: Ic3430a9df34844cdfa82e109456be788eaa1789a\nSigned-off-by: Daniel Thompson \u003cdaniel.thompson@linaro.org\u003e\nReviewed-on: https://review.coreboot.org/26946\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\nReviewed-by: Idwer Vollering \u003cvidwer@gmail.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "b2154e8a1d456875122cbbff2a18e5e1c55ef4d2", "tree": "ee5cf1e29adf35b89d6078ba117638b4009cfd89", "parents": [ "ac01baa073b0f154ffd3ffdc7c9e75987f8b525c" ], "author": { "name": "Lubomir Rintel", "email": "lkundrak@v3.sk", "time": "Sun Jan 14 17:35:33 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 26 10:02:38 2018 +0000" }, "message": "digilent_spi: add a driver for the iCEblink40 development board\n\nThis is driver that supports the Lattice iCE40 evaluation kits. On the\nboard is a SPI flash memory chip labeled ST 25P10VP.\n\nTested to work read/write/erase with \"-p digilent_spi -c M25P10\" or\nwith a patch that resets the part beforehands (in which case it gets\ndetected as a M25P10-A and is way faster due to paged writes).\n\nChange-Id: I7ffcd9a2db4395816f0e8b6ce6c3b0d8e930c9e6\nSigned-off-by: Lubomir Rintel \u003clkundrak@v3.sk\u003e\nReviewed-on: https://review.coreboot.org/23338\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f9a30554803a670f9b95a7794be00f03929d6ecd", "tree": "46da1dafce0c76ab5730540540aaf4093463f551", "parents": [ "291764a70e6d8b212680e311bfb0825abf2b9a2f" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Sat May 23 20:30:30 2015 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Thu May 17 16:49:16 2018 +0000" }, "message": "linux_mtd: Import driver from ChromiumOS\n\nThis imports a series of patches from chromiumos for MTD support.\nThe patches are squashed to ease review and original Change-Ids have\nbeen removed to avoid confusing Gerrit.\n\nThere are a few changes to integrate the code:\n- Conflict resolution\n- Makefile changes\n- Remove file library usage from linux_mtd. We may revisit this and use\n it for other Linux interfaces later on.\n- Switch to using file stream functions for reads and writes.\n\nThis consolidated patch is\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\n\nThe first commit\u0027s message is:\nInitial MTD support\n\nThis adds MTD support to flashrom so that we can read, erase, and\nwrite content on a NOR flash chip via MTD.\n\nBUG\u003dchrome-os-partner:40208\nBRANCH\u003dnone\nTEST\u003dread, write, and erase works on Oak\n\nSigned-off-by: David Hendricks \u003cdhendrix@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/272983\nReviewed-by: Shawn N \u003cshawnn@chromium.org\u003e\n\nThis is the 2nd commit message:\n\nlinux_mtd: Fix compilation errors\n\nThis fixes compilation errors from the initial import patch.\n\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\n\nThis is the 3rd commit message:\n\nlinux_mtd: Suppress message if NOR device not found\n\nThis just suppresses a message that might cause confusion for\nunsuspecting users.\n\nBUG\u003dnone\nBRANCH\u003dnone\nTEST\u003dran on veyron_mickey, \"NOR type device not found\" message\nno longer appears under normal circumstances.\nSigned-off-by: David Hendricks \u003cdhendrix@chromium.org\u003e\n\nReviewed-on: https://chromium-review.googlesource.com/302145\nCommit-Ready: David Hendricks \u003cdhendrix@chromium.org\u003e\nTested-by: David Hendricks \u003cdhendrix@chromium.org\u003e\nReviewed-by: Shawn N \u003cshawnn@chromium.org\u003e\n\nThis is the 4th commit message:\n\nlinux_mtd: Support for NO_ERASE type devices\n\nSome mtd devices have the MTD_NO_ERASE flag set. This means\nthese devices don\u0027t require an erase to write and might not have\nimplemented an erase function. We should be conservative and skip\nerasing altogether, falling back to performing writes over the whole\nflash.\n\nBUG\u003db:35104688\nTESTED\u003dZaius flash is now written correctly for the 0xff regions.\n\nSigned-off-by: William A. Kennington III \u003cwak@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/472128\nCommit-Ready: William Kennington \u003cwak@google.com\u003e\nTested-by: William Kennington \u003cwak@google.com\u003e\nReviewed-by: Brian Norris \u003cbriannorris@chromium.org\u003e\n\nThis is the 5th commit message:\n\nlinux_mtd: do reads in eraseblock-sized chunks\n\nIt\u0027s probably not the best idea to try to do an 8MB read in one syscall.\nTheoretically, this should work; but MTD just relies on the SPI driver\nto deliver the whole read in one transfer, and many SPI drivers haven\u0027t\nbeen tested well with large transfer sizes.\n\nI\u0027d consider this a workaround, but it\u0027s still good to have IMO.\n\nBUG\u003dchrome-os-partner:53215\nTEST\u003dboot kevin; `flashrom --read ...`\nTEST\u003dcheck for performance regression on oak\nBRANCH\u003dnone\n\nSigned-off-by: Brian Norris \u003cbriannorris@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/344006\nReviewed-by: David Hendricks \u003cdhendrix@chromium.org\u003e\n\nThis is the 6th commit message:\n\nlinux_mtd: make read/write loop chunks consistent, and documented\n\nTheoretically, there should be no maximum size for the read() and\nwrite() syscalls on an MTD (well, except for the size of the entire\ndevice). But practical concerns (i.e., bugs) have meant we don\u0027t quite\ndo this.\n\nFor reads:\nBug https://b/35573113 shows that some SPI-based MTD drivers don\u0027t yet\nhandle very large transactions. So we artificially limit this to\nblock-sized chunks.\n\nFor writes:\nIt\u0027s not clear there is a hard limit. Some drivers will already split\nlarge writes into smaller chunks automatically. Others don\u0027t do any\nsplitting. At any rate, using *small* chunks can actually be a problem\nfor some devices (b:35104688), as they get worse performance (doing an\ninternal read/modify/write). This could be fixed in other ways by\nadvertizing their true \"write chunk size\" to user space somehow, but\nthis isn\u0027t so easy.\n\nAs a simpler fix, we can just increase the loop increment to match the\nread loop. Per David, the original implementation (looping over page\nchunks) was just being paranoid.\n\nSo this patch:\n * clarifies comments in linux_mtd_read(), to note that the chunking is\n somewhat of a hack that ideally can be fixed (with bug reference)\n * simplifies the linux_mtd_write() looping to match the structure in\n linux_mtd_read(), including dropping several unnecessary seeks, and\n correcting the error messages (they referred to \"reads\" and had the\n wrong parameters)\n * change linux_mtd_write() to align its chunks to eraseblocks, not page\n sizes\n\nNote that the \"-\u003epage_size\" parameter is still somewhat ill-defined, and\nonly set by the upper layers for \"opaque\" flash. And it\u0027s not actually\nused in this driver now. If we could figure out what we really want to\nuse it for, then we could try to set it appropriately.\n\nBRANCH\u003dnone\nBUG\u003db:35104688\nTEST\u003dvarious flashrom tests on Kevin\nTEST\u003dReading and writing to flash works on our zaius machines over mtd\n\nChange-Id: I3d6bb282863a5cf69909e28a1fc752b35f1b9599\nSigned-off-by: Brian Norris \u003cbriannorris@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/505409\nReviewed-by: David Hendricks \u003cdhendrix@chromium.org\u003e\nReviewed-by: Martin Roth \u003cmartinroth@chromium.org\u003e\nReviewed-by: William Kennington \u003cwak@google.com\u003e\nReviewed-on: https://review.coreboot.org/25706\nTested-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Philipp Deppenwiese \u003czaolin.daisuki@gmail.com\u003e\n" }, { "commit": "e083880279119677e443fc16b4694f8c81bf2c40", "tree": "03413b996779bc4c86ec41590f3e7bcdd97d0ef5", "parents": [ "124ef38f7afc61ad7c713c22aad7c5c7f79bdb9b" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Mon Apr 02 11:14:02 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 24 20:21:41 2018 +0000" }, "message": "Remove address from GPLv2 headers\n\nChange-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/25381\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "2b5adfb1b656dd6a6efbf45a7a411c87840c5394", "tree": "cfc4bf09d45d4ad59b645c0cadaec9507ba5c152", "parents": [ "25fde40f8594b1c13ba7a4c3a605b96b200a4e11" ], "author": { "name": "Shawn Anastasio", "email": "shawnanastasio@yahoo.com", "time": "Sun Dec 31 00:17:15 2017 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 26 15:23:10 2018 +0000" }, "message": "buspirate_spi: Add support for variable serial speeds\n\nThis patch sets the default baud rate for communication between\nthe host device and the Bus Pirate for hardware versions 3.0\nand greater to 2M baud.\n\nIt also introduces the ability to manually set the baud rate via\nthe added \u0027serialspeed\u0027 programmer parameter.\n\nThis is done in two parts. Firstly, the requested serial speed is looked up\nin a table to determine the appropriate clock divisor and the divisor is sent\nto the bus pirate. Then, the system\u0027s baud rate for the selected serial port\nis set using serial.c\u0027s \u0027serialport_config\u0027. This function\u0027s prototype had to\nbe added to programmer.h.\n\nIn testing, using the 2M baud rate was able to significantly decrease\nflash times (down from 20+ minutes to less than 2 minutes for an 8MB flash).\n\nChange-Id: I3706f17a94fdf056063f2ad4a5f0a219665cdcbf\nSigned-off-by: Shawn Anastasio \u003cshawnanastasio@yahoo.com\u003e\nReviewed-on: https://review.coreboot.org/23057\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "1cf407b4f8d56035816efaf936a40553441eca46", "tree": "c8e41e1172aaeb567af161a9763521c53073bdc4", "parents": [ "ed098d62d66d91cf7330a37f9b83e303eb7f56d8" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 10 20:18:23 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jan 02 20:14:34 2018 +0000" }, "message": "spi_master: Introduce SPI_MASTER_4BA feature flag\n\nAdd a feature flag SPI_MASTER_4BA to `struct spi_master` that advertises\nprogrammer-side support for 4-byte addresses in generic commands (and\nread/write commands if the master uses the default implementations). Set\nit for all masters that handle commands address-agnostic.\n\nDon\u0027t prefer native 4BA instructions if the master doesn\u0027t support them.\n\nChange-Id: Ife66e3fc49b9716f9c99cad957095b528135ec2c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22421\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "ed098d62d66d91cf7330a37f9b83e303eb7f56d8", "tree": "639b6233e588fd8b4150b42112da36e239ba7fa4", "parents": [ "7e3c81ae7122120fe10d43fcba61a513e2461de9" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Apr 21 23:47:08 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:49:05 2017 +0000" }, "message": "spi: Move ICH BBAR quirk out of the way\n\nGet rid of the layering violations around ICH\u0027s BBAR. Move all the weird\naddress handling into (surprise, surprise) `ichspi.c`. Might fix writes\nfor the `BBAR !\u003d 0` case by accident.\n\nBackground: Some ICHs have a BBAR (BIOS Base Address Configuration\nRegister) that, if set, limits the valid address range to [BBAR, 2^24).\nCurrent code lifted addresses for REMS, RES and READ operations by BBAR,\nnow we do it for all addresses in ichspi. Special care has to be taken\nif the BBAR is not aligned by the flash chip\u0027s size. In this case, the\nlower part of the chip (from BBAR aligned down, up to BBAR) is inacces-\nsible (this seems to be the original intend behind BBAR) and has to be\nleft out in the address offset calculation.\n\nChange-Id: Icbac513c5339e8aff624870252133284ef85ab73\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22396\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a5216367d5640f07d58a6549fa6df86d91daff1a", "tree": "72cb2a7ba167ed6d6e0509ad8292ea7283932e7a", "parents": [ "aa91d5c16858cb400cc61e8a759838f645e3f314" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Tue Aug 08 20:02:22 2017 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Fri Sep 01 20:34:44 2017 +0000" }, "message": "chipset_enable: Add support for C620-series Lewisburg PCH\n\nThis adds PCI IDs for C620-series PCHs and adds\nCHIPSET_C620_SERIES_LEWISBURG as a new entry in the ich_chipset enum.\n\nLewisburg is very similar to Sunrise Point for Flashrom\u0027s purposes,\nhowever one important difference is the way the \"number of masters\" is\ninterpreted from the flash descriptor (0-based vs. 1-based). There are\nalso new flash regions defined.\n\nChange-Id: I96c89bc28bdfcd953229c17679f2c28f8b874d0b\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/20922\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a54ceb1dbe76e76ca8701dbda3e5baf011b16d6d", "tree": "f27ce3b104511a8b1598e77858cb42b41cb5e515", "parents": [ "67d71792929f94d4638a3663f2fc19aea4918681" ], "author": { "name": "Youness Alaoui", "email": "kakaroto@kakaroto.homelinux.net", "time": "Wed Jul 26 18:03:36 2017 -0400" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 10 15:18:11 2017 +0000" }, "message": "rpci: Use pci_dev struct pointer to avoid API breaks\n\nThe pci_dev structure is never meant to be used as is, but always as a\npointer. By using the struct itself in undo_pci_write_data, we are risking\ndata corruption, or buffer overflows if the structure size changes.\n\nThis is especially apparent on my system where flashrom segfaults\nbecause I compile it with pciutils 3.3.0 and I run it on a system\nwith pciutils 3.5.2. The struture size is different and causes a\nstruct with the wrong size to be sent to the library, with invalid\ninternal field values.\n\nThis has been discovered and discussed in Change ID 18925 [1]\n\n[1] https://review.coreboot.org/#/c/18925/\n\nChange-Id: Icde2e587992ba964d4ff92c33aa659850ba06298\nSigned-off-by: Youness Alaoui \u003ckakaroto@kakaroto.homelinux.net\u003e\nReviewed-on: https://review.coreboot.org/20784\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "93c306939b732fb05f6d8a692acc3fca78bc0f9f", "tree": "197478ba299562a8044c7d998c24e365af61b295", "parents": [ "d152fb95e2b7fda62a85f6c8e4112ba9f353a8d6" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Mar 20 14:25:09 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 28 12:13:59 2017 +0000" }, "message": "chipset_enable: Add support for Intel Skylake / Kabylake\n\nAll publicly known Skylake / Kabylake / Sunrise Point PCH variants\nshare the same register interface [1..6]. Although all SPI configu-\nration is now done through the SPI PCI device 1f.5, we can\u0027t probe\nfor it directly since its PCI vendor and device IDs are usually hid-\nden.\n\nTo work around the hidden IDs, we use another PCI accessor that doesn\u0027t\nrely on the OS seeing the PCI device.\n\nThis handles SPI flashes only. While booting from LPC is still sup-\nported, it seems nobody uses it any more.\n\nSome additional PCI IDs were gathered from driveridentifier.com.\n\nTEST\u003dCompiled with B150 set to NT (instead of BAD) and checked for\n sane register readings.\n\n[1] 6th Generation Intel® Core(TM) Processor Families I/O Platform\n Datasheet - Volume 1 of 2\n Revision 002EN\n Document Number 332995\n\n[2] 6th Generation Intel® Processor I/O Datasheet for U/Y Platforms\n Volume 2 of 2\n Revision 001EN\n Document Number 332996\n\n[3] 7th Generation Intel® Processor Families I/O Platform\n Datasheet - Volume 1 of 2\n Revision 002\n Document Number 334658\n\n[4] 7th Generation Intel® Processor Families I/O for U/Y Platforms\n Datasheet - Volume 2 of 2\n Revision 002\n Document Number 334659\n\n[5] Intel® 100 Series and Intel® C230 Series Chipset Family Platform\n Controller Hub (PCH)\n Datasheet - Volume 1 of 2\n Revision 004EN\n Document Number 332690\n\n[6] Intel® 100 Series Chipset Family Platform Controller Hub (PCH)\n Datasheet - Volume 2 of 2\n Revision 001EN\n Document Number 332691\n\nChange-Id: I000819aff25fbe9764f33df85f040093b82cd948\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18925\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Youness Alaoui \u003csnifikino@gmail.com\u003e\n" }, { "commit": "560111e2ce506b75b112f0d10b5f9b99f007bfa5", "tree": "d9a568d1b4c092a80c9252a648f7ea7ce79bff01", "parents": [ "512059118e9ff56d2b4f3c324db5e764e288ac68" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Apr 26 12:27:17 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 20 11:48:06 2017 +0200" }, "message": "ichspi: Drop `dev` parameter from init functions\n\nIt\u0027s never used and has no clear contract (e.g. will the pointer stay\nvalid beyond the call?).\n\nChange-Id: I0d4e7cc731364e86eff214b9022b842a577f9ef4\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/19460\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilippe.mathieu.daude@gmail.com\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n" } ], "next": "512059118e9ff56d2b4f3c324db5e764e288ac68" }