)]}'
{
  "log": [
    {
      "commit": "9c6b35f03ca30c60ee6d9d90b0a0309945e2714b",
      "tree": "7defede1317b0d76d0f9ff9c1a753fd5afd4ac44",
      "parents": [
        "83d04387cfd38b2e286a7686c9373435665cea51"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Feb 08 18:19:00 2026 +0100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Tue Feb 10 15:56:47 2026 +0000"
      },
      "message": "ich_descriptors: Pretty print voltage on supported platforms\n\nSeems more and more important to have such clues about 1.8V parts.\n\nChange-Id: Ida9a447d840d63a9fed7c48b3a18546e67284a44\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/396\n"
    },
    {
      "commit": "b3cc2c6d3b39cc3c97d4130257b805a152a79b4c",
      "tree": "a8175496af3d776dcd5b528a045bc8853d5f3455",
      "parents": [
        "8e4151ddb5b4533aa004594e5009ad92159b0651"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Mon Jul 15 00:45:17 2024 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Nov 10 13:58:05 2024 +0000"
      },
      "message": "ich_descriptors: Unify pretty printing of PCH100+ masters\n\nThe newer platforms mostly differ in names and numbers of masters and\nregions.  Make that obvious, and write a generic printing loop. Hope-\nfully this will make future additions easier.\n\nChange-Id: I3e616064743e9558f799159ef8b702f2bbd8ec89\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/182\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n"
    },
    {
      "commit": "c3b02dce51aad2766512d1939a1b7447c2d526b8",
      "tree": "58069f464bb8a777ef06e93767813a4c5a042cb0",
      "parents": [
        "a02df33fbf1c196395a61049e60895d4ae0e0a5b"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat Aug 12 01:13:45 2023 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Mon Sep 18 19:24:39 2023 +0000"
      },
      "message": "Rebrand to flashprog and update URLs\n\nMostly automated `sed` work. As of now, URLs to the old wiki are broken\neither way, so changing them shouldn\u0027t hurt. Other URLs (e.g. to mailing\nlist archives) were hopefully filtered correctly.\n\nChange-Id: I9d43bfd0e675eff2fcbad05f304b9ce9f5006b08\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashrom-stable/+/21\n"
    },
    {
      "commit": "58015c25eb05fa77966d1c53261a83b56a3cf6b3",
      "tree": "a1df11881a074c8c66de756f846be9030ce0443a",
      "parents": [
        "e276765eca031c6900d37b22b89e686283f39c91"
      ],
      "author": {
        "name": "Thomas Heijligen",
        "email": "thomas.heijligen@secunet.com",
        "time": "Thu Apr 14 13:50:55 2022 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Jan 29 12:29:02 2023 +0000"
      },
      "message": "Introduce an `include` directory for header files\n\nMove all header files to the new `include` directory.\nAdapt include directives and build systems to the new directory.\n\nChange-Id: Iaddd6bbfa0624b166d422f665877f096983bf4cf\nSigned-off-by: Felix Singer \u003cfelix.singer@secunet.com\u003e\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58622\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72322\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n"
    },
    {
      "commit": "5bd990c2ab8ceb263d598a2348d7020ce774784f",
      "tree": "0ee2bdd6b6aa9af15becf68d7afd4142df0bf99c",
      "parents": [
        "92e0b62fc37a6d89975ced41f5ec3c3715404f33"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Jun 16 19:46:46 2019 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Jan 29 12:29:02 2023 +0000"
      },
      "message": "layout: Introduce flashrom_layout_new()\n\nIt initializes an empty layout. Currently the maximum number of entries\nhas to be specified, which will vanish once we use dynamic allocation\nper entry.\n\nWe replace the two special cases `single_layout` and `ich_layout` with\ndynamically allocated layouts. As a result, we have to take care to\nrelease the `default_layout` in a flashctx once we are done with it.\n\nChange-Id: I2ae7246493ff592e631cce924777925c7825e398\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/33543\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72214\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "927c1f036fc6b3d9b6cb84c5cacc8e78ec7d28cc",
      "tree": "1393274311640dca4be11768ae87d71dfc9aec52",
      "parents": [
        "48c3f1844888d7175106d2bd98262353e985e3cb"
      ],
      "author": {
        "name": "Edward O\u0027Callaghan",
        "email": "quasisec@google.com",
        "time": "Tue Aug 02 11:31:16 2022 +1000"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Thu Jan 05 16:35:01 2023 +0000"
      },
      "message": "include/ich_descriptors.h: Add missing include\n\nAvoid transitively including the bool type for the ich_descriptor\nfunctionality.\n\nChange-Id: I2d9eb833ca9198c0586543d3f0074893aac5c6fb\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66348\nOriginal-Reviewed-by: Matei Dibu \u003cmatdibu@protonmail.com\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71474\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "5c9f542bf8ce514c628c59e42e35fbcb615d8937",
      "tree": "bcc2215bccd5a34f07460ff0f680aa7fba224744",
      "parents": [
        "cce1e5b8636ebef59dd509680594e17b0a207857"
      ],
      "author": {
        "name": "Michał Żygowski",
        "email": "michal.zygowski@3mdeb.com",
        "time": "Wed Jun 16 15:13:54 2021 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Thu Jan 05 16:15:22 2023 +0000"
      },
      "message": "Add Tiger Lake U Premium support\n\nTiger Lake has very low ICCRIBA (TGL\u003d0x11, CNL\u003d0x34 and CML\u003d0x34) and\ndetects as unknown chipset compatible with 300 series chipset. Add a\nnew enum CHIPSET_500_SERIES_TIGER_POINT and treat it identically to\nCHIPSET_400_SERIES_COMET_POINT. There are some exceptions though,\nICCRIBA is no longer present n descriptor content so a new union has\nbeen defined for new fields and used in descriptor guessing.\nfreq_read field is not present on Tiger Lake, moreover in CannonPoint\nand Comet Point this field is used as eSPI/EC frequency, so a new\nfunction to print read frequency has ben added. Finally Tiger lake\nboot straps include eSPI, so a new bus has been added for the new\nstraps.\n\nTested: Flash BIOS region on Intel i5-1135G7\n\nSigned-off-by: Michał Żygowski \u003cmichal.zygowski@3mdeb.com\u003e\nChange-Id: I28f3b6fe9f8ce9e976a6808683f46b6f4ec72bdd\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55578\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71437\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "3ad9aad483029c8b4c7c9f0b8dd362faf1c12ef3",
      "tree": "74ad9724b0ab7db87fe06ba4323a16707107bf61",
      "parents": [
        "66e04562f48cfb1f2266c316c81693ea73371a60"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Thu Jun 17 22:05:00 2021 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Thu Jan 05 16:15:22 2023 +0000"
      },
      "message": "ich_descriptors: Revise detection for chipsets w/ ICCRIBA\n\nDetection based on ICCRIBA and FMSBA became a little messy lately.\nHowever, there\u0027s a new static difference: Since 300 series (Cannon\nPoint), there is an MDTBA field in FLUMAP1 that has always been 0\n(reserved) before. Taking this into account, we can relax the checks\non ICCRIBA.\n\nChange-Id: I587ad1abe390843d4a9e74431b6fc4b63f8ba512\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55647\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Michał Żygowski \u003cmichal.zygowski@3mdeb.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71399\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "4db0fdfdcb59f94e41c0967375c899e2d274e113",
      "tree": "5866347a6c5e63477f8e05cc32443085319c2df3",
      "parents": [
        "771bb7952a91722d2d9f100e19b0566f06298126"
      ],
      "author": {
        "name": "Angel Pons",
        "email": "th3fanbus@gmail.com",
        "time": "Fri Jul 10 17:04:10 2020 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Thu Jan 05 16:15:22 2023 +0000"
      },
      "message": "Add Gemini Lake support\n\nThe SPI hardware is pretty much unchanged from Apollo Lake. However, the\nIFD differs significantly enough to require special handling.\n\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nChange-Id: Ib5dcdf204166f44a8531c19b5f363b851d2ccd77\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54276\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71354\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "2a5dfaf140eb8f22c923a026df855da0c5e9bf82",
      "tree": "a1d231512e360758c35367d3b9b71e69f1ccbc57",
      "parents": [
        "5ec84b3c096c9ace0bf3650206a0a9412e977c64"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.huber@secunet.com",
        "time": "Thu Jul 04 16:01:51 2019 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Thu Aug 08 21:29:37 2019 +0000"
      },
      "message": "ichspi: Add support for discrete Cannon Lake PCHs\n\nOnly minor differences in the Firmware Descriptor, compared to their\npredecessors.\n\nWe extend our check on the `ICCRIBA` field in the descriptor to dis-\ntinguish it from older generation. Alas, the `freq_read` field was\nrepurposed, so we can\u0027t use it as sanity check any more.\n\nChange-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34072\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\n"
    },
    {
      "commit": "ac01baa073b0f154ffd3ffdc7c9e75987f8b525c",
      "tree": "c81104f7a8f08db2c6f0cc5d59f8f0e3fe7ea494",
      "parents": [
        "b0247b3acbc7d8d9f8da1db48a9b81c5f2e24a38"
      ],
      "author": {
        "name": "Elyes HAOUAS",
        "email": "ehaouas@noos.fr",
        "time": "Mon May 28 16:52:21 2018 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Jun 24 13:44:51 2018 +0000"
      },
      "message": "Remove unneeded white spaces\n\nChange-Id: I90f171924790ced74a62ca344fee8607607aa480\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/26652\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n"
    },
    {
      "commit": "e083880279119677e443fc16b4694f8c81bf2c40",
      "tree": "03413b996779bc4c86ec41590f3e7bcdd97d0ef5",
      "parents": [
        "124ef38f7afc61ad7c713c22aad7c5c7f79bdb9b"
      ],
      "author": {
        "name": "Elyes HAOUAS",
        "email": "ehaouas@noos.fr",
        "time": "Mon Apr 02 11:14:02 2018 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Tue Apr 24 20:21:41 2018 +0000"
      },
      "message": "Remove address from GPLv2 headers\n\nChange-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/25381\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n"
    },
    {
      "commit": "7a8305f1bd452a74a1679e75383f888b48e67f4d",
      "tree": "233c0b969a71ffc196466e5ff4138060a2654bc1",
      "parents": [
        "0eb00d4e77d3ad0fceef62b0d2ea69aa4835aa8e"
      ],
      "author": {
        "name": "David Hendricks",
        "email": "dhendricks@fb.com",
        "time": "Fri Sep 01 20:16:58 2017 -0700"
      },
      "committer": {
        "name": "David Hendricks",
        "email": "david.hendricks@gmail.com",
        "time": "Sun Sep 03 19:33:08 2017 +0000"
      },
      "message": "ich_descriptors: Use MAX_NUM_FLREGS for entries[]\n\n5 regions made sense in 2013 when this bit of code was originally\nwritten. MAX_NUM_FLREGS is now used to keep track of the max number of\nflash regions and is \u003e5 since Sunrise Point.\n\nChange-Id: Idb559e618369fecf930724a7c1c84765247f3e38\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/21338\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n"
    },
    {
      "commit": "0eb00d4e77d3ad0fceef62b0d2ea69aa4835aa8e",
      "tree": "9860c6d1b56afd370a1fdeaa7a43511ac96aa095",
      "parents": [
        "a5216367d5640f07d58a6549fa6df86d91daff1a"
      ],
      "author": {
        "name": "David Hendricks",
        "email": "dhendricks@fb.com",
        "time": "Fri Sep 01 20:02:36 2017 -0700"
      },
      "committer": {
        "name": "David Hendricks",
        "email": "david.hendricks@gmail.com",
        "time": "Sun Sep 03 19:32:52 2017 +0000"
      },
      "message": "Move ich_layout from layout.h to ich_descriptors.h\n\nThis moves the ich_layout declaration from one header to another. This\nwill avoid a circular dependency when we update the entries[] member in\nthe follow-up patch to use MAX_NUM_FLREGS which is defined in\nich_descriptors.h.\n\nChange-Id: I08006f1f7c9ccdd17a9a6d74881ed2c8541d4de1\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/21337\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n"
    },
    {
      "commit": "4d440a7c4102faae21b16204e667ea74c1dc8e52",
      "tree": "7122caef5133c365278a24d93cb7991a49aa36ae",
      "parents": [
        "8e76230dfbcc7720c5565a70daff650496556702"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Tue Aug 15 11:26:48 2017 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Wed Aug 16 17:01:59 2017 +0000"
      },
      "message": "Include \u003csys/types.h\u003e wherever ssize_t is used\n\n`ssize_t` is a POSIX type (cf. IEEE Std 1003.1).\n\nChange-Id: I5f6f114523f541b3a8d845c6faee2c0b9f753bae\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReported-by: Urja Rannikko \u003curjaman@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/21015\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Urja Rannikko \u003curjaman@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "8e76230dfbcc7720c5565a70daff650496556702",
      "tree": "ab453e50dfada2bc28e71e7202f7f3d397e3f581",
      "parents": [
        "a54ceb1dbe76e76ca8701dbda3e5baf011b16d6d"
      ],
      "author": {
        "name": "David Hendricks",
        "email": "dhendricks@fb.com",
        "time": "Wed Aug 09 22:21:31 2017 -0700"
      },
      "committer": {
        "name": "David Hendricks",
        "email": "david.hendricks@gmail.com",
        "time": "Sun Aug 13 00:38:12 2017 +0000"
      },
      "message": "ich_descriptors: Modify limits for C620/Lewisburg PCH\n\nChange-Id: Ic8adc4b87993e65096166fa6d665432697070b4c\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/20936\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n"
    },
    {
      "commit": "67d71792929f94d4638a3663f2fc19aea4918681",
      "tree": "ea1f35914191ac66f66734777a1e1542ea20b403",
      "parents": [
        "500263434b69594dc01b3ccfe5e2c4c498d87656"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.huber@secunet.com",
        "time": "Sat Jun 17 03:10:15 2017 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Jul 28 12:31:58 2017 +0000"
      },
      "message": "ich_descriptors: Pretty print an assumed chipset\n\nChange-Id: Id28cb3abc45c6e7f4c4accfc019579c7448c45d7\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/20247\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "fa62294536a3ce5070e8d9065aaa1aa45031f910",
      "tree": "66152f87787e5c3c6ce2c9db903f8e1a70bd9311",
      "parents": [
        "1dc3d420831b0ee482aede5f46ba53a0d2de4b74"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.huber@secunet.com",
        "time": "Fri Mar 24 17:25:37 2017 +0100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Jul 28 12:30:21 2017 +0000"
      },
      "message": "ich_descriptors: Update for Intel Skylake\n\nInterpretation of component clocks changed. Also more regions and more\nmasters are supported now. The number of regions (NR) is now static per\nchipset (10 in the 100 Series case) and not coded into the descriptor\nany more.\n\nv2: o Use guess_ich_chipset() for read_ich_descriptors_from_dump().\n    o Update region extraction in `ich_descriptors_tool`.\n\nTEST\u003dRun `ich_descriptors_tool` over a 100 Series dump and checked\n     that output looks sane. Run `ich_descriptors_tool` over dumps\n     of five different older systems (1 x Sandy Bridge, 3 x Ivy Bridge,\n     1 x Haswell). Beside whitespace changes, regions not accounted\n     by `NR` are not printed any more.\n\nChange-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18973\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "1dc3d420831b0ee482aede5f46ba53a0d2de4b74",
      "tree": "2c42e68012e89e5dec203874eaa0b3e6e6e086e6",
      "parents": [
        "0bb3f7142aecdf883cc28bd9b771bdba3da5d7d9"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.huber@secunet.com",
        "time": "Sat Jun 17 00:09:31 2017 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Jul 28 12:26:01 2017 +0000"
      },
      "message": "ich_descriptors: Add function to guess chipset version\n\nAdd guess_ich_chipset() that takes fields from a descriptor dump and\nreturns the lowest possible chipset version.\n\nIntel did several incompatible changes to the descriptor through the\nyears. However, they forgot to add a version number. So we have to\napply some heuristics to detect the chipset version in case of exter-\nnal flashing.\n\nChange-Id: Ie1736663dc33801b19d3e695c072c61a6c6345a2\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/20246\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "0bb3f7142aecdf883cc28bd9b771bdba3da5d7d9",
      "tree": "1bd56eecff210a628c148c836e2dfce13ebfd5f8",
      "parents": [
        "d54e4f467753a247552bfb629f007f8931b0caa7"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.huber@secunet.com",
        "time": "Wed Mar 29 16:44:33 2017 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Jul 28 12:24:06 2017 +0000"
      },
      "message": "ich_descriptors: Draw +0xfff into ICH_FREG_LIMIT()\n\nThe condition `base \u003e limit` is still valid since `base` is always at\nleast 4096 greater than `limit` in this case.\n\nChange-Id: I11ac0a50b3f32f47879e7cfb7a26068cd0572ede\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/19046\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "d54e4f467753a247552bfb629f007f8931b0caa7",
      "tree": "0a7bb8254865783ad1fa1dc958e74e1a57936953",
      "parents": [
        "93c306939b732fb05f6d8a692acc3fca78bc0f9f"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Thu Mar 23 23:45:47 2017 +0100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Jul 28 12:22:58 2017 +0000"
      },
      "message": "ichspi: Add support for Intel Skylake\n\nThe Sunrise Point PCH, paired with Skylake, has some minor changes\nin the HW sequencing interface:\n\n  * Support for more flash regions moved PR* registers\n  * Only 4KiB erase blocks are supported by the primary erase command\n  * A second erase command for 64KiB pages was added\n  * More commands were added for status register access etc.\n  * A \"Dedicated Lock Bits\" register was added\n\nNo support for the new commands was added.\n\nThe SW sequencing interface seems to have moved register location and\nis not supported any more officially. It\u0027s also untested.\n\nChanges are loosely based on the Skylake support commit in Chromium OS\nby Ramya Vijaykumar:\n\n  commit a9a64f9e4d52c39fcd3c5f7d7b88065baed189b1\n  Author: Ramya Vijaykumar \u003cramya.vijaykumar@intel.com\u003e\n\n      flashrom: Add Skylake platform support\n\nChange-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18962\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Youness Alaoui \u003csnifikino@gmail.com\u003e\n"
    },
    {
      "commit": "305f417ea565a18c1e87dcf5d97307369b721c6c",
      "tree": "75fd4a1087415f99a64d0a5f26eaddcb54969883",
      "parents": [
        "ad18631b59d814b38bb6757df93fac17937a6bc9"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.huber@secunet.com",
        "time": "Fri Jun 14 11:55:26 2013 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Wed Jun 14 11:43:32 2017 +0200"
      },
      "message": "Add option to read ROM layout from IFD\n\nAdd an option --ifd to read the ROM layout from an Intel Firmware\nDescriptor (IFD). Works the same as the -l option, if given, -i\nspecifies the images to update.\n\nv2: o Rebased on libflashrom, use libflashrom interface.\n    o Use functions from ich_descriptors.c.\n\nv3: o Move ich_descriptors.o to LIB_OBJS, thus build it independent\n      of arch and programmers.\n    o Bail out if we aren\u0027t compiled for little endian.\n    o Update flashrom.8.tmpl.\n\nv4: o Incorporated David\u0027s comments.\n    o Removed single-character `-d` option.\n\nv5: Changed region names to match the output of `ifdtool --layout ...`\n\nChange-Id: Ifafff2bf6d5c5e62283416b3269723f81fdc0fa3\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/17953\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n"
    },
    {
      "commit": "ad18631b59d814b38bb6757df93fac17937a6bc9",
      "tree": "64a5fde5ab5bc0432fa74e3c263291e931330e3e",
      "parents": [
        "3828b39263d008fb6cc5ebdbe7fb49bc6f926566"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.huber@secunet.com",
        "time": "Mon May 02 15:15:29 2016 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Wed Jun 14 11:32:36 2017 +0200"
      },
      "message": "Make read_ich_descriptors_from_dump() available in flashrom\n\nI didn\u0027t really know what I was doing and hope removing the #ifdefs\ndoesn\u0027t have negative side effects.\n\nThe idea is to make the functions generally available for external\nflashing (e.g. you might want to flash an Intel machine using an ARM\ndevice as programmer).\n\nBeware of big endian trouble, I guess. :-P\n\nChange-Id: Ib3d38a622a581afee87b49777e775942cc901fc8\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/17952\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n"
    },
    {
      "commit": "60dead4aee579f9da86549ce33d7de29de4e043b",
      "tree": "5ede315815890d8f8ff89c6f28590403d502c824",
      "parents": [
        "80e647158800d927c776d1278d8817f0ed8f17cd"
      ],
      "author": {
        "name": "Tai-Hong Wu",
        "email": "thwu@lunartoday.com",
        "time": "Mon Jan 05 23:00:14 2015 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Mon Jan 05 23:00:14 2015 +0000"
      },
      "message": "Fix wrong density encoding on Intel Silvermont\n\nSilvermont (Bay Trail, Rangeley, Avoton) seems to still use the old\ndensity encoding with 3 bits per chip. Documentation is unavailable\n(held concealed by Intel) but thanks to the efforts of Tai-Hong\n(Type) Wu the layout is clear now. This patch is based on his one\nbut solves the issue differently thus reducing the code complexity.\n\nCorresponding to flashrom svn r1861.\n\nSigned-off-by: Tai-Hong Wu \u003cthwu@lunartoday.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "823096e5270dc7ccd8b0315377428556d1987dcf",
      "tree": "53fbf8653802401b1a35a6046aa8c54e0f8b0d1a",
      "parents": [
        "4095ed797f87c92b52e15d9f6fdc0b895c414cc9"
      ],
      "author": {
        "name": "Duncan Laurie",
        "email": "dlaurie@chromium.org",
        "time": "Wed Aug 20 15:39:38 2014 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Wed Aug 20 15:39:38 2014 +0000"
      },
      "message": "Add support for Intel Wildcat Point PCH\n\nThe Wildcat Point PCH can be paired with Broadwell or Haswell.\nThis patch was essentially backported from ChromiumOS commit 9bd2af8.\n\nCorresponding to flashrom svn r1845.\n\nSigned-off-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "2ba9f6ebe56b208a1fb0b0ce5edf81097a0158be",
      "tree": "06741544f702c84fa5fcbc5edb8a888530917481",
      "parents": [
        "9e3a6984da1bb38af37ce4bb54af8f7475b7c766"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Wed Aug 20 15:39:19 2014 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Wed Aug 20 15:39:19 2014 +0000"
      },
      "message": "Refine Flash Component descriptor handling\n\nPossible values as well as encodings have changed in newer chipsets as follows.\n - Pre-PCH (i.e. ICH) chipsets had a maximum frequency of 33 MHz for all\n   operations\n - Since Cougar Point the chipsets support dual output fast reads (encoded\n   in bit 30).\n - Flash component density encoding has changed from 3 to 4 bits with Lynx\n   Point, currently allowing for up to 64 MB chips.\n\nCorresponding to flashrom svn r1843.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "d94d25d75be771eec26578355dc5c70cfb3e9c73",
      "tree": "d2cb1083a5fa9dd1274213c17bc4ede903913d3d",
      "parents": [
        "a0fce5f459871840166348de1451fd8cd8bb9cb8"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sat Jul 28 03:17:15 2012 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sat Jul 28 03:17:15 2012 +0000"
      },
      "message": "Add a bunch of new/tested stuff and various small changes 13\n\nTested Mainboards:\nOK:\n - ASRock A780FullHD\n   http://www.flashrom.org/pipermail/flashrom/2012-July/009599.html\n - ASRock 880G Pro3\n   http://www.flashrom.org/pipermail/flashrom/2012-July/009492.html\n - ASRock N61P-S\n   http://www.flashrom.org/pipermail/flashrom/2012-May/009316.html\n - ASUS M2N68-VM\n   http://www.flashrom.org/pipermail/flashrom/2012-May/009334.html\n - ASUS M3N78 PRO\n   http://www.flashrom.org/pipermail/flashrom/2012-July/009519.html\n - ASUS M4N68T V2\n   http://www.flashrom.org/pipermail/flashrom/2012-May/009277.html\n - ASUS M5A78L-M LX\n   reported by clavile on IRC\n - ASUS P8P67 PRO (rev. 3.0)\n   http://www.flashrom.org/pipermail/flashrom/2012-April/009188.html\n - ASUS P8Z68-V\n   reported by Kano on IRC\n   http://paste.flashrom.org/view.php?id\u003d1232\n - ASUS SABERTOOTH 990FX\n   http://paste.flashrom.org/view.php?id\u003d1214\n - Dell Inspiron 1420\n   http://www.flashrom.org/pipermail/flashrom/2012-May/009196.html\n - ECS GF8200A\n   http://www.flashrom.org/pipermail/flashrom/2012-May/009256.html\n - GIGABYTE GA-H61M-D2H-USB3\n   http://www.flashrom.org/pipermail/flashrom/2012-May/009333.html\n - MSI MS-7250 (K9N SLI (rev 2.1))\n   http://www.flashrom.org/pipermail/flashrom/2012-June/009436.html\n - MSI MS-7676 (Z68MA-G45 (B3))\n   http://www.flashrom.org/pipermail/flashrom/2012-June/009424.html\n - Palit N61S\n   http://www.flashrom.org/pipermail/flashrom/2012-May/009212.html\n\nNOT OK:\n - ASRock H61M-ITX\n   http://www.flashrom.org/pipermail/flashrom/2012-May/009224.html\n - Dell Latitude E6520\n   http://www.flashrom.org/pipermail/flashrom/2012-May/009197.html\n - Dell Vostro 3700\n   http://www.flashrom.org/pipermail/flashrom/2012-May/009197.html\n - Intel DH61AG\n   http://www.flashrom.org/pipermail/flashrom/2012-June/009417.html\n - Intel DQ965GF\n   http://www.flashrom.org/pipermail/flashrom/2012-May/009295.html\n - HP/Compaq 8100 Elite CMT PC (304Bh)\n   http://paste.flashrom.org/view.php?id\u003d1182\n - HP Z400 Workstation (0AE4h)\n   http://www.flashrom.org/pipermail/flashrom/2012-June/009350.html\n - Supermicro X9DR3-F\n   http://www.flashrom.org/pipermail/flashrom/2012-June/009422.html\n   \n\nTested flash chips:\n - mark AMIC A25L032 as TEST_OK_PREW (+PREW)\n   http://www.flashrom.org/pipermail/flashrom/2012-June/009363.html\n - mark Atmel AT25DF321A as TEST_OK_PREW (+REW)\n   http://www.flashrom.org/pipermail/flashrom/2012-July/009492.html\n - mark Atmel AT26DF161 as TEST_OK_PR (+PR)\n   http://www.flashrom.org/pipermail/flashrom/2012-June/009350.html\n - mark Eon EN25QH16 as TEST_OK_PR (+PR)\n   http://www.flashrom.org/pipermail/flashrom/2012-July/009566.html\n - mark SST SST39VF010 as TEST_OK_PREW (+W)\n   http://www.flashrom.org/pipermail/flashrom/2012-June/009425.html\n - mark ST M25P64 as TEST_OK_PREW (+PREW)\n   http://www.flashrom.org/pipermail/flashrom/2012-May/009332.html\n\nTested chipset enables:\n - Intel 3420\n   http://www.flashrom.org/pipermail/flashrom/2012-May/009332.html\n\n - Add board enable for ASUS P5GD2-X\n   lspci: http://paste.flashrom.org/view.php?id\u003d1234\n   write: http://paste.flashrom.org/view.php?id\u003d1240\n\nMiscellaneous\n - Reorder some boards in print.c.\n - Remove broken abit URLs.\n - Whitespace changes.\n - Fix the maximum number of southbridge straps in the ICH descriptor structs.\n - Refine documentation regarding ICH region lock bits.\n - Demote verbosity of ICH Opcode reprogramming to -VV.\n - Exclude Pony-SPI for DOS targets (missing serial support).\n\nCorresponding to flashrom svn r1554.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "b3850964f6a87f107e7eaae16d75299f32cc6e76",
      "tree": "9af3d08c6dfd14c5ef741db24abcc1507b5f045c",
      "parents": [
        "222bf1013f39808e42479cd2f1cc2687cc59e657"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sat Dec 24 00:00:32 2011 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sat Dec 24 00:00:32 2011 +0000"
      },
      "message": "Add ich_descriptor_tool to decode all flash descriptors stored in a flash dump file\n\nThis patch adds an external utility that shares most of the existing descriptor\ndecoding source code. Additionally to what is available via FDOC/FDOD this\nallows to access:\n - the softstraps which are used to configure the chipset by flash content\n   without the need for BIOS routines. on ICH8 it is possible to read those\n   with FDOC/FDOC too, but this was removed in later chipsets.\n - the ME VSCC (Vendor Specific Component Capabilities) table. simply put,\n   this is an SPI chip database used to figure out the flash\u0027s capabilities.\n - the MAC address stored in the GbE image.\n\nIntel thinks this information should be confidential for ICH9 and up, but\nreferences some tidbits in their public documentation.\nThis patch includes the human-readable information for ICH8, Ibex Peak\n(5 series) and Cougar Point (6 series); the latter two were obtained from\nleaked \"SPI Flash Programming Guides\" found by google. Data regarding ICH9\nand 10 is unknown to us yet. It can probably found in:\n\"Intel® ICH7, ICH8, ICH9 and ICH10 — SPI Family Flash Programming Guide\"\nInformation regarding the upcoming Panther Point chipset is also not included.\n\nCorresponding to flashrom svn r1480.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Matthias Wenzel \u003cbios@mazzoo.de\u003e\n"
    },
    {
      "commit": "a8d838d9d3a0373b51408a2ecb647c320e1aaff9",
      "tree": "8524bb99c9ff890da6311769656a6480abb0a1d5",
      "parents": [
        "532c717bccc95aa93bae7af8be0695bee83c32b5"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sun Nov 06 23:51:09 2011 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sun Nov 06 23:51:09 2011 +0000"
      },
      "message": "ichspi: use a variable to distinguish ich generations instead of spi_programmer-\u003etype\n\nThe type member is enough most of the time to derive the wanted\ninformation, but\n - not always (e.g. ich_set_bbar),\n - only available after registration, which we want to delay till the\n   end of init, and\n - we really want to distinguish between chipset version-grained\n   attributes which are not reflected by the registered programmer.\n\nHence this patch introduces a new static variable which is set up\nearly by the init functions and allows us to get rid of all \"switch\n(spi_programmer-\u003etype)\" in ichspi.c. We reuse the enum introduced\nfor descriptor mode for the type of the new variable.\n\nPreviously magic numbers were passed by chipset_enable wrappers. Now\nthey use the enumeration items too. To get this working the enum\ndefinition had to be moved to programmer.h.\n\nAnother noteworthy detail: previously we have checked for a valid\nprogrammer/ich generation all over the place. I have removed those\nchecks and added one single check in the init method. Calling any\nfunction of a programmer without executing the init method first, is\nundefined behavior.\n\nCorresponding to flashrom svn r1460.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n"
    },
    {
      "commit": "d0c5dc23e25f33439dd6166a5798ffbcaabf67f8",
      "tree": "46817260e91768863e9815741486d0f1b0a804bc",
      "parents": [
        "836b26a423c5dad86646bc6bc24560d444181405"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Thu Oct 20 12:57:14 2011 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Thu Oct 20 12:57:14 2011 +0000"
      },
      "message": "ichspi: add (partially) dead support code for Intel Hardware Sequencing\n\nThis was done to ease the review. Another patch will hook up (and\nexplain) this code later.\n\nCorresponding to flashrom svn r1452.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n"
    },
    {
      "commit": "1e14639f4268c21a9200fe45a8c8235472cde1c2",
      "tree": "522d54a0740bb86c1e3307823a09c37098dfe667",
      "parents": [
        "c93f5f123239121fdeba03c02f9e448ed97c52a4"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Thu Sep 15 23:52:55 2011 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Thu Sep 15 23:52:55 2011 +0000"
      },
      "message": "ichspi: add ICH/PCH flash descriptor decoding via FDOC/FDOD\n\nBased on the work of Matthias \u0027mazzoo\u0027 Wenzel this patch adds pretty\nprinting of those ICH/PCH flash descriptor sections that are\ncached/mapped by the chipset (and which are therefore reachable via\nFDOC/FDOD registers).\n\nthis includes the following:\n- content section:\n    describes the image and some generic properties (number of\n    sections, offset of sections, PCH/ICH and MCH/PROC strap\n    offsets and lengths)\n- component section:\n    identify the different SPI flash chips and their capabilities.\n- region section\n    similarly to a partition table this describes the different regions.\n    the content of FLREG* is derived from this section.\n- master section\n    defines SPI master (host, ME, GbE) access rights of the\n    individual regions. the content of PR* is derived from this section.\n\nthis is only a part of the data included in the descriptor. other\ninformation can be retrieved from a complete binary dump of the\ndescriptor region only.\n\nthis patch also adds macros and pretty printing for \"Vendor Specific\nComponent Capabilities\" registers: there are two of them: lower and\nupper. they describe the properties of the address space divided by\nFPBA (which allows to use multiple flash chips or partitions with\ndifferent properties). the properties of all supported flash chips\n(together with their RDIDs) are stored in the same format in table\nin a descriptor section (which is used by the ME apparently). a\nlater patch will use the macros outside of ichspi.c which is the\nreason why the prettyprinting function and the register bit macros\nare not defined in ichspi.c but ich_descriptors.h (else they would\nbe moved in the follow-up patch).\n\nbecause this patch relies on (compiler) implementation-specific\nlayouting of bit-fields, it checks for correct layout before taking\nany action on runtime.\n\nCorresponding to flashrom svn r1443.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n"
    }
  ]
}