)]}' { "log": [ { "commit": "d954d5d700d7aa2ff144e7f8a5a2b6df08b07590", "tree": "6babb137bb091429368d23f745f75713295f0dde", "parents": [ "e0ceedf76d48757a05f22860e7ddd03e430c2252" ], "author": { "name": "Mario Limonciello", "email": "mario.limonciello@dell.com", "time": "Tue Sep 24 16:06:57 2019 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 16 21:47:13 2019 +0000" }, "message": "meson.build: Sanitize the version string\n\nMatch strictly the library version, and remove all starting letters.\n\nChange-Id: I25587ed2ad7fbcffdf14eb758c1f0d6ab2aea545\nSigned-off-by: Mario Limonciello \u003cmario.limonciello@dell.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35566\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Richard Hughes \u003crichard@hughsie.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "e0ceedf76d48757a05f22860e7ddd03e430c2252", "tree": "e74511724d0f856e267825b1bafabe143260164c", "parents": [ "28d081924ea6fca7a643ae273cb56cd11788adc5" ], "author": { "name": "Fabrice Fontaine", "email": "fontaine.fabrice@gmail.com", "time": "Wed Jul 17 19:04:12 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 16 19:30:57 2019 +0000" }, "message": "linux_spi: reorder includes for linux \u003c4.14\n\nThis works around a missing header in spidev.h present in older\nversions of Linux. Patch is ported from:\nhttps://git.buildroot.net/buildroot/tree/package/flashrom/0001-spi.patch\n\nSigned-off-by: \"Yann E. MORIN\" \u003cyann.morin.1998@free.fr\u003e\nSigned-off-by: Fabrice Fontaine \u003cfontaine.fabrice@gmail.com\u003e\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nChange-Id: Ieab60f59bc63aca0dc4867f31699dab4167da05b\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35830\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "28d081924ea6fca7a643ae273cb56cd11788adc5", "tree": "f8b63bb8fc1337da5d76cb262cd4ce1728e2a7d4", "parents": [ "7f15de164c2b6fcb82fb9634d5d43a2368338ac3" ], "author": { "name": "David Hendricks", "email": "dhendrix@chromium.org", "time": "Sun Sep 08 13:59:42 2019 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Mon Oct 14 05:23:01 2019 +0000" }, "message": "util/git-hooks: Check for Signed-off-by line\n\nEnforce the DCO. The logic comes from coreboot\u0027s commit-msg hook,\nand I\u0027ve added a pointer to flashrom\u0027s development guidelines.\n\nChange-Id: Iea49a06c2d4824be073eff98c8aae1cbc5b145e4\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35295\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "7f15de164c2b6fcb82fb9634d5d43a2368338ac3", "tree": "68bc0a0affb1705f828c6b956f007bb64cf5bb37", "parents": [ "d58128eb83e59e09113666c80da81c891d76e949" ], "author": { "name": "Jonathan Liu", "email": "net147@gmail.com", "time": "Sun Oct 06 16:22:04 2019 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 08 18:12:26 2019 +0000" }, "message": "Fix compilation if CONFIG_INTERNAL\u003dno\n\nChange-Id: Id9e07332003832465a0eccf1d89e73d15abb35c0\nSigned-off-by: Jonathan Liu \u003cnet147@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35808\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "d58128eb83e59e09113666c80da81c891d76e949", "tree": "8ef79ded03a5d02eac66c0dde923a24fcd8408b2", "parents": [ "9e2dc2fc818cc9c1b46924e103ce669ad154b7ab" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Oct 06 21:07:44 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 08 09:59:22 2019 +0000" }, "message": "chipset_enable.c: Mark Intel Q75 as DEP\n\nTested reading, writing and erasing the internal flash chip using an HP\nPro 6300 SFF mainboard with an Intel Q75 PCH. However, since ME-enabled\nchipsets are marked as DEP instead of OK, this one shall also be.\n\nChange-Id: I273af0eb33e74b31bc4fdc95362527bba080c5a0\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35826\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "9e2dc2fc818cc9c1b46924e103ce669ad154b7ab", "tree": "0aa6df52053c8e7cb9a04614551ce0779c589e3e", "parents": [ "5374dc3461f1e74a56a4db1a8d684b29cb3a92e5" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 23 22:00:47 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 05 23:36:34 2019 +0000" }, "message": "Makefile,meson.build: Enable/assume -Wextra\n\nEnable all -Wextra warnings but -Wunused-parameter. Nobody seems to\nmiss warnings about unused parameters and we have a lot unavoidable\noccurrences in flashrom because of common interfaces.\n\nChange-Id: Id2ece264c2d483e34019985dd3a7631c4889abe6\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30411\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\n" }, { "commit": "5374dc3461f1e74a56a4db1a8d684b29cb3a92e5", "tree": "311ed873936176c06226c160ea04a574a3cbe046", "parents": [ "92b17a52a3aaec7e87aabfc6ce5f05726d1000c0" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 04 16:16:15 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 05 23:33:22 2019 +0000" }, "message": "flashchips: Add missing block erasers for GD25Q256D\n\nChange-Id: I7e49e468c7f1eaf0ddd5fc08d6cc6569274faf94\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35798\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "92b17a52a3aaec7e87aabfc6ce5f05726d1000c0", "tree": "1f2789021c48219aa78b0a2fdea8b1d7fb288353", "parents": [ "961f4a1f29787cbb6bd9a8a43b6ac4f3f0d024c0" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 04 18:47:24 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 05 23:27:00 2019 +0000" }, "message": "board_enable: Work around -Wtype-limits issue\n\nIn case of an empty `board_matches` list (i.e. on non-x86), we checked\nif the `unsigned i` is smaller 0. Shuffling the computation avoids that\nproblem.\n\nChange-Id: I636d73c920a7b7e7507eafe444bab8236d7acb67\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35801\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nReviewed-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\n" }, { "commit": "961f4a1f29787cbb6bd9a8a43b6ac4f3f0d024c0", "tree": "13023be2c6cc0140cbfa97dee108a441e696b638", "parents": [ "b417c0c2d2616feff30cc87316a278055da8c64a" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 04 17:34:22 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 05 23:26:25 2019 +0000" }, "message": "Fix more sign-compare issues\n\nThe one in the `dummyflasher` is a little peculiar. We actually never\nknew the type of the `st_size` field in `struct stat`. It happens to\nbe `signed` in some systems (e.g. DJGPP).\n\nChange-Id: If36ba22606021400b385ea6083eacc7b360c20c5\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35800\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nReviewed-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\n" }, { "commit": "b417c0c2d2616feff30cc87316a278055da8c64a", "tree": "9143a7e9b1b9b25e1d1e172cb1ee2fd5076d14ce", "parents": [ "349b5d24345c5a550c0e38cf26452c6338cc1c12" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Sep 24 22:12:40 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 05 22:45:20 2019 +0000" }, "message": "meson: Correct license to GPL-2.0\n\nParts of flashrom are 2.0+ but some are not. As Meson\u0027s purpose is to\nlink these together, it should advertise only GPL-2.0 for the whole.\n\nChange-Id: Iab99c74f5f9d54dac56085ecc7475b14be00a310\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35584\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "349b5d24345c5a550c0e38cf26452c6338cc1c12", "tree": "3a300f5d2819d91db2a8a0ee3f81c399127065e3", "parents": [ "3d8868c2b46548be6885198987492d91933c9ff7" ], "author": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sat Oct 05 12:44:27 2019 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sat Oct 05 20:19:36 2019 +0000" }, "message": "meson: Add spi95.c to fix the build\n\nReported in issue #105 on github.\n\nChange-Id: Ibe484b4ef60533135fa1e96eb203bb55985d1f8e\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35819\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "3d8868c2b46548be6885198987492d91933c9ff7", "tree": "2277db98f8b19982802f812b2a984a2591009e37", "parents": [ "4a84ec273a487c27f91bd3df70cbdf8894af70e1" ], "author": { "name": "Konstantin Grudnev", "email": "grudnevkv@gmail.com", "time": "Tue Jul 23 00:48:54 2019 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 04 17:41:01 2019 +0000" }, "message": "Add support for M95M02-A125\n\nAutomotive 2 Mbit (256KiB) serial SPI bus EEPROM\nPREW tested successfully with use of ch341a programmer\non Linux host 5.2.0-1-MANJARO x86_64\n\nSigned-off-by: Konstantin Grudnev \u003cgrudnevkv@gmail.com\u003e\nChange-Id: Ic29cd9051c7eac4822d620c299834134f987f01b\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34496\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "4a84ec273a487c27f91bd3df70cbdf8894af70e1", "tree": "faee09346d0a195ac778befa68a87c5f669cfe22", "parents": [ "de77ad4678cb33ca0b58edf89fab8113eb304bcd" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Thu Jul 25 19:12:31 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 04 14:35:20 2019 +0000" }, "message": "tree: Enable -Wwrite-strings\n\nWhen compiling, this warning gives string literals the type const char[]\nto help catch accidental modification (which is undefined behaviour).\nThere currently aren\u0027t any instances of this in flashrom, so let\u0027s\nenable this warning to keep it that way. This requires adding const\nqualifiers to the declarations of several variables that work with\nstring literals.\n\nChange-Id: I62d9bc194938a0c9a0e4cdff7ced8ea2e14cc1bc\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34577\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "de77ad4678cb33ca0b58edf89fab8113eb304bcd", "tree": "a4615817583239b756c969e72d8e9327f345b9ac", "parents": [ "8900d6c8e1438ee2a4a77c8e4d3feab81ee261e2" ], "author": { "name": "Miklós Márton", "email": "martonmiklosqdev@gmail.com", "time": "Tue Aug 06 22:43:19 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 04 11:11:47 2019 +0000" }, "message": "Add board enable for Asus P4P800SE\n\nSee github issue #32:\nhttps://github.com/flashrom/flashrom/issues/32\n\nChange-Id: I12b25ca3f85e5f2302681bddbe1adafa49c5fcb9\nSigned-off-by: Miklós Márton \u003cmartonmiklosqdev@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34764\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "8900d6c8e1438ee2a4a77c8e4d3feab81ee261e2", "tree": "5664d15b2f3ca63f9f96ef3284cbbf5c46499179", "parents": [ "7d6b526ef5b7b11f89eee37062e91590f5fa7f43" ], "author": { "name": "Miklós Márton", "email": "martonmiklosqdev@gmail.com", "time": "Tue Jul 30 00:03:22 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 04 11:03:46 2019 +0000" }, "message": "helpers: Implement strndup() for MinGW\n\nProvide strndup implementation if compiled with MinGW because\nit is a POSIX only method\n\nSigned-off-by: Miklós Márton \u003cmartonmiklosqdev@gmail.com\u003e\nChange-Id: If418080bffff1f5961cacf2a300ea9c666682458\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34621\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "7d6b526ef5b7b11f89eee37062e91590f5fa7f43", "tree": "c10247a7a5f2f15f83e9f55d1a85c03edb8d682f", "parents": [ "0cd11d8919c66351b9508f58ca0a7f7aaad6dd59" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Mon Sep 23 22:53:14 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Fri Oct 04 10:45:15 2019 +0000" }, "message": "cli_classic: Add convenient \u0027--{flash,get}-size\u0027 cli opt\n\nWe have this in the ChromiumOS fork of flashrom which we rely\non to obtain the current flash chip in use. This ports it for\nupstream consumption.\n\nV.2: Constrain number_of_operations to one as per Nico\u0027s comment.\nV.3: Rename \u0027--get-size\u0027 to \u0027--flash-size\u0027 however keep old arg as\n \u0027undocumented\u0027 for back-compat.\nV.4: Add missing --help line.\nV.5: Add man page entry.\nV.6: Use printf() directly.\n\nChange-Id: I8f002f3b2012aec4d26b0e81456697b9a5de28d6\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35592\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "0cd11d8919c66351b9508f58ca0a7f7aaad6dd59", "tree": "4034df1770ba21ccc57c9af8249e275cf2ea7352", "parents": [ "ca598dabc3e658b3b80fd41143417d884d436e06" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Mon Sep 23 22:46:12 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Fri Oct 04 10:43:50 2019 +0000" }, "message": "cli_classic: Add convenient \u0027--flash-name\u0027 cli opt\n\nWe have this in the ChromiumOS fork of flashrom which we rely\non to obtain the current flash chip in use. This ports it for\nupstream consumption.\n\nV.2: Constrain number_of_operations to one as per Nico\u0027s comment.\nV.3: Move two goto\u0027s outside inner if-else block.\nV.4: Add missing --help line.\nV.5: Add man page entry.\nv.6: Use printf() directly.\n\nChange-Id: I23d574a2f8eaf809a5c0524490db9e3a560ede56\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35591\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "ca598dabc3e658b3b80fd41143417d884d436e06", "tree": "9404e4002f46fb82bd9db759422274a06830fb31", "parents": [ "1c0c8fd9da34d29d549803f3ddff9a68dd95dfed" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Mon Aug 12 10:44:17 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Sep 24 19:12:51 2019 +0000" }, "message": "dummyflasher: Add error check for file read\n\nPrint an error message and return if the read from emu_persistent_image\nfails.\n\nChange-Id: Icd1a72f9171e547f2081ba4bc53834a17ef7fcab\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nFound-by: Coverity CID 1403912\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34845\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "1c0c8fd9da34d29d549803f3ddff9a68dd95dfed", "tree": "4cdf8d00d844fc0286f05cda7677d298d9ead6b9", "parents": [ "4a7970bc98c5bacd2cebcc2b4a3a39be304a1cae" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Mon Aug 12 14:14:40 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Sep 24 19:09:29 2019 +0000" }, "message": "linux_spi: Use fgets() to read buffer size\n\nSince fread() returns the number of bytes read, this currently will only\ncheck for errors if it returns 0 (i.e. the file was empty). However, it\nis possible for fread() to encounter an error after reading a few bytes,\nwhich this doesn\u0027t catch. Fix this by using fgets() instead, which will\nreturn NULL if EOF or an error is encountered, and is simpler anyway.\n\nChange-Id: I4f37c70e97149b87c6344e63a57d11ddde7638c4\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nFound-by: Coverity CID 1403824\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34848\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "4a7970bc98c5bacd2cebcc2b4a3a39be304a1cae", "tree": "edf5151351669ba16c2d845974997ad398494200", "parents": [ "ba7199958c9eef803845dcd9f3930277bbf9eb76" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Mon Aug 12 14:31:46 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Sep 24 19:07:45 2019 +0000" }, "message": "print: Fix vendor string memory leak\n\nFreeing this string won\u0027t really matter in the incredible case that we\nrun out of memory, but it keeps Coverity happy.\n\nChange-Id: I962d2f2227850473b70272bc48b3fc0a0fb11342\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nFound-by: Coverity CID 1403822\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34849\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "ba7199958c9eef803845dcd9f3930277bbf9eb76", "tree": "83b9c4c92e2d3c39e4e25d33a870a02f38ca3e1d", "parents": [ "1c091d1aebb055149c89f88fd5766ca4e33b7b3e" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Mon Aug 12 12:07:03 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Sep 24 19:07:02 2019 +0000" }, "message": "linux_mtd: Fix param memory leak\n\nextract_programmer_param() stores allocated memory in param, so make\nsure it is freed at the end of the function.\n\nChange-Id: I363e66b49c1ed4034ac058b94a938c8bb197e048\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nFound-by: Coverity CID 1403823\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34847\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "1c091d1aebb055149c89f88fd5766ca4e33b7b3e", "tree": "1ca7c754bcaaf1b9e8150af14af58a8a609838bf", "parents": [ "15f539c8c978e002f2b6397a7a74e1af817d5cb3" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Mon Aug 12 11:14:14 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Sep 24 19:02:48 2019 +0000" }, "message": "internal: Fix board vendor and model memory leaks\n\nThe board vendor and model are sometimes specified as arguments during\nan internal flash, so make sure they are freed at the end of\ninitialization.\n\nChange-Id: I9f43708f3b075896be67acec114bc6f390f8c6ca\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nFound-by: Coverity CID 1230664, 1230665\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34846\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "15f539c8c978e002f2b6397a7a74e1af817d5cb3", "tree": "933422f889c4d668cace147b383c4aa3a9b024a6", "parents": [ "a1fc01d9e2f28d3d5f1506117c11f35bd42a7a6a" ], "author": { "name": "David Hendricks", "email": "dhendrix@chromium.org", "time": "Thu Aug 26 21:27:17 2010 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Sep 24 18:49:09 2019 +0000" }, "message": "ichspi: Replace default JEDEC_BE_D8 with JEDEC_SE\n\nThis aligns the upstream master branch with chromium\u0027s. On-the-fly\nopcode reprogramming is supported by both branches so the default\nopcode shouldn\u0027t matter.\n\nReview URL: http://codereview.chromium.org/3239001\n\nChange-Id: I379549e8fa966e75e3d8b7932700df62cf50df64\nSigned-off-by: Mayur Panchal \u003cpanchalm@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34689\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "a1fc01d9e2f28d3d5f1506117c11f35bd42a7a6a", "tree": "c800a57c8c1bc4dc851ac939b289dd21ad03b33b", "parents": [ "07b8a17db65ad38ffcb7344192ba37d79f03193e" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Mon Sep 23 17:12:44 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Sep 24 03:20:55 2019 +0000" }, "message": "flashchips.c: Add W25Q128.V..M printlock attribute\n\nAdd a printlock attribute for the Winbond W25Q128.V..M chip. The\nprintlock attributes matches the ChromiumOS repo\u0027s definition of this\nchip.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I775d5d40677593dcb2d05750f8bbc62871b0e551\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35549\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "07b8a17db65ad38ffcb7344192ba37d79f03193e", "tree": "5f69f7abdcb32f73a25e14d9d0c4039385f84676", "parents": [ "86fc9cf7ab221bc54ef6f10252e296fc2d7a22d2" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Mon Sep 23 16:47:05 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Sep 24 03:19:00 2019 +0000" }, "message": "flashchips.c: Mark W25Q40EW as TESTED_PREW\n\nMark Winbond W25Q40EW as TESTED_PREW.\n\nThe Winbond W25Q40EW has been marked TESTED_PREW in the ChromiumOS\nrepository. ChromiumOS has the same defintion for this chip as this\nrepo, except that ChromiumOS does not have FEATURE_OTP.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I4be5b2e1069a3f735f0dc6ec92d5f4c8946fbb02\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35535\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "86fc9cf7ab221bc54ef6f10252e296fc2d7a22d2", "tree": "8ef1d074dab28dee198fe84fab0ef7dbccf7bfd2", "parents": [ "40f0757750f246bd78981fb7c02aadf1d47b18e8" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Mon Aug 26 15:02:12 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Sep 24 03:00:33 2019 +0000" }, "message": "flashchips.c: Add GD25Q256D from downstream\n\nTake definition of GD25Q256D from ChromiumOS repository.\n\nThis chip was added in `commit 0c38355c` by dlaurie@google.com\n2019-03-17.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I79d4ed48aa9126a8a6ce455a9564451346195b8f\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35480\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "40f0757750f246bd78981fb7c02aadf1d47b18e8", "tree": "81f42762d82c932b7024a1a403090ab1781a7ebe", "parents": [ "4362e629762857fefecd54fc970cdfbf5f9d6741" ], "author": { "name": "Mario Limonciello", "email": "mario.limonciello@dell.com", "time": "Thu Aug 29 14:19:21 2019 -0500" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Tue Sep 24 01:15:48 2019 +0000" }, "message": "libflashrom.h: Add types not included in all projects\n\nAdd \u003cstdbool.h\u003e and \u003cstdint.h\u003e to allow compilation in fwupd.\n\nSigned-off-by: Mario Limonciello \u003cmario.limonciello@dell.com\u003e\nChange-Id: Ib48ddc6412f82677f43e445346dc64ccfadf2423\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35155\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\n" }, { "commit": "4362e629762857fefecd54fc970cdfbf5f9d6741", "tree": "5a4d3dacda6d39344416481eab4b0586f1a3d691", "parents": [ "03707300db4369a8c197fdda0b7730d4a43182fd" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Mon Aug 26 15:02:12 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Wed Sep 18 01:20:33 2019 +0000" }, "message": "flashchips.c: Mark EN29F002(A)(N)B as tested +EW\n\nMark EN29F002(A)(N)B as tested for erase and write. This chip was marked\ntested in the Chromium (downstream) repo change\n98d917cfba55b68516cdf64c754d2f36c8c26722 \"Add a bunch of new/tested\nstuff and various small changes 8\"\n\nTEST\u003dBuild and run flashrom -L\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Idd26187905f389fc858eea5b13915af88e40afe9\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35092\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "03707300db4369a8c197fdda0b7730d4a43182fd", "tree": "38c72cfe7cee022776e9a71876738dadb9e39262", "parents": [ "4f00912c704ea6b69df8dc331199503b1c6739c3" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Mon Aug 26 12:50:43 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Sep 17 07:40:02 2019 +0000" }, "message": "flashchips.c: Identify MX25L25645G part\n\nApply downstream patch d978051c2e7da88088ec4ef19827c04873a5479d,\n\"flashrom: Identify MX25L25645G part\" from\nchris_zhou@compal.corp-partner.google.com 2019-04-13. Change description\nwas:\n\n\"\"\"\nMX25L25635F and MX25L25645G have the same chips identify. Add\nMX25L25645G to the name of the part so that it doesn\u0027t confused people.\n\"\"\"\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I317345b4753cfc46fdca8f673a0591e33b62138b\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35091\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "4f00912c704ea6b69df8dc331199503b1c6739c3", "tree": "18b7d84641364382629a82122b858bd5d90db5b3", "parents": [ "dd59220e7e774d3e8fa100cd0b448fa363e3be73" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Mon Aug 26 10:45:18 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Sep 17 06:29:47 2019 +0000" }, "message": "flashchips: Add GD25Q127C name to the GD25Q128C entry\n\nRenamed GigaDevice GD25Q128 to GD25Q127C/GD25Q128.\n\nAccording to downstream (ChromiumOS) change\n4216ba3d0fbd1804a71002b9c17e0b04029a03f1 \"flashchips: Add GD25Q127C name\nto the GD25Q128C entry\", the 127C chip is replacement for the 128C chip.\nI have confirmed that 127C is newer and that 128C does not appear to be\ndocumented on Gigadevice\u0027s website or available from Digikey.\n\nTEST\u003dRan flashrom -L\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I3366e5904eff2443fda90552f7f5e31a8785d8b3\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35089\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "dd59220e7e774d3e8fa100cd0b448fa363e3be73", "tree": "6d7c8fb007bf977a011c3b4b63bb906f5872b677", "parents": [ "71b706f544eff68657a15139c39b9f0d8c3b2940" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Fri Aug 23 10:11:37 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Sep 17 06:29:13 2019 +0000" }, "message": "flashchips.c: Put SFDP-capable chip back into position\n\nPut entry for Unknown SFDP-capable chip back into place at end of file.\n\nChange 1f9cc7d89992114c70f7a0545ad9f98701bebe56 \"flashchips.c: Sort file\nby vendor and model\" reordered many entries in flashchips.c, including\nthis one. However, the entry for Unknown, SFDP-capable chip should not\nhave been moved before any specific chip entries.\n\nAs reported by Angel Pons \u003cth3fanbus@gmail.com\u003e at\nhttps://review.coreboot.org/c/flashrom/+/33931:\n\n\"\"\"\nOops, this introduced a bug: the SFDP entry is no longer at the end of\nflashchips.c, so probing on a SFDP-capable Winbond chip results in added\nnoise (flashrom says things about an unknown chip, and then has two\ndefinitions for the same chip).\n\"\"\"\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I5955020456dbcd5e7db280a459b668a743e464dc\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35037\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "71b706f544eff68657a15139c39b9f0d8c3b2940", "tree": "c1dde02bfa7df1aeb1c29d2dd881f826f0b6c118", "parents": [ "188127e5692df218c560253095a1e96cdff7c6cd" ], "author": { "name": "Artur Raglis", "email": "artur.raglis@3mdeb.com", "time": "Wed Jun 05 19:24:52 2019 +0200" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Tue Sep 17 00:34:37 2019 +0000" }, "message": "libflashrom: add querying functions with meson integration\n\nWork based on lukasz.dmitrowski@gmail.com code\n\nChange-Id: I49041b8fa5700dabe59fef0d2337339d34cd6c6f\nSigned-off-by: Artur Raglis \u003cartur.raglis@3mdeb.com\u003e\nSigned-off-by: Lukasz Dmitrowski \u003clukasz.dmitrowski@gmail.com\u003e\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34363\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "188127e5692df218c560253095a1e96cdff7c6cd", "tree": "f4e17efd282d0c26c07ab5c1342c9120874e45b6", "parents": [ "ea0c093246fbaba9ab89348400ba4e99032aa4e0" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Tue Aug 06 16:10:34 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Wed Aug 21 06:18:16 2019 +0000" }, "message": "flashchips: upstream changes to GD25LQ128\n\nChange name of GD25LQ128 to GD25LQ128CD. This is an upstreaming of the\nchange from the chromium flashrom repo SHA\n6c957d745f5d3dcadd1035734a5cf1b804bd0f2f (Also visible at\nhttps://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/1181175)\n\nThe rationale from that change was:\n\n The GD25LQ128C part is EOL. It\u0027s replacement is GD25LQ128D, but\n both chips identify in the same manner. Add GD25LQ128D to the name\n of the part so that it doesn\u0027t confused people.\n\nMaking this name consistent will simplify further merging from the\nchromium fork.\n\nChange-Id: I57804f1a33170668e029a7b08ac050d9a3bd6dbb\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34735\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "ea0c093246fbaba9ab89348400ba4e99032aa4e0", "tree": "f5982cd4b2d3e207d064612083a286fcd5ad5cfc", "parents": [ "bde44a1989342859240c6993d1f782945bb4ce94" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Jul 04 17:34:16 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:33:25 2019 +0000" }, "message": "chipset_enable: Mark Intel CM236 and CM246 as DEP\n\nThe usual ME-lock limitations apply, so this is DEP instead of OK.\n\nTested on Kontron/bSL6 (SKL) and Siemens/Field PG M6 (CFL) and also\nregression tested on Apollo Lake. Flashrom works fine, and logs and\ndescriptor dumps look good. Also, register and descriptor output\nagree on the flash layout and permissions.\n\nChange-Id: I40db4773f127bec63e377e1d2ab402b47edf9a61\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34073\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "bde44a1989342859240c6993d1f782945bb4ce94", "tree": "8887b05e3561727001e0dd6ad14ee1d040ff9ee3", "parents": [ "2a5dfaf140eb8f22c923a026df855da0c5e9bf82" ], "author": { "name": "Matt DeVillier", "email": "matt.devillier@puri.sm", "time": "Thu Jul 04 17:52:40 2019 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:29:46 2019 +0000" }, "message": "chipset_enable: Add support for Cannon Lake U Premium\n\nAdd support for Cannon Lake U Premium (CFL-U/WHL-U).\nSame as discrete 300-series CNP PCH.\n\nTested on a WHL-U laptop w/unlocked IFD.\n\nChange-Id: I8a318d63cf408a3b2cec436a3fa6e26cf8552ead\nSigned-off-by: Matt DeVillier \u003cmatt.devillier@puri.sm\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34076\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "2a5dfaf140eb8f22c923a026df855da0c5e9bf82", "tree": "a1d231512e360758c35367d3b9b71e69f1ccbc57", "parents": [ "5ec84b3c096c9ace0bf3650206a0a9412e977c64" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Jul 04 16:01:51 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:29:37 2019 +0000" }, "message": "ichspi: Add support for discrete Cannon Lake PCHs\n\nOnly minor differences in the Firmware Descriptor, compared to their\npredecessors.\n\nWe extend our check on the `ICCRIBA` field in the descriptor to dis-\ntinguish it from older generation. Alas, the `freq_read` field was\nrepurposed, so we can\u0027t use it as sanity check any more.\n\nChange-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34072\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\n" }, { "commit": "5ec84b3c096c9ace0bf3650206a0a9412e977c64", "tree": "473c877a4c2901830e7a8005aa45b07d50323e9d", "parents": [ "045b97ebd97426b70706db7338a7fd76790b8781" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Mar 19 17:00:03 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:29:24 2019 +0000" }, "message": "chipset_enable: Add support for discrete Cannon Lake PCHs\n\nThe Cannon Lake \"300 Series\" PCHs [1,2] share the register layout of the\nSkylake \"100 Series\". Mark them as BAD until `ichspi.c` is adapted.\n\n[1] Intel(R) 300 Series and Intel(R) C240 Series\n Chipset Family Platform Controller Hub\n Datasheet - Volume 1 of 2\n Revison 4 (Dec 2018)\n Document Number 337347\n\n[2] Intel(R) 300 Series Chipset Families Platform Controller Hub\n Datasheet - Volume 2 of 2\n Revision 2? (Oct 2018)\n Document Number 337348\n\nChange-Id: If0b54799d5b93169ee660409bad57ae14677340c\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34071\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\nReviewed-by: Jeremy Soller \u003cjackpot51@gmail.com\u003e\n" }, { "commit": "045b97ebd97426b70706db7338a7fd76790b8781", "tree": "428bed111f3cc84a29c0059d74e337fe4cf7c7c9", "parents": [ "e8e7b0e6e8b7f665c0cce4e9a68c5b7573d39130" ], "author": { "name": "Jacob Creedon", "email": "jcreedon@google.com", "time": "Mon Jul 22 12:26:56 2019 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Aug 05 21:12:47 2019 +0000" }, "message": "flashchips: Add missing MT25Q erase commands\n\nThis adds additional 32KiB subsector erase commands 0x5c and 0x52 and an\nadditional bulk erase command of 0x60.\n\nSigned-off-by: Jacob Creedon \u003cjcreedon@google.com\u003e\nChange-Id: I5307c4b96cbd62203f5bad0c94737180fda621aa\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34490\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "e8e7b0e6e8b7f665c0cce4e9a68c5b7573d39130", "tree": "28ad082eab9008a0906bd409bf01377511202b27", "parents": [ "08e9d1d895edc2a86e8c89aeda6ffe03b503eb24" ], "author": { "name": "Jacob Creedon", "email": "jcreedon@google.com", "time": "Mon Jul 22 12:21:22 2019 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Aug 05 21:12:41 2019 +0000" }, "message": "flashchips: Fix N25Q512 bulk erase\n\nThe N25Q is a stacked device, so it requires 0xC4 to perform a die\nerase.\n\nSigned-off-by: Jacob Creedon \u003cjcreedon@google.com\u003e\nChange-Id: Ib408fbe5633abd8b657e3907142b997e88b33f84\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34489\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "08e9d1d895edc2a86e8c89aeda6ffe03b503eb24", "tree": "e554fa9e21be6164a33b6486e1cc04346f39d005", "parents": [ "a4e579f94a80b949a0173b4b49cce01f20383aa7" ], "author": { "name": "Jacob Creedon", "email": "jcreedon@google.com", "time": "Mon Jul 22 12:04:40 2019 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Aug 05 21:09:32 2019 +0000" }, "message": "flashchips: Split MT25Q from N25Q\n\nThe MT25Q is the successor to the N25Q from Micron/Numonyx/ST. The MT25Q\nis almost entirely backwards compatible with the N25Q series, however,\nthe MT25Q has additional subsector erase commands available, and there\nare differences in stacked devices in the higher capacity variants. The\nN25Q devices are left with \"Micron/Numonyx/ST\" as the vendor and MT25Q\ndevices are set with \"Micron\" as the vendor.\n\nSigned-off-by: Jacob Creedon \u003cjcreedon@google.com\u003e\nChange-Id: I9d79978544b19cf9acd5f3ea6196cf6f3b3435ef\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34488\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "a4e579f94a80b949a0173b4b49cce01f20383aa7", "tree": "320e0898ff31848178faa258ae6d326a10a37c14", "parents": [ "8855257d2051b2db0f6b1a4125d39f075d360cc4" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Wed Jul 24 14:18:39 2019 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Aug 03 14:47:06 2019 +0000" }, "message": "flashchips.c: Mark AMD Am29F010A/B as TEST_OK_PRE\n\nThe AMD Am29F010 was marked TEST_OK_PRE in chromium repo change\nSHA d217d1219ccaa43a01cd75475409183bd5714410. There are no other\ndifferences in the definition of this chip.\n\nThis is the only change from the Chromium repo to be upstreamed for AMD\nchips.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I7fa10d33b42c09d035c611535a54592083c4eaa0\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34534\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\n" }, { "commit": "8855257d2051b2db0f6b1a4125d39f075d360cc4", "tree": "3968368edfdf80bc3b8be45714492d29654e2a88", "parents": [ "a508ca0acdc5cbd0ae8c2342d865d363ef24f185" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Wed Jul 24 13:56:06 2019 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Aug 03 14:46:24 2019 +0000" }, "message": "flashchips.c: Mark Intel 82802AB as TEST_OK_PREW\n\nIntel 82802AB Was marked as TEST_OK_PREW in the Chromium fork in their\nSHA312d9ff1fb1ccb5533a867d4248eb1be95ec3fbc. The definitions in the fork\nand here in upstream are otherwise substantially similar.\n\nThere are no other downstream changes for Intel chips to be upstreamed.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Iec75f0b1c35000308601fa6fdd63ab1738d0ef94\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34533\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nTested-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n" }, { "commit": "a508ca0acdc5cbd0ae8c2342d865d363ef24f185", "tree": "8fe50245d5bb3b8817427287510f199df1015e73", "parents": [ "519be66fc59558971dd653afe69ccaf1a633b492" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jul 24 19:34:43 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jul 31 08:27:57 2019 +0000" }, "message": "chipset_enable: Fix recent -Wmissing-field-initializer trouble\n\nChange-Id: Idb2ec4a767bdc8fdfab6a78b6448e76ea3388a32\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34551\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\n" }, { "commit": "519be66fc59558971dd653afe69ccaf1a633b492", "tree": "74f0912de156a86d56111f377db080246e5205e9", "parents": [ "ef78de4a21323b8c459337356289218211f2c5ce" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 23 20:03:35 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jul 31 08:26:59 2019 +0000" }, "message": "Fix -Wsign-compare trouble\n\nMostly by changing to `unsigned` types where applicable, sometimes\n`signed` types, and casting as a last resort.\n\nChange-Id: I08895543ffb7a48058bcf91ef6500ca113f2d305\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30409\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\n" }, { "commit": "ef78de4a21323b8c459337356289218211f2c5ce", "tree": "5f6b24b01b1091c97ce32e72fb8424c2d8e9b9c1", "parents": [ "5800f5841de2fd74bfc6590978bd034a6c9e6102" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Thu Jul 18 15:08:10 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 19 16:20:08 2019 +0000" }, "message": "cli_classic: Fix Memory leak\n\nFound-by: scan-build 7.0.1-8\nChange-Id: I84e642b57b95953f376569e443ef8d8eda7bf98f\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34405\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "5800f5841de2fd74bfc6590978bd034a6c9e6102", "tree": "929fbfc5ca19a359b7bf1743ac138e1cac63e34d", "parents": [ "3384fb6ddae9583c2e201fc9c8a819e9df530369" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Thu Jul 18 14:30:47 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 19 16:17:58 2019 +0000" }, "message": "spi25: Remove dead increment\n\nValue stored in \u0027pos\u0027 is never read.\n\nFound-by: scan-build 7.0.1-8\nChange-Id: I9a70593f182d7558e71e831fc2b834ac58a25b2a\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34404\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "3384fb6ddae9583c2e201fc9c8a819e9df530369", "tree": "c0b78c341908d77ff6573416eca2e98094ee0b82", "parents": [ "a136d425cebc01fa4cfb670696243fd2194dd711" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Thu Jul 18 14:00:13 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 19 16:17:44 2019 +0000" }, "message": "pickit2_spi: Fix \"dead\" assignment\n\nWe never read the first \u0027ret\u0027. Let\u0027s check the first \u0027ret\u0027\nand exit if it failed.\n\nAlso, print the version only when the command succeeded.\n\nFound-by: scan-build 7.0.1-8\nChange-Id: I4aac5e1f3bd0604b079e1fdd9b7f09f1f4fc2d7f\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34403\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "a136d425cebc01fa4cfb670696243fd2194dd711", "tree": "9792a00db0dbd81de32d32f5da3b2d1651e5437b", "parents": [ "b221cd7048f9cde1fe789e686a0e0adaf9a688b3" ], "author": { "name": "Hemanth Guruva Reddy", "email": "meethemanth@gmail.com", "time": "Thu Jul 11 11:08:27 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jul 17 10:45:16 2019 +0000" }, "message": "flashchips: Add Macronix MX25L51245G as known chip\n\nMX25L51245G is identical to handling of MX66L51235F.\n\nChange-Id: I964e630197e33d69b199fdfb8816f18e3112bbb1\nSigned-off-by: Hemanth Guruva Reddy \u003cmeethemanth@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34234\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "b221cd7048f9cde1fe789e686a0e0adaf9a688b3", "tree": "9937847a661fbf7b83ee7d341daf59367d4d3a6e", "parents": [ "d2d3993a25c3236d397209f9c2118c3b17ce4f95" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Fri Apr 05 15:08:35 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jul 10 18:59:55 2019 +0000" }, "message": "pickit2_spi: update to libusb1 and drop libusb0 dependency\n\nTESTED: read, write, verify\n\nChange-Id: Icfc5372aa1789d35ed22d68297d5e68a74d40388\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/32213\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "d2d3993a25c3236d397209f9c2118c3b17ce4f95", "tree": "8c91f0f2d588e66963c13e48dd972de555985bf4", "parents": [ "3750986348cb99b8f0d828b73972b545a2f9c878" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Jan 18 16:49:37 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jul 06 17:23:53 2019 +0000" }, "message": "ichspi: Add Apollo Lake support\n\nIt\u0027s almost identical to 100 series PCHs and later. There are some\nadditional FREGs (12..15). To not clutter the `if` conditions further,\nmake more use of `switch` statements.\n\nTested on Kontron mAL10. Mark it as DEP as usually the last sector\nis not covered by the descriptor layout and can\u0027t be read.\n\nChange-Id: I1c464b5b3d151e6d28d5db96495fe874a0a45718\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30995\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "3750986348cb99b8f0d828b73972b545a2f9c878", "tree": "62b7c2d2a5b84561596fdbbeddc6111d27dfc315", "parents": [ "908adf4589d34eaf3bd8395afa52aed8c8887cfd" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Jan 18 14:23:02 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jul 06 17:15:58 2019 +0000" }, "message": "chipset_enable: Add Apollo Lake\n\nIt works the same as 100 series PCHs and on. The SPI device is at\n0:0d.2, though. Mark as BAD until `ichspi` is revised.\n\nChange-Id: I7b1ad402ba562b7b977be111f8cf61f1be50843a\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30994\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\n" }, { "commit": "908adf4589d34eaf3bd8395afa52aed8c8887cfd", "tree": "7381774317fc86dd8426183093d99ca45b06d5c1", "parents": [ "1f9cc7d89992114c70f7a0545ad9f98701bebe56" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Wed Jul 03 15:34:06 2019 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 05 22:48:40 2019 +0000" }, "message": "flashchips.c: Make .tested lines consistent\n\nAs per comments on https://review.coreboot.org/c/flashrom/+/33833/, make\nplacement of spaces in .tested attributes with literal definitions\nconsistent.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I18118f9f1e858547170fda8412bf6769f5cdcf53\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33998\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "1f9cc7d89992114c70f7a0545ad9f98701bebe56", "tree": "be790c5a8ade8cbf74fccf2c05a878f77ea25651", "parents": [ "2d7ab6963c4450f2fae74632e0e74037641d50d2" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Mon Jul 01 11:10:45 2019 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 05 22:48:18 2019 +0000" }, "message": "flashchips.c: Sort file by vendor and model\n\nFor self-consistency, and to allow tools to assist with merging the\nchromium fork of flashrom, sort the entries of flashchips.c. The file is\nalready largely sorted, though deviations have crept in over time.\n\nThis is a non-clever mostly ASCII-order sorting. It is not intended to\nbe permanent.\n\nChange-Id: I75a99583592526f60ba5264e92391bf8b1213b20\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33931\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "2d7ab6963c4450f2fae74632e0e74037641d50d2", "tree": "6f8fb00ab0aa528ac495152610d98826cce7f99a", "parents": [ "69146f70a65e8f376833390ced3951d8a8746996" ], "author": { "name": "Patrick Rudolph", "email": "patrick.rudolph@9elements.com", "time": "Wed Jul 03 17:58:24 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jul 04 18:48:31 2019 +0000" }, "message": "layout: Increase max rom layout size\n\nWhen trying to flash a single FMAP region on VBOOT enabled boards the\ndefault of 32 entries is to small to store all regions. Flashrom will\nbail out with \"Cannot add fmap entries to layout - Too many entries.\"\n\nIncrease the maximum rom layout size to 128 to support complex FMAPs.\n\nTested on coreboot\u0027s UP/squared mainboard using SF600.\nWith this patch it\u0027s possible to update a single FMAP region.\n\nChange-Id: I68084b08f7b35a162b5f2d3109d82a8b63c194ff\nSigned-off-by: Patrick Rudolph \u003cpatrick.rudolph@9elements.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34025\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Christian Walter \u003cchristian.walter@9elements.com\u003e\n" }, { "commit": "69146f70a65e8f376833390ced3951d8a8746996", "tree": "645527630eca55e910925cf5239294931a34ef9b", "parents": [ "f29ea362bb9ea035b6a36f0eff88c6ab77bbb97f" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 17:14:11 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Thu Jul 04 04:32:50 2019 +0000" }, "message": "flashchips.c: Format SFDP-capable chip entry\n\nTo allow automated tools to manipulate flashchips.c, make the definition\nof SFDP-capable chip more consistent with other definitions. This\ninvolves\n- reordering fields to match both other entries and the definition of\n struct flashchip.\n- reformatting comments to make them consistent with other entries.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I8708a11993822085b3e8d8c80532dfb935d39876\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33834\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "f29ea362bb9ea035b6a36f0eff88c6ab77bbb97f", "tree": "ed7eeb1e769ca400001f31c54985655f20f69f04", "parents": [ "c1863cad848a03a07e6d1a9b24dafaac39d62a94" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 17:14:02 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Thu Jul 04 04:32:22 2019 +0000" }, "message": "flashchips.c: Make comment placement consistent\n\nFor consistency, move a comment about an entry from inside the open\nbrace to outside it.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Ie9a745b7e7dc752cfd6fc14ebeb04754179893c6\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33837\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "c1863cad848a03a07e6d1a9b24dafaac39d62a94", "tree": "60e3d752d3d826d7f45f9872f3a1aed1233fe73c", "parents": [ "f5ad688f8be10c23dacc853ec0120bef5c6c3e1f" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 15:08:03 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Thu Jul 04 04:31:57 2019 +0000" }, "message": "flashchips.c: Fix field order\n\nFor consistency and in order to allow automated tools to work with\nflashchips.c, put fields in the same order as they are defined in struct\nflashchip, in flash.h\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I5e0d81cb71b2c50ffeb9bb70267f16e9ac7a263c\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33833\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "f5ad688f8be10c23dacc853ec0120bef5c6c3e1f", "tree": "474ca95ab1203026b761fbcfd325ab99390bcf32", "parents": [ "86bf6ab8876898d93ec19472190d8a2d0d56056e" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 12:09:13 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Thu Jul 04 04:30:42 2019 +0000" }, "message": "flashchips.c: Add comma after every .voltage attribute\n\nTo allow automated tools to manipulate flashchips.c, ensure that every\nvoltage attribute ends with a comma, even if it is the last member in\nthe definition.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Ie609d11ab846361f375f7b024d6ca55f83b01682\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33832\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\n" }, { "commit": "86bf6ab8876898d93ec19472190d8a2d0d56056e", "tree": "5001c54868278741c6675e2bf319128d88ef1b6e", "parents": [ "fdf5da43975808230f4e7c455dd0c57552622dfb" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 16:58:20 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Thu Jul 04 04:29:26 2019 +0000" }, "message": "flashchips: Drop dead code of AT26DF321\n\nThe definition for the AT26DF321 has been commented out since it was\nfirst added in 2008. The chip now appears to be obsolete, being marked\n\"obsolete\" and unstocked at Digikey. It is also only referred to in\nhistorical documents on the manufacturer\u0027s website (microchip.com).\n\nTo avoid further bitrot of this dead code, drop it.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Ib30b3a16f25de5def508d90ec9375563b1d4d384\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33836\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "fdf5da43975808230f4e7c455dd0c57552622dfb", "tree": "27b3ddb8e2b32af53ce543deea1526b96b09fbd5", "parents": [ "cbb85c007605c4c643aa99738981ee6284644667" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 16:56:52 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Wed Jul 03 13:08:52 2019 +0000" }, "message": "flashchips.c: format block_erasers members\n\nTo allow automated tools to manipulate flashchips.c, ensure all\n.block_erasers definitions have consistent formatting:\n- start with the opening brace on a new line.\n- ensure end brace indented exactly two tabs.\n\nSFDP-capable chip is the one exception to this rule as it has an empty\nblock instead.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Ib168bdbbef4cf097109805de15c97ecc1f7915b3\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33831\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "cbb85c007605c4c643aa99738981ee6284644667", "tree": "d8a51d547c2ebafb629219854350355ae8438299", "parents": [ "57938f86991548c2efa62cb0fabd30f8090847b3" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Tue Jun 25 13:42:34 2019 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jul 02 09:49:26 2019 +0000" }, "message": "flashchips.c: Make end of line comments consistent\n\nTo allow automated tools to manipulate flashchips.c, make end of line\ncomment formatting more consistent. Specifically, this change moves the\ncomma from end of line to immediately after the field value, before the\ncommment.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Ic4f97454766eff640b26a6c6eca29dc56c34c444\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33830\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "57938f86991548c2efa62cb0fabd30f8090847b3", "tree": "c93fc8e290c4d3a80ce0b2dd1bbda2bd770422a0", "parents": [ "fa3fcd3ab353deb959130ee82f72f845f0fd8209" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 15:06:43 2019 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jul 02 09:46:38 2019 +0000" }, "message": "flashchips.c: ATMEL-\u003eAtmel for consistency\n\nReplace the single instance where a vendor name was spelled\ninconsistently.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I6478bc29f640f789f3b35e7b4816133f4a0d292e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33829\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "fa3fcd3ab353deb959130ee82f72f845f0fd8209", "tree": "1b0839e1cb7b8e257ded1dd9d132b043c76f486a", "parents": [ "f75d8c558778a47e90f814860b3c664115aefc36" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 15:41:50 2019 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jul 02 09:45:53 2019 +0000" }, "message": "flashchips.c: Make whitespace consistent\n\nFor consistency, and to make the file amenable to manipulation by tools,\nuse only tabs when indenting. Some previous changes had introduced\nspaces for indenting.\n\nAlso ensure that every table entry is separated by a single blank line.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Ib2193798cc52641d6c443f8851903c749b31cb74\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33828\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "f75d8c558778a47e90f814860b3c664115aefc36", "tree": "7ceb5b5f2a4c4ae037e48290f747c61240e711de", "parents": [ "0a0b45bba6c1f467958c92620110a731d4917c89" ], "author": { "name": "David Tomaschik", "email": "davidtomaschik@google.com", "time": "Thu Jun 20 09:49:01 2019 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 28 06:44:59 2019 +0000" }, "message": "Add support for MX25U25635F\n\nThis is a 256Kb part with support for JEDEC 4 byte addressing modes.\nTested successfully for probe/read.\n\nChange-Id: I5bdcd32acd1942edf65e50bce0f81c836095ee8c\nSigned-off-by: David Tomaschik \u003cdavidtomaschik@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33639\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "0a0b45bba6c1f467958c92620110a731d4917c89", "tree": "d5d6b03b2dfb1e1db99770fddf4e4a9f50a5969b", "parents": [ "deeac7e41a311a0806af0e65a2ce5c6673f9cf92" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Wed Jun 26 10:35:11 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 28 06:42:41 2019 +0000" }, "message": "cli_classic: Remove old usage warnings\n\nWe are at version 1.1 now, and the user interface change in 0.9.6 was\nto make setting the programmer mandatory. This was done all the way\nback in 2012, so it is safe to remove these warnings now.\n\nChange-Id: If1b379b7b8234d50a2f0a4f522f15820a1a6603c\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33815\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "deeac7e41a311a0806af0e65a2ce5c6673f9cf92", "tree": "2ff1082bf9ed049c2863deff9a6d66b6980b1812", "parents": [ "959aafa53eeae4f22766b9d098e5ca952af8c070" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Apr 22 00:09:42 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 27 10:25:15 2019 +0000" }, "message": "spi: Drop spi_controller type\n\nNot needed anymore. Drop it fast before it encourages anyone to\nviolate layers again!\n\nChange-Id: I8eda93b429e3ebaef79e22aba76be62987e496f4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33651\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "959aafa53eeae4f22766b9d098e5ca952af8c070", "tree": "12b2cf5512e0331370f75645a73372750f273d46", "parents": [ "afc3ad64300bbcc14266e645beec897ef06df13d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Apr 22 00:13:15 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 27 10:24:47 2019 +0000" }, "message": "spi25: Fix layering violation in probe_spi_rdid4()\n\nMove the message to a lower level where we can do a more generic check\nand don\u0027t need internal knowledge of the SPI-master driver.\n\nChange-Id: Idd21d20465cb214f3ff5bf3267b9014f8beee3f3\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33650\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\n" }, { "commit": "afc3ad64300bbcc14266e645beec897ef06df13d", "tree": "d356edb82af5f5d530c36626b575467c80136211", "parents": [ "cd8aeba7f1cee4c2bd1f8598009fc3e6e7afd8bb" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Mon Jun 24 16:05:28 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jun 26 07:25:01 2019 +0000" }, "message": "tree: Make internal variables static\n\nAll these variables are only used in the files they are defined in, so\nthey can be made static.\n\nChange-Id: I1e55138adef540e9d3a2237aa5b289cb338c0608\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33747\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "cd8aeba7f1cee4c2bd1f8598009fc3e6e7afd8bb", "tree": "4ad6bbf2cc48fa388bdbfd12f6dfe76819b9cdbc", "parents": [ "cf3976e658e06464e84d04c5230c466e0ec44df7" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Fri Jun 21 15:43:19 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 23 21:40:20 2019 +0000" }, "message": "Makefile: Enable -Wmissing-prototypes\n\nChange-Id: Ia2ea3dee11e505c04a9e7956417615e39d511886\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33670\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "cf3976e658e06464e84d04c5230c466e0ec44df7", "tree": "a5d76371a4e67765060f63693568c9a3f26da8c1", "parents": [ "6c68363d0c1db0fd5e2ac95fb4adeaf254f669a7" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Fri Jun 21 15:40:33 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 23 21:40:09 2019 +0000" }, "message": "tree: Remove unused functions with no prototypes\n\nThese functions are no longer used, or were never used in the first place.\n\ngenerate_testpattern() - Introduced in commit eaac68bf8b, never used\nlist_programmers() - Introduced in commit 552420b0d6, never used\npci_dev_find_filter() - Prototype removed in commit 5c316f9549\nerase_chip_jedec() - Usage and prototype removed in commit f52f784bb3\nprintlock_regspace2_blocks() - Introduced in commit ef3ac8ac17, never used\nspi_write_status_enable() - Usage dropped in commit fcbdbbc0d4\n\nChange-Id: I742164670521fea65ffa3808446594848ce63cec\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33669\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "6c68363d0c1db0fd5e2ac95fb4adeaf254f669a7", "tree": "d04d0449d10e7d37744447aebae8530af02edd9a", "parents": [ "beeb8bc925bef6973e1c9fa6c4fd26a4113a1777" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Fri Jun 21 15:33:09 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 23 21:39:48 2019 +0000" }, "message": "tree: Include missing headers for function prototypes\n\nThese files all contain functions whose prototypes are in header files,\nso make sure those header files are included.\n\nChange-Id: I0189a1550bf90d4a0b87dcef9f8a8449590cc9d7\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33668\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "beeb8bc925bef6973e1c9fa6c4fd26a4113a1777", "tree": "30c63cf4ae4bb14a19849b1680622ad6eed86d63", "parents": [ "cb44eb7dad17522f47792dca4fc499310ff7d6f3" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Fri Jun 21 15:24:17 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 23 21:39:31 2019 +0000" }, "message": "tree: Make internal functions static\n\nNone of these functions are used outside of the files they are defined\nin, so make them all static.\n\nChange-Id: Ie9cbe12d289bcedacf2f1bf483ae64ef8039ccc1\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33667\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "cb44eb7dad17522f47792dca4fc499310ff7d6f3", "tree": "026822102436ac0dcda8d8d007f16757ad73488b", "parents": [ "712ba3a0659a70c2e93a55d9e194b2fae6db28d1" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Apr 22 00:09:42 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 23 13:06:51 2019 +0000" }, "message": "bitbang_spi: Drop bitbang_spi_master_type\n\nIt only existed to make maintenance harder and waste our time.\n\nChange-Id: I7a3b5d9ff1e99d2d4f873c6f19fb318f93762037\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33638\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "712ba3a0659a70c2e93a55d9e194b2fae6db28d1", "tree": "fe655d8877332059bcda1ea220466d2e45589d42", "parents": [ "e276411e82588e93a8578b5eadd672ecd35058ee" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Sun Jun 09 17:11:49 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 21 15:08:58 2019 +0000" }, "message": "ft2232_spi.c: Remove unneeded \u0027else\u0027\n\n\u0027else\u0027 is not needed after a \u0027break\u0027 or \u0027return\u0027.\n\nChange-Id: Ia4762d0c0601d56528de56658b869b62fbe5b263\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33346\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "e276411e82588e93a8578b5eadd672ecd35058ee", "tree": "e097d63f30075b36a289683ff922ba7a89f2c6da", "parents": [ "a67ac58dd7d62de17b7d1d8a13b327dd825502f6" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Sun Jun 09 17:09:25 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 21 15:08:30 2019 +0000" }, "message": "fmap.c: Remove unneeded \u0027else\u0027\n\n\u0027else\u0027 is not needed after a \u0027break\u0027 or \u0027return\u0027.\n\nChange-Id: I5df4d8075be012b9edf7be520d611042d9945094\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33345\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "a67ac58dd7d62de17b7d1d8a13b327dd825502f6", "tree": "d4947a65cccf6a2c166bfc173db0cd36925d9875", "parents": [ "ec819d6ccc2575f2b600b2570bb20ffde91e1bbf" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Sun Jun 09 17:06:50 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 21 15:07:47 2019 +0000" }, "message": "dmi.c: Remove unneeded \u0027else\u0027\n\n\u0027else\u0027 is not needed after a \u0027break\u0027 or \u0027return\u0027.\n\nChange-Id: I71ab1fec98c2b61d73aeb646ddfc810662d4136d\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33344\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "ec819d6ccc2575f2b600b2570bb20ffde91e1bbf", "tree": "1a912f89cf703649bfa67967ac47637e540e6243", "parents": [ "29e46d0aa6ec9ce0b5234bf3bdbd9f22c951252c" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Sun Jun 09 17:50:51 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 21 15:07:09 2019 +0000" }, "message": "serprog.c: Remove unneeded \u0027else\u0027\n\n\u0027else\u0027 is not needed after a \u0027break\u0027 or \u0027return\u0027.\n\nChange-Id: I9015020889c25ecbd391a18f56f99affc8ea307d\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33348\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "29e46d0aa6ec9ce0b5234bf3bdbd9f22c951252c", "tree": "5c2e329fbd6ca08b5dfe66c65eb8fa00049ff7ab", "parents": [ "504215b9f68e26938eea75afcbc22bdf389af991" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Sun Jun 09 17:38:25 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 21 15:06:47 2019 +0000" }, "message": "ichspi.c: Remove unneeded \u0027else\u0027\n\n\u0027else\u0027 is not needed after a \u0027break\u0027 or \u0027return\u0027.\n\nChange-Id: Ie000732158f27632ee92404c66a9aab43f3b374c\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33347\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "504215b9f68e26938eea75afcbc22bdf389af991", "tree": "85f3be7cd8fb2512a2eca63eb2ac3f3cf2456ce9", "parents": [ "477e1693c830d3246c4fd7caae8a2f2b8e9f49c1" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Apr 22 00:13:15 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 21 12:00:34 2019 +0000" }, "message": "spi25: Fix layering violation in default_spi_write_aai()\n\nChange-Id: I8aa3e2992f64906edc669060936f9522d32637fb\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33649\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "477e1693c830d3246c4fd7caae8a2f2b8e9f49c1", "tree": "1c0680caa6ef647771fec6994e474af6de76e552", "parents": [ "d8b2e808cd46986f945ba9cf3b90c70fe58de9c6" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 18 23:56:01 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 21 11:54:37 2019 +0000" }, "message": "dediprog: Bail out on unsupported, long transfers\n\nChange-Id: I7b16701597909c015f98199e73ebb7d923f2b072\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33614\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Ryan O\u0027Leary\nReviewed-by: ron minnich \u003crminnich@gmail.com\u003e\n" }, { "commit": "d8b2e808cd46986f945ba9cf3b90c70fe58de9c6", "tree": "4094be4996c4ae32a78e0e13c558ee78bcdd85dc", "parents": [ "0373ce31fe5b11dcf23b27fbc221ba019a1cf7f1" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 18 23:39:56 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 21 11:54:19 2019 +0000" }, "message": "spi: Move 16MiB partitioning up into spi_chip_read()\n\nWe enforced a 16MiB limit in spi_read_chunked() for multi-die flash\nchips that can\u0027t be fully read at once. The same limit can be useful\nfor dediprog programmers. So move it into a more generic place.\n\nChange-Id: Iab1fd5b2ea550b4b3ef3e8402e0b6ca218485a51\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33613\nReviewed-by: Ryan O\u0027Leary\nReviewed-by: ron minnich \u003crminnich@gmail.com\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "0373ce31fe5b11dcf23b27fbc221ba019a1cf7f1", "tree": "473242727e8cd1df910c3787c42857ff8ab9741e", "parents": [ "5ca5523fd8f6800c32cbc8f3724b393e791cebd6" ], "author": { "name": "Paul Menzel", "email": "pmenzel@molgen.mpg.de", "time": "Wed Oct 04 13:14:13 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 21 11:51:30 2019 +0000" }, "message": "print: Update Asus URLs to use more secure HTTPS\n\nAsus set up HTTPS for their site, and redirects to that by default. So,\nuse this by default, which also saves one redirect.\n\n```\n$ curl -I http://www.asus.com/\nHTTP/1.1 301 Moved Permanently\nContent-Length: 0\nLocation: https://www.asus.com/\nDate: Wed, 04 Oct 2017 11:15:14 GMT\nConnection: keep-alive\nX-Akamai-Device-Characteristics: desktop\nX-Akamai-Device-Model: ; ; cURL; cURL\n```\n\nUse the command below to change the occurrences.\n\n```\nsed -i \u0027s,http://www.asus.com,https://www.asus.com,g\u0027 print.c\n```\n\nChange-Id: I62319bfbf39c73f98ed3f865a11f4fe870befee4\nSigned-off-by: Paul Menzel \u003cpmenzel@molgen.mpg.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/21874\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "5ca5523fd8f6800c32cbc8f3724b393e791cebd6", "tree": "f68209e48c9c54006a5af5c09e6d0b5d4ad1c9d9", "parents": [ "70461a9524fc84ec5c095f11927cffa0429a6267" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jun 15 22:29:08 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jun 17 08:33:09 2019 +0000" }, "message": "layout: Introduce layout_next_included()\n\nChange-Id: Ib01c8af06c3f84eafbd585760e74c3c287b9fa7d\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33518\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "70461a9524fc84ec5c095f11927cffa0429a6267", "tree": "0df6b67aec1d936bf8b39a86d5d9ed97ef5aa125", "parents": [ "4f213285d78974c4b8915b311aff88449279f554" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jun 15 14:56:19 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jun 17 08:32:43 2019 +0000" }, "message": "layout: Make `romentry.name` a pointer\n\nThis should provide more flexibility while we don\u0027t have to allocate\n256B extra per layout entry.\n\nChange-Id: Ibb903113550ec13f43cbbd0a412c8f35fe1cf454\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33515\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "4f213285d78974c4b8915b311aff88449279f554", "tree": "6927f36d10acff0bee42054d881072354dff192c", "parents": [ "2b94cdb5cb2a33958b2b0165e02bec17a58a8494" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jun 15 17:33:49 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jun 17 08:31:18 2019 +0000" }, "message": "layout: Move generic layout functions into `layout.c`\n\nChange-Id: If1edde70fc51e88e6e1c560d79a0d51941b9627c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33514\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "2b94cdb5cb2a33958b2b0165e02bec17a58a8494", "tree": "fb28dffe7e4c2e8bf09b606f98869cffcf30c0bb", "parents": [ "b04fef91c100d815265bc1948e61a62f284c42ef" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jun 15 18:19:26 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jun 17 08:31:07 2019 +0000" }, "message": "layout: Never use global `layout` directly\n\nAnd rename it to `global_layout` to free `layout` as a local variable\nname. We will get rid of the global layout entirely later.\n\nChange-Id: Ia2d7d1f4f649cd239b559ba6a40ee0977004e774\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33513\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "b04fef91c100d815265bc1948e61a62f284c42ef", "tree": "9446fe01e60f38fde4dd777602a1e8dab2cce8cd", "parents": [ "ee13d0c8fa365455002b109ded7f94f990be8347" ], "author": { "name": "Arthur Heymans", "email": "arthur@aheymans.xyz", "time": "Tue Feb 05 17:35:05 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jun 17 08:03:12 2019 +0000" }, "message": "layout.c: Don\u0027t use global variables for included regions\n\nThis removes the use of global variables for included region arguments\nand also uses a linked list to store the arguments.\n\nChange-Id: I6534cc58b8dcc6256c2730c809286d8083669a6c\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/31247\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "ee13d0c8fa365455002b109ded7f94f990be8347", "tree": "c2e9fc62f57b32ce0347a16646562db67528d2fb", "parents": [ "911b8d8bc425ad1e519013e68799c494bf60ca4f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 07 17:47:40 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 14 16:02:45 2019 +0000" }, "message": "libflashrom: Add CPP guard to fix big-endian builds\n\nCalm a compiler warning on big-endian builds about the unused static\nflashrom_layout_parse_fmap(). The guard is ugly but gets the job done.\nWe should forbid endian-specific code in the future, I guess.\n\nChange-Id: Id3f4a57e027f88cc469ed50312adddcc8af71a63\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33306\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "911b8d8bc425ad1e519013e68799c494bf60ca4f", "tree": "c79baaae62dd56fcaa2b34af2ad672eb70a7e8b7", "parents": [ "a724602fe0a573071c50a54e75dbe40ff43ecc1d" ], "author": { "name": "Patrick Rudolph", "email": "patrick.rudolph@9elements.com", "time": "Thu Jun 06 11:23:55 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 14 16:00:56 2019 +0000" }, "message": "cli: Add error on missing IFD\n\nWhen no IFD is present, but the option --ifd is specified, flashrom would just\nexit without printing a helpful error message.\n\nAdd error message that IFD could not be read or parsed.\n\nTested on Intel platform without IFD present.\n\nChange-Id: Ie1edd7f36f647c52b17799878185d1e69e10d3b0\nSigned-off-by: Patrick Rudolph \u003cpatrick.rudolph@9elements.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33245\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "a724602fe0a573071c50a54e75dbe40ff43ecc1d", "tree": "2abea5c6783a7bcf8777550c594ba606d2c7de5a", "parents": [ "84c6fb5fe2b58c61dc4ed6a2026d2041a5beec5d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 07 17:39:18 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jun 08 20:47:32 2019 +0000" }, "message": "Makefile: Also blacklist J-Link SPI for DOS\n\nlibjaylink will probably never be available.\n\nChange-Id: Ie9222f82e16fe4c76fe7dd0f9aac7de6a862ab98\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33305\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "84c6fb5fe2b58c61dc4ed6a2026d2041a5beec5d", "tree": "1a91cb1f276a9a101b71740f74ff3af52e5cf238", "parents": [ "129e938e4c79caccc376d05869d2b2d08a0664ec" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 07 17:35:56 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jun 08 20:47:02 2019 +0000" }, "message": "Makefile: Blacklist Digilent SPI (using USB) for DOS\n\nChange-Id: I9a7dd5a2afcd12dd247e1f5534db61b79d77525e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33304\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "129e938e4c79caccc376d05869d2b2d08a0664ec", "tree": "9500d1d8476aaaf5ffb34f157a1e2862e55f028e", "parents": [ "32b9f5c665f4fd65d9ba742e72ae8e762f33762f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 06 15:43:27 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 07 12:32:14 2019 +0000" }, "message": "ich_descriptors: Drop line numbering comments\n\nChange-Id: Ia895e35edfc86b6955395c4570d67477da70e2c7\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33256\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "32b9f5c665f4fd65d9ba742e72ae8e762f33762f", "tree": "40050630587b90d86f83e9d32e442d5e78b301ec", "parents": [ "2e50cdc494bf4e44c01e9e331b82a3633b1d9ef2" ], "author": { "name": "Arthur Heymans", "email": "arthur@aheymans.xyz", "time": "Tue Feb 05 16:14:55 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 06 16:18:02 2019 +0000" }, "message": "layout.c: Use the libflashrom function for included arguments\n\nUse the libflashrom function to determine whether included regions are\npresent in the layout file.\n\nChange-Id: I5e9375baad763612e179262973413a7161acba8b\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/31244\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "2e50cdc494bf4e44c01e9e331b82a3633b1d9ef2", "tree": "78a7f9d9a0dd67f97d25e60c02a10e9785590fbf", "parents": [ "ba22411335f26601a76dbdf0d74a71e932b7cff8" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Sep 23 20:20:26 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 06 15:54:46 2019 +0000" }, "message": "Rework internal bus handling and laptop bail-out\n\nWe used to bail out on any unknown laptop. However, modern systems with\nSPI flashes don\u0027t suffer from the original problem. Even if a flash chip\nis shared with the EC, the latter has to expect the host to send regular\nJEDEC SPI commands any time.\n\nSo instead of bailing out, we limit the set of buses to probe. If we\nsuspect to be running on a laptop, we only allow probing of SPI and\nopaque programmers. The user can still use the existing force options\nto probe all buses.\n\nThis will obsolete some board-enables that could be moved to `print.c`\nin follow-up commits.\n\nChange-Id: I1dbda8cf0c10d7786106f14f0d18c3dcce35f0a3\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/28716\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\n" }, { "commit": "ba22411335f26601a76dbdf0d74a71e932b7cff8", "tree": "aaefbff11150db7ffd80d0ef2a1e3ea4d33e875d", "parents": [ "7eb38aa7dbd45cbc040ac513ed4375995246aa93" ], "author": { "name": "Patrick Rudolph", "email": "patrick.rudolph@9elements.com", "time": "Tue Jun 04 12:21:10 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 06 13:04:57 2019 +0000" }, "message": "dediprog: Allow 4BA on all protocol V2 devices\n\nTested on dediprog SF100 protocol V2 (firmware V:6.5.03).\nAssume it works fine on SF200 protocol V2, too.\n\nChange-Id: I8822b79f46876feff0fd443f711c57dffb67b349\nSigned-off-by: Patrick Rudolph \u003cpatrick.rudolph@9elements.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33195\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "7eb38aa7dbd45cbc040ac513ed4375995246aa93", "tree": "0b96573c7ec755ca09aa8799501e307284f337e6", "parents": [ "17890b37f362e551e886506f39e7bf7181419457" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Mar 21 15:42:54 2019 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Tue Jun 04 13:54:54 2019 +0000" }, "message": "dediprog: Implement 4BA EAR mode for protocol v1\n\nWith an SF100 and protocol version 1, using the extended address\nregister of the flash chip seems safe. Make use of that and remove\nthe broken 4BA modes flag.\n\nTested with SF100 V:5.1.9 and W25Q256FV.\n\nChange-Id: If926cf3cbbebf88231116c4d65bafc19d23646f6\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/32016\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "17890b37f362e551e886506f39e7bf7181419457", "tree": "9278586896099d40869319f64cd3124e1c4f902a", "parents": [ "f9632d82634bbbdc7e90357d3ea7c4a631ab4376" ], "author": { "name": "Evgeny Zinoviev", "email": "me@ch1p.com", "time": "Sun Jun 02 23:07:52 2019 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jun 03 20:21:58 2019 +0000" }, "message": "chipset_enable: Mark Intel QS77 as DEP\n\nTested reading and writing with `-p internal` on MacBook Air 5,2 with\nIntel QS77.\n\nChange-Id: I508b6379507c2881c976d6baf7348b1161449cfe\nSigned-off-by: Evgeny Zinoviev \u003cme@ch1p.io\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33164\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f9632d82634bbbdc7e90357d3ea7c4a631ab4376", "tree": "7534151dac52915dd1b1ebf8e462dc1a411a98e9", "parents": [ "4ca575dc5a81587da5affecd2cd97b7c8b4596b3" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 20 11:23:49 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jun 03 10:46:01 2019 +0000" }, "message": "dummyflasher: Add emulation for Winbond W25Q128FV\n\nJust needed a 16MiB chip.\n\nChange-Id: Ic01d45c1f709808404ad53bb31f8b998c6977a9d\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/31011\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\n" }, { "commit": "4ca575dc5a81587da5affecd2cd97b7c8b4596b3", "tree": "f29d091284687337fb0757dbeb64cbe9ac24bb87", "parents": [ "93db6e16895287b7ac3a8a8f7f4a4f176547b7ed" ], "author": { "name": "Patrick Rudolph", "email": "patrick.rudolph@9elements.com", "time": "Mon May 20 11:31:44 2019 +0200" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Mon May 27 19:18:28 2019 +0000" }, "message": "usbdev: Only match requested USB devices\n\nDon\u0027t use a device that has the same vendor ID, but a different\nthan requested product ID.\n\nFixes broken dediprog detection with TOMU in use.\n\nChange-Id: I08c1c363ce2d6603e46efecc61d3910e02314fca\nSigned-off-by: Patrick Rudolph \u003cpatrick.rudolph@9elements.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/32891\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Daniel Thompson \u003cdaniel.thompson@linaro.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "93db6e16895287b7ac3a8a8f7f4a4f176547b7ed", "tree": "5f7d8dcfce6b7bb62829251b381526fbdc2f5497", "parents": [ "cb97368328bc68698ab7e58a6d692635dfb1b1c7" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Sep 30 01:18:43 2018 +0200" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Mon Apr 15 18:44:22 2019 +0000" }, "message": "dediprog: Enable 4BA support for SF600, protocol V2\n\nThe only combination we could successfully test so far is the SF600 with\nprotocol version V2 (firmware 7.2.21) and native 4BA commands. Let\u0027s\nenable that at least.\n\nChange-Id: I665d0806aec469a3509620a760815861fbe22841\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/28804\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" } ], "next": "cb97368328bc68698ab7e58a6d692635dfb1b1c7" }