)]}'
{
  "log": [
    {
      "commit": "fbc41d2a932ede9c02aa7803472c31f39ec200f2",
      "tree": "8b72b78abfd99bf8737b90cc2fece11f2dbe93d3",
      "parents": [
        "966dc9b776c2897d1245937639ab41fc834d7cb9"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Feb 22 23:04:01 2026 +0100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Mar 22 09:47:02 2026 +0000"
      },
      "message": "spi: Move SPI related things into new chipdrivers/spi.h\n\nA few things that rely heavily on `flash.h` are moved there instead:\n* function signatures containing `erasefunc_t`,\n* the inline default_wrsr_target() that needs to know struct flashctx.\n\nThis allows to keep the new header file free of a transitive `flash.h`\ninclude.\n\nChange-Id: Ib215821feeb822ea3fc11bf9f48c0328f9a394d4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/416\n"
    },
    {
      "commit": "6898f5b13d4cc0b5864b0f1f898af10fb1815797",
      "tree": "5717fe27dd3924f083b6403dd7eeb31d15a683e4",
      "parents": [
        "55e788491607997ca93c86e58a38f2ac5dc73afe"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Jul 21 15:59:57 2024 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Nov 03 17:54:48 2024 +0000"
      },
      "message": "spi25_statusreg: Prefer volatile status register writes\n\nNow that libflashprog API users can choose whether to target volatile\nor non-volatile status register bits, we turn around the default beha-\nvior if both are supported. This way, we won\u0027t unnecessarily wear sta-\ntus registers in cases where we automatically disable protections.\n\nChange-Id: I92d84e4a140169464e318c7f84690b7665fdb29f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/194\n"
    },
    {
      "commit": "4ac536bde43a1d64e11034cab34aabd7a6efd5dc",
      "tree": "ceb3d304075fadbe31ed8d0d25dc8d4b8b8e60fb",
      "parents": [
        "b1d2baea270c1177a78d1672b4f8dd42ed246eb4"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Jul 21 00:22:29 2024 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Mon Jul 22 10:08:47 2024 +0000"
      },
      "message": "spi25_statusreg: Allow to write (non-)volatile bits specifically\n\nThere\u0027s a subtle difference between prepending a write-status-register\ncommand with a write enable (WREN)  or an enable write status register\n(EWSR): The former targets non-volatile bits, while the latter targets\nvolatile bits, i.e. register bits that do not survive a reset.\n\nSometimes bits are implemented as both volatile and non-volatile. Then,\nthe non-volatile state is loaded into the volatile registers after chip\nreset, and writes with a WREN target both.  So far, we simply used WREN\nwhen possible.  This can, however, lead to unnecessary wear of the non-\nvolatile bits. Flash datasheets do not mention any maximum write cycles\nfor them. However, it is unclear if this is an academic issue, i.e. the\nmanufacturers account for the wear and implement redundancy, or if they\nsimply don\u0027t expect that many configuration changes.\n\nFor a start, allow to specify explicitly which kind of register bits we\nwant to write. We keep the current behavior. However, the logic to dis-\nable block protections automatically should be revised  to prefer vola-\ntile writes.\n\nChange-Id: I807a2c48f4eaa85d5a10b37362e71818359a4c93\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/190\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n"
    },
    {
      "commit": "1b1deda80bbd7f56b8047fad32badb749eeefffb",
      "tree": "e7058d9d175d08ed2542f6e34be0842a7ade8f57",
      "parents": [
        "a1b7f3521f66a19a2d4c9a6a373c5a7ab36e1473"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Thu Apr 18 00:35:48 2024 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Mon Jul 22 10:08:47 2024 +0000"
      },
      "message": "Implement QPI support\n\nWith the quad-i/o support in place, this is actually straight-\nforward:\n* we check for compatibility of the flash chip and programmer,\n* select an appropriate fast-read function, and\n* always set the respective io-mode when passing a SPI command\n  to the programmer.\n\nTested with FT4222H + W25Q128FV and linux_gpio_spi + MX25L25645G.\n\nChange-Id: I2287034f6818f24f892d66d1a505cb719838f75d\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/165\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n"
    },
    {
      "commit": "d518563f197241cc72f5da4b2108b2df10f00372",
      "tree": "8ec807be43adf3b5c9f66a2701b7bf0ea3a4a11f",
      "parents": [
        "bd72a470b9b58386b52ca4568313be71b4d2c472"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Jan 05 18:44:41 2024 +0100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Mon Jul 22 10:08:47 2024 +0000"
      },
      "message": "spi: Prepare for multi i/o and dummy bytes\n\nMulti-i/o commands split SPI transactions into multiple phases that\ncan be transferred over 1, 2 or 4 wires. For this, we adapt `struct\nspi_command` with a new enum, specifying the transfer mode, and ad-\nditional size fields.  While we are at it, move everything related\ninto a new header file `spi_command.h` so we won\u0027t further clutter\n`flash.h`.\n\nOn the master side, we add respective feature flags for the multi-\ni/o modes.\n\nSee also the comment in `spi_command.h` about multi-i/o commands.\n\nChange-Id: I79debb845f1c8fec77e0556853ffb01735e73ab8\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/44\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n"
    },
    {
      "commit": "bd72a470b9b58386b52ca4568313be71b4d2c472",
      "tree": "078afe70db3836ef41b37ce2c64fb6de67c38747",
      "parents": [
        "3d728e7524fe086e90779ea76bf2f9bd02cdf6de"
      ],
      "author": {
        "name": "Sergii Dmytruk",
        "email": "sergii.dmytruk@3mdeb.com",
        "time": "Sun Jul 24 17:11:05 2022 +0300"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Mon Jul 22 10:08:47 2024 +0000"
      },
      "message": "spi25_statusreg: support reading/writing configuration register\n\nOne more variation of registers.\n\nThis one is read via a separate RDCR command, but written as if it\u0027s\nSR2 using WRSR_EXT2.\n\nPorted to flashprog w/o the FEATURE_CFGR flag, we\u0027ll already have that\ninformation in the register description.\n\nChange-Id: I45f9afcc31f1928ef6263a749596380082963de4\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOrignal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66211\nOrignal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOrignal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/71007\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n"
    },
    {
      "commit": "3d728e7524fe086e90779ea76bf2f9bd02cdf6de",
      "tree": "74d3bec50d87ac2fc45c1c2beaf5d780e6acda4a",
      "parents": [
        "a358b14d2e7e93e317499a687223ada2d221a36a"
      ],
      "author": {
        "name": "Sergii Dmytruk",
        "email": "sergii.dmytruk@3mdeb.com",
        "time": "Sat Nov 27 15:14:27 2021 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Mon Jul 22 10:08:47 2024 +0000"
      },
      "message": "spi25_statusreg.c: support reading security register\n\nNot to be confused with \"secure registers\" of OTP.\n\nSecurity register is a dedicated status register for security-related\nbits. You don\u0027t write its value directly, issuing special write commands\nwith no data set separate OTP bits to 1 automatically (WRSCUR, WPSEL\ncommands). No WREN is necessary, but at least some datasheets indicate\nBUSY state after those write commands.\n\nUnlike cases where OTP bit is part of SR and can only be written while\nin OTP mode, security register can only be written outside of the mode.\n\nThe register is found in at least these chips by Macronix:\n * MX25L6436E\n * MX25L6445E\n * MX25L6465E\n * MX25L6473E\n\nPorted to flashprog w/o the FEATURE_SCUR flag, we\u0027ll already have that\ninformation in the register description.\n\nChange-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59709\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/71006\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n"
    },
    {
      "commit": "3f3c1f3238dcede30d0d15d36da6326b428b8b12",
      "tree": "9adc4f207793fe401c9ffd28e2f7c60460766533",
      "parents": [
        "478e179f2d5ecf6a8b82984444b9111913a8f50f"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat May 28 16:48:26 2022 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Dec 30 01:16:50 2022 +0100"
      },
      "message": "spi25_statusreg: Allow WRSR_EXT for Status Register 3\n\nSpansion flash chips S25FL128L and S25FL256L use the WRSR instruction to\nwrite more than 2 registers. So align SR2 and SR3 support: The current\nFEATURE_WRSR_EXT is renamed to FEATURE_WRSR_EXT2 and FEATURE_WRSR_EXT3\nis added. Also, WRSR3 needs a separate flag now.\n\nVerified that FEATURE_WRSR_EXT2 still works using the `dummy_flasher`.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: Ibdfc6eb3d2cfecbf8da0493d067031ddb079a094\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64746\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70988\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n"
    },
    {
      "commit": "0b2e7dd80847f19f30db35e6e0d47f3c7b02ffbf",
      "tree": "020dea176939135afa15e8f328088e808b6c812a",
      "parents": [
        "9bf829d9a0b08323ca0ef8f2b52737f3eafbfe21"
      ],
      "author": {
        "name": "Sergii Dmytruk",
        "email": "sergii.dmytruk@3mdeb.com",
        "time": "Sun Dec 19 18:37:51 2021 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Dec 30 01:16:48 2022 +0100"
      },
      "message": "spi25_statusreg.c: add SR3 read/write support\n\nAdds support for reading and writing the third status register.\n\nFeature flag is not needed because it would never on its own control\nwhether SR3 access occurs.  If added, it would be in one of three\npossible states: wrong, useless or redundant.\n\nChange-Id: Id987c544c02da2b956e6ad2c525265cac8f15be1\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60230\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70980\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "b8a90d0a8c4b9b1a037f763e8792ae4c5363b4fb",
      "tree": "85191d34786a8297b7618919e50b64095fa2cee0",
      "parents": [
        "a1d6865d1ef53626a6a4ae61a89da2ba7d75f8f3"
      ],
      "author": {
        "name": "Nikolai Artemiev",
        "email": "nartemiev@google.com",
        "time": "Thu Oct 28 16:18:28 2021 +1100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Dec 30 01:16:47 2022 +0100"
      },
      "message": "spi25_statusreg: delete spi_read_status_register()\n\nDelete the spi_read_status_register() function because the generic\nspi_read_register() function can be used instead.\n\nThis patch also converts all call sites over to spi_read_register().\nA side effect is that error codes are now properly propagated and\nchecked.\n\nTested: flashrom -{r,w,E}\nTested: Tested with a W25Q128.W flash on a kasumi (AMD) dut.\n     Read SR1/SR2 with --wp-status and activated various WP ranges\n     that toggled bits in both SR1 and SR2.\n\nChange-Id: I146b4b5439872e66c5d33e156451a729d248c7da\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59529\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70975\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "a1d6865d1ef53626a6a4ae61a89da2ba7d75f8f3",
      "tree": "cbbb97227c2ae0e4cf45b9d222e22893118f0ec0",
      "parents": [
        "9e1afb785efd0e6144a19d1faff012d4cbf5a668"
      ],
      "author": {
        "name": "Nikolai Artemiev",
        "email": "nartemiev@google.com",
        "time": "Mon Nov 22 13:18:49 2021 +1100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Dec 30 01:16:46 2022 +0100"
      },
      "message": "spi25_statusreg: inline spi_write_register_flag()\n\nCreating the entire SPI command that should be sent to the chip in\nspi_write_register() is simpler than splitting it across two functions\nthat have to pass multiple parameters between them.\n\nAdditionally, having separate spi_write_register_flag() function\nprovided little benefit, as it was only ever called from\nspi_write_register().\n\nTested: flashrom -{r,w,E}\nTested: Tested with a W25Q128.W flash on a kasumi (AMD) dut.\n     Read SR1/SR2 with --wp-status and activated various WP ranges\n     that toggled bits in both SR1 and SR2.\n\nChange-Id: I4996b0848d0ed09032bad2ab13ab1f40bbfc0304\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59528\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70974\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "9de3f8710d5c46d35cd9869018c85e5aa51483b0",
      "tree": "b742b7c1631b89e1cfa18a5553fc3da57ed2b8df",
      "parents": [
        "0167522794a2e66f00248347122c1bb8ce3b001d"
      ],
      "author": {
        "name": "Nikolai Artemiev",
        "email": "nartemiev@google.com",
        "time": "Wed Oct 20 22:32:25 2021 +1100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Dec 30 01:16:44 2022 +0100"
      },
      "message": "spi25_statusreg,flashchips: add SR2 read/write support\n\nThis patch adds support for reading and writing the second status\nregister and enables it on a limited set of flash chips.\n\nChip support for RDSR2/WRSR2/extended WRSR is represented using feature\nflags to be consistent with how other SPI capabilities are represented.\n\nTested: flashrom -{r,w,E}\nTested: flashrom --wp-{enable,disable,range,list,status} at end of patch series\nTested: logged SR2 read/write values during wp commands\n\nChange-Id: I34a503b0958e8f2f22a2a993a6ea529eb46b41db\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58570\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70965\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "0167522794a2e66f00248347122c1bb8ce3b001d",
      "tree": "ac01ed9312b2946bdcdbe1abf1078b69f6117183",
      "parents": [
        "236a38cc46ac810d0be679402bb21e83aebcb8b9"
      ],
      "author": {
        "name": "Nikolai Artemiev",
        "email": "nartemiev@google.com",
        "time": "Wed Oct 20 22:30:41 2021 +1100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Dec 30 01:16:43 2022 +0100"
      },
      "message": "spi25_statusreg: make register read/write functions generic\n\nThis patch adds new spi_{read,write}_register() functions that take the\nsource/destination register as an argument. Currently they can only\naccess SR1, support for other registers will be added in another patch.\n\nSince we\u0027re refactoring things, this commit also makes\nspi_read_register() return an error code, making it possible to identify\nerror conditions that spi_read_status_register() concealed.\n\nThis also removes the initial 100ms delay between writing a register and\nthe first attempt to check the chip\u0027s status. An initial delay was added\nto avoid needing to read the status register multiple times, but that is\nunlikely to cause problems on modern flash chips.\n\nTested: flashrom -{r,w,E}\nTested: flashrom --wp-{enable,disable,range,list,status} at end of patch series\n\nChange-Id: I0a3951bbf993f2d8d830143b29d3ce16cc6901d7\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58475\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70964\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "721a4f390410debb77487562c8a47a20edb4d7f2",
      "tree": "cf842e10410c39de9bf712d547cdd23f40a5a19b",
      "parents": [
        "ef88423928abf61fa894d2798a9d265fd001cd26"
      ],
      "author": {
        "name": "Nikolai Artemiev",
        "email": "nartemiev@google.com",
        "time": "Mon Dec 14 07:39:02 2020 +1100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Dec 30 01:16:37 2022 +0100"
      },
      "message": "spi25_statusreg.c: restore SR contents at flashrom exit\n\nregister_chip_restore() provides a general mechanism for restoring a chip\u0027s state at flashrom exit; it can be used whenever the SR needs to be changed temporarily to perform some operation and changed back after the operation is complete. The only current current use case is in s25f.c, which changes the SR\u0027s sector layout bits so that entire flash accessible.\n\nThis patch uses the chip restore functionality to reset changes to the status register made by spi_disable_blockprotect_generic(). This should help to ensure consistency across multiple runs of flashrom and make it easier to predict how a specific operation will change the flash.\n\nImported from cros flashrom at `b170dd4e1d5c33b169c5`\n\nChange-Id: If2f0e73518d40519b7569f627c90a34c364df47c\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/48778\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70943\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "5eca427ae64519b70d1c4ccfb427305ca9974ba0",
      "tree": "1ca22ef1e0072a76650fdd182206844f8ebddd7d",
      "parents": [
        "1bbc501f79319cc6c8d839bc44fa55e96afab33a"
      ],
      "author": {
        "name": "Edward O\u0027Callaghan",
        "email": "quasisec@google.com",
        "time": "Sun Apr 12 17:27:53 2020 +1000"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Dec 30 01:16:34 2022 +0100"
      },
      "message": "const\u0027ify flashctx to align signatures with cros flashrom\n\nThe ChromiumOS flashrom fork has since const\u0027ify flashctx\nin a few places. This aligns the function signatures to\nmatch with downstream to ease forward porting patches\nout of downstream back into mainline flashrom.\n\nThis patch is minimum viable alignment and so feedback is\nwelcome.\n\nChange-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70933\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "4af3609828a980bad9ecaf99365f99305d4180f8",
      "tree": "2fca2548be1d41c2e48164e3c4f2683ac1862837",
      "parents": [
        "355a1df1837e36075f2b6e59ec1f7db1db95f02a"
      ],
      "author": {
        "name": "Yuji Sasaki",
        "email": "sasakiy@chromium.org",
        "time": "Fri Mar 22 10:59:50 2019 -0700"
      },
      "committer": {
        "name": "Felix Singer",
        "email": "felixsinger@posteo.net",
        "time": "Thu Sep 29 17:05:05 2022 +0000"
      },
      "message": "spi25: Debug flashrom crash when Write Protect is ON\n\nWhen hardware write protect is applied, flashrom crashed and\ngenerate coredump. spi_disable_blockprotect_generic() calls\nflash-\u003echip-\u003eprintlock() method when disable was failed,\nbut this method is optional, can be NULL depends on type of\nflashrom chip. NULL pointer check before call is added to\navoid crash.\n\nBRANCH\u003dnone\nBUG\u003db:129083894\nTEST\u003dRun on Mistral P2\n(On CR50 console, run \"wp disable\")\nflashrom --wp-range 0 0x400000\nflashrom --wp-enable\n(On CR50 console, run \"wp enable\")\nflashrom -r /tmp/test.bin\nVerify \"Block protection could not be disabled!\" is shown,\nbut flash read completes.\nSigned-off-by: Yuji Sasaki \u003csasakiy@chromium.org\u003e\n\nChange-Id: I81094ab5f16a85871fc9869a2e285eddbbbdec4e\nReviewed-on: https://chromium-review.googlesource.com/1535140\nCommit-Ready: ChromeOS CL Exonerator Bot \u003cchromiumos-cl-exonerator@appspot.gserviceaccount.com\u003e\nTested-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: Stefan Reinauer \u003creinauer@google.com\u003e\nReviewed-by: SANTHOSH JANARDHANA HASSAN \u003csahassan@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/40468\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67865\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n"
    },
    {
      "commit": "cf3976e658e06464e84d04c5230c466e0ec44df7",
      "tree": "a5d76371a4e67765060f63693568c9a3f26da8c1",
      "parents": [
        "6c68363d0c1db0fd5e2ac95fb4adeaf254f669a7"
      ],
      "author": {
        "name": "Jacob Garber",
        "email": "jgarber1@ualberta.ca",
        "time": "Fri Jun 21 15:40:33 2019 -0600"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Jun 23 21:40:09 2019 +0000"
      },
      "message": "tree: Remove unused functions with no prototypes\n\nThese functions are no longer used, or were never used in the first place.\n\ngenerate_testpattern() - Introduced in commit eaac68bf8b, never used\nlist_programmers() - Introduced in commit 552420b0d6, never used\npci_dev_find_filter() - Prototype removed in commit 5c316f9549\nerase_chip_jedec() - Usage and prototype removed in commit f52f784bb3\nprintlock_regspace2_blocks() - Introduced in commit ef3ac8ac17, never used\nspi_write_status_enable() - Usage dropped in commit fcbdbbc0d4\n\nChange-Id: I742164670521fea65ffa3808446594848ce63cec\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33669\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n"
    },
    {
      "commit": "db7482bb72035fab8386226d1720cde09e0c700e",
      "tree": "8a2114a45c22a44e01d8494f224b38c35b17cb71",
      "parents": [
        "e2cbb12f2209a0ba16bc87e31d544fd7fc47f0e2"
      ],
      "author": {
        "name": "Richard Hughes",
        "email": "richard@hughsie.com",
        "time": "Wed Dec 19 12:04:30 2018 +0000"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Mon Feb 11 23:50:12 2019 +0000"
      },
      "message": "Fix several -Wno-implicit-fallthrough warnings\n\nGCC is picky about the comment being where the break should go.\n\nChange-Id: I05db2fb34025fefe2c6ddd1274c8e45b7cc5a4b6\nSigned-off-by: Richard Hughes \u003crichard@hughsie.com\u003e\nReviewed-on: https://review.coreboot.org/c/30406\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n"
    },
    {
      "commit": "25584de9d0108a5dde41e0296fdf0a7854390a81",
      "tree": "d505c037e5a2e729e1eb64882c60fd69fcb1b40e",
      "parents": [
        "1b365931ea8a9d5766972c17c7cf91b9de595fb1"
      ],
      "author": {
        "name": "Wei Hu",
        "email": "wei@aristanetworks.com",
        "time": "Mon Apr 30 14:02:08 2018 -0700"
      },
      "committer": {
        "name": "David Hendricks",
        "email": "david.hendricks@gmail.com",
        "time": "Sun May 06 20:56:02 2018 +0000"
      },
      "message": "flashchips: Add SST26VF016B(A), SST26VF032B(A), SST26VF064B(A)\n\nThis patch seems to have originally been from\nhttps://patchwork.coreboot.org/patch/4126/ . The most recent version\nseems to be in OpenEmbedded (commit 503a572) which added support for\n16Mbit and 32Mbit variants.\n\nThe OpenEmbedded patch also makes changes to linux_spi.c to add some\ndebug prints which are omitted in this version.\n\nFrom the original commit message:\nDifferences between SST26 and SST25:\n1. The WREN instruction must be executed prior to WRSR [Section 5.31].\n   There is no EWSR.\n2. Block protection bits are no longer in the status register. There\n   is a dedicated 144-bit register [Table 5-6].  The device is\n   write-protected by default. A Global Block-Protection Unlock\n   command unlocks the entire memory [Section 4.1].\n\nChange-Id: Ib019bed8ce955049703eb3376c32a83ef607c219\nSigned-off-by: Wei Hu \u003cwei@aristanetworks.com\u003e\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@student.tuwien.ac.at\u003e\nReviewed-on: https://review.coreboot.org/25962\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "e083880279119677e443fc16b4694f8c81bf2c40",
      "tree": "03413b996779bc4c86ec41590f3e7bcdd97d0ef5",
      "parents": [
        "124ef38f7afc61ad7c713c22aad7c5c7f79bdb9b"
      ],
      "author": {
        "name": "Elyes HAOUAS",
        "email": "ehaouas@noos.fr",
        "time": "Mon Apr 02 11:14:02 2018 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Tue Apr 24 20:21:41 2018 +0000"
      },
      "message": "Remove address from GPLv2 headers\n\nChange-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/25381\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n"
    },
    {
      "commit": "1f081530b60ee805532f106f59cc33973e160481",
      "tree": "ebb7155eaeda5f891a435d4087e6532ccb8a15c5",
      "parents": [
        "8b2152d54a67e4139525ce49aefe1a6d0e41b85c"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat Oct 14 15:01:13 2017 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Nov 05 14:36:50 2017 +0000"
      },
      "message": "spi25_statusreg: Return defined value on failed RDSR\n\nThe interface of spi_read_status_register() is broken and can\u0027t return\nerrors. Let\u0027s not return random stack data at least.\n\nChange-Id: I714b20001a5443bba665c2e0061ca14069777581\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22017\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n"
    },
    {
      "commit": "bcf6109a76a873fc1227402d4b5b13a87dc3eb1a",
      "tree": "a3b5a06e4e58d208ecf22c956cd8c160b4d52ebc",
      "parents": [
        "94d8665ea34cb9678c4b08ea340c4a292e520a1d"
      ],
      "author": {
        "name": "Ben Gardner",
        "email": "bgardner@wabtec.com",
        "time": "Sun Nov 22 02:23:31 2015 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sun Nov 22 02:23:31 2015 +0000"
      },
      "message": "Add support for SST SST25WF020A, SST25WF040B, SST25WF080B\n\nApart from the strange ID (using Sanyo\u0027s vendor ID 0x62) the main\ndifference from the plain SST25WF series is that they lack op codes\n0xAD (AAI Word program) and 0x52 (32K erase). The smallest version\ndoes not support dual I/O operations either.\n\nSST25WF080B was tested under Linux with spidev.\n\nCorresponding to flashrom svn r1901.\n\nTested-by: Ben Gardner \u003cbgardner@wabtec.com\u003e\nSigned-off-by: Ben Gardner \u003cbgardner@wabtec.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "5c316f954941241ed75a1f00f00bf1bff318488a",
      "tree": "ce836bcb29d7d9da86ee583a88236b020985ba36",
      "parents": [
        "dc627931848ed6af40be4f7d5bdb8e33d28b8333"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sun Feb 08 21:57:52 2015 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sun Feb 08 21:57:52 2015 +0000"
      },
      "message": "Add a bunch of new/tested stuff and various small changes 22\n\nTested mainboards:\nOK:\n - AOpen UK79G-1394 (used in EZ18 barebones)\n   Reported by Lawrence Gough\n - ASUS M4N78 SE\n   Reported by Dima Veselov\n - ASUS P5LD2-VM\n   Mark board enable as tested (reported by Dima Veselov)\n - GIGABYTE GA-970A-UD3P (rev. 2.0)\n   Reported by trucmar on IRC\n - GIGABYTE GA-990FXA-UD3 (rev. 4.0)\n   Reported by ROKO__ on IRC\n - GIGABYTE GA-H77-DS3H (rev. 1.1)\n   Reported by Evgeniy Edigarev\n - GIGABYTE GA-P55-USB3 (rev. 2.0)\n   Reported by Måns Thörnqvist\n - MSI MS-7817 (H81M-E33)\n   Reported by Igor Kolker\n\nChipsets:\n - Marked Intel Bay Trail (0x0f1c) as tested OK\n   Reported by Antonio Ospite\n - Refine Intel IDs\n    * Add IDs for Braswell\n    * Add IDs for 9 Series PCHs (e.g. H97, Z97)\n    * Rename Wellsburg devices slightly\n\nFlash chips:\n - Atmel AT25DF041A to PREW (+PREW)\n   Reported by Tai-hwa Liang\n - Atmel AT26DF161 to PREW (+EW)\n   Reported by Steve Shenton\n - Atmel AT45DB011D to PREW (+PREW)\n   Reported by The Raven\n - Atmel AT45DB642D to PREW (+PREW)\n   Reported by Mahesh Mokal\n - Eon EN25F32 to PREW (+PREW)\n   Reported by Arman Khodabande\n - Eon EN25F40 to PREW (+REW)\n   Reported by Jerrad Pierce\n - Eon EN25QH16 to PREW (+EW)\n   Reported by Ben Johnson\n - GigaDevice GD25Q20(B) to PREW (+PREW)\n   Reported by Gilles Aurejac\n - Macronix MX25U6435E/F to PR (+PR)\n   Reported by Matt Taggart\n - PMC Pm25LV512(A) to PREW (+PREW)\n   Reported by The Raven\n - SST SST39VF020 to PREW (+PREW)\n   Reported by Urja Rannikko\n - Winbond W25Q40.V to PREW (+EW)\n   Reported by Torben Nielsen\n - Add E variants of MX25Lx006 (MX25L2006E, MX25L4006E, MX25L8006E).\n - Add MX25L6465E variant.\n - There was never a MX25L12805 AFAICT.\n - Split MX25L12805 from models with the same ID but an additional 32 kB\n   eraser: MX25L12835F/MX25L12845E/MX25L12865E.\n - Add a bunch of ST parallel NOR flash chip IDs.\n\nMiscellaneous:\n - Whitelist ThinkPad X200.\n - Constify master parameter of register_master().\n - Remove FEATURE_BYTEWRITES because it was never used at all.\n - Refine hwseq messages and make them less prominent.\n - Fix the yet unused PRIxCHIPADDR format string thingy.\n - Fix copy\u0026paste error in spi_prettyprint_status_register_bp().\n   Spotted by Pablo Cases.\n - Add an additional SMBus controller revision to identify another Yangtze\n   model. Thanks to Dan Christensen for reporting this issue.\n - dediprog: add missing include for stdlib.h.\n   This fixes (at least) building on FreeBSD and DragonflyBSD with gcc.\n - Remove references to struct pci_filter from programmer.h.\n   It is only needed in internal.c where it has a complete type. Having\n   it in programmer.h provokes a warning by some old versions of gcc.\n - Tiny other stuff.\n\nCorresponding to flashrom svn r1879.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "a60d408a78be0e0d34dda616977489a307cb98b6",
      "tree": "012c6fd5e70fa651b144f556c7e3a0b3f605d18a",
      "parents": [
        "2a10e70cd3b3e974c173b035dae01bf53899c228"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Wed Jun 04 16:17:03 2014 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Wed Jun 04 16:17:03 2014 +0000"
      },
      "message": "Add support for Sanyo LE25FW106\n\nAlso, add spi_disable_blockprotect_bp1_srwd().\n\nOriginally written and tested by The Raven \u003coriginalraven@hotmail.com\u003e.\n\nCorresponding to flashrom svn r1818.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "12f3d51a8eec91f04fdd67652114d6d8529dc8b8",
      "tree": "886fdfa5be8927d516c8922f537a59dc461c78e7",
      "parents": [
        "85f09f72f18f14eb3b06dcfbc448e16145b75fd2"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Tue May 27 21:27:27 2014 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Tue May 27 21:27:27 2014 +0000"
      },
      "message": "Rename some spi_prettyprint_status_register_* functions\n\nSpi_prettyprint_status_register_default_bpX -\u003e\nspi_prettyprint_status_register_bpX_srwd\n\nWhy was the default in there anyway? :)\n\nCorresponding to flashrom svn r1802.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "85f09f72f18f14eb3b06dcfbc448e16145b75fd2",
      "tree": "72094e403ba57a0e9746ce6b7230b635d1198f52",
      "parents": [
        "df64a42d6d6232af9aac20c7d2aedb4d527eaeef"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Tue May 27 21:27:14 2014 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Tue May 27 21:27:14 2014 +0000"
      },
      "message": "Add support for ESMT F25L32PA\n\nCorresponding to flashrom svn r1801.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "c2eec2c92015785ead5a5bcba4ce3a42501084c8",
      "tree": "830a7bc9e2b33e1e56809979affa14d6ca0915bd",
      "parents": [
        "f80419c75a344b303275e380add3b8cb750bab9d"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sat May 03 21:33:01 2014 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sat May 03 21:33:01 2014 +0000"
      },
      "message": "Add a bunch of new/tested stuff and various small changes 20\n\nTested mainboards:\nOK:\n - abit BX6 2.0\n   Reported by Stefan Tauner\n - Acer EM61SM/EM61PM (used in Acer Aspire T180)\n   Reported by Benjamin Bellec\n - ADLINK Express-HR\n   Reported by Obermair Thomas\n - ASUS M3N-H/HDMI\n   Reported by Franc Serres\n - Attro G5G100-P\n   Reported by Christoph Grenz\n - ASRock 960GM-GS3 FX\n   Reported by Fuley Istvan\n - Elitegroup P6BAP-A+ (V2.2)\n   Reported by Arnaldo Pirrone\n - Elitegroup GeForce7050M-M (V2.0)\n   Reported by Leif Middelschulte\n - Fujitsu D3041-A1 (used in ESPRIMO P2560)\n   Reported by Daggi Duck\n - GIGABYTE GA-8S648\n   Reported by TeslaBIOS\n - GIGABYTE GA-970A-D3P (rev. 1.0)\n   Reported by Jean-Francois Pirus\n - GIGABYTE GA-B85M-D3H\n   Reported by Mladen Milinković\n - GIGABYTE GA-X79-UD3\n   Reported by Jeff O\u0027Neil\n - GIGABYTE GA-X79-UP4 (rev. 1.0)\n   Reported by George Spelvin\n - GIGABYTE GA-Z68MA-D2H-B3 (rev. 1.3)\n   Reported by Vangelis Skarmoutsos\n - GIGABYTE GA-Z87-HD3\n   Reported by virii5\n - Lenovo Tilapia CRB\n   Reported by jenkins56 on IRC\n - MSI GT60-2OD (notebook, only with layout patches)\n   Reported by Vasiliy Vylegzhanin\n - MSI MS-6704 (845PE Max2 PCB 1.0) (Pure Version w/o raid)\n   Reported by professorll\n - MSI MS-7399 1.1 (used in Acer Aspire M5640/M3640)\n   Reported by Koen Rousseau\n - MSI MS-7125 (K8N Neo4(-F/FI/FX))\n   We had a board enable for that one for years, but it was not (and still is not)\n   completely clear which boards are covered.\n - MSI MS-7522 (MSI X58 Pro-E)\n   Reported by Gianluigi Tiesi\n - PCWARE APM80-D3\n   Reported by César Augusto Jakoby\n - Pegatron IPP7A-CP\n   Reported by Илья Шипко\n - Supermicro H8QME-2\n   Reported by Greg Tippitt\n - Supermicro X7SPA-H\n   Reported by Kyle Bentley\n - Supermicro X7SPE-HF-D525\n   Reported by Micah Anderson\n - Supermicro X8DTE\n   Reported by Mark Nipper\n - Supermicro X8SIL-F\n   Reported by Peter Samuelson\n - ZOTAC IONITX-A (-E) version\n   Reported by Maciej Wroniecki\nNOT OK:\n - Supermicro X10SLM-F\n   Reported by Micah Anderson\n\nFlash chips:\n - Atmel AT29C020 to PREW (+PREW)\n   It was marked like that in the past, but I could not find the reason why the\n   test bits were reset. Urja Rannikko tested it again and it still works.\n - Eon EN25F10 to PREW (+PREW)\n   Reported by Stolmár Tamás\n - Eon EN25QH64 to PR (+PR)\n   Reported by Vladimir \u0027φ-coder\u0027 Serbinenko\n - GigaDevice GD25Q32(B) to PREW (+PREW)\n   Reported by mrnuke\n - Macronix MX25L512(E)/MX25V512(C) to PREW (+PREW)\n   Reported by Jamie Nichol\n - Macronix MX25L2005(C) to PREW (+PREW)\n   Reported by Давыдов Дмитрий\n - Micron/Numonyx/ST N25Q064..1E to PREW (+PREW)\n   Reported by Paolo Zambotti\n - Pmc Pm25LD010(C) to PREW (+PREW)\n   Reported by Vasile Ceteras\n - Micron/Numonyx/ST M25P16 to PREW (+EW)\n   Reported by raven\n - Micron/Numonyx/ST M25PX64 to PREW (+W)\n   Reported by Zaolin\n - SST SST25VF020B to PREW (+PREW)\n   Reported by Michaël Zweers\n - SST SST49LF040 to PREW (+W)\n   Reported by Oskar Enoksson\n - Add support for MX25L3273E (evil twin of MX25L3205 et al.)\n   Also, add MX25L1673 and MX25L6473E to the names of their twins and\n   add a note about MX25L8073E.\n - Winbond W25X32 to PREW (+REW)\n   Reported by The Raven\n - Winbond W29C010 etc. to PREW (+W)\n   Reported by san\n\nChipsets tested OK:\n - Intel NM70 (8086:1e5f)\n   Reported by mrnuke\n - Intel C204 (8086:1c54)\n   Reported by Vasiliy Vylegzhanin\n - Intel QM67 (8086:1c4f)\n   Reported by Obermair Thomas\n - Intel HM77 (8086:1e57)\n   Reported by Vasiliy Vylegzhanin\n - Intel B85 (8086:8c50)\n   Reported by Mladen Milinković\n - Intel HM87 (8086:8c4b)\n   Reported by Vasiliy Vylegzhanin\n - Intel Z87 (8086:8c44)\n   Reported by virii5\n - NVIDIA MCP51 (10de:0261)\n   Reported by Marcin Kościelnicki\n - SiS 648 (1039:0648)\n   Reported by TeslaBIOS\n\nMiscellaneous:\n - Mark ARM-USB-TINY-H as tested in ft2232_spi (reported by _nanodev_).\n - getrevision.sh: Ignore failing date calls.\n - getrevision.sh: Fix -u and -l for older git versions which require \u003d for the\n   git log grep parameter.\n - Corrected K8T Neo2-F entries due to a report from Stelios Tsampas.\n - Add \"-p internal\" to output that requests users to send flashrom -V logs.\n - Add Macbook2,1, Thinkpad X230, EasyNote LM85 to laptop whitelist.\n - Tiny other stuff.\n\nCorresponding to flashrom svn r1783.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "db4e87dccf040f29dca18571bc455ee23fb430eb",
      "tree": "d88ea1cd6abaa3cbad69fb447eb6dc0092fbb78e",
      "parents": [
        "6db8bad530612262a42c492f06816eb85b8598fc"
      ],
      "author": {
        "name": "Aidan Thornton",
        "email": "makosoft@gmail.com",
        "time": "Tue Aug 27 18:01:53 2013 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Tue Aug 27 18:01:53 2013 +0000"
      },
      "message": "Add support for Atmel AT45DB* chips\n\nCorresponding to flashrom svn r1723.\n\nSigned-off-by: Aidan Thornton \u003cmakosoft@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "0554ca5cd33fe2cc599cfdbe91fff03c8fa752c5",
      "tree": "1d37d76b5b3d810c6b2a1286a5de7c2b60ce69a0",
      "parents": [
        "305e0b999a7d452a845709d5558c17a31afe178c"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Thu Jul 25 22:54:25 2013 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Thu Jul 25 22:54:25 2013 +0000"
      },
      "message": "Add a bunch of new/tested stuff and various small changes 18\n\nTested mainboards:\nOK:\n - ASUS C60M1-I\n   http://www.flashrom.org/pipermail/flashrom/2013-February/010578.html\n - ASUS P8H77-I\n   http://www.flashrom.org/pipermail/flashrom/2013-March/010607.html\n - ASUS P8H77-M\n   http://www.flashrom.org/pipermail/flashrom/2013-May/010994.html\n - ASUS P8P67 LE (B2)\n   http://www.flashrom.org/pipermail/flashrom/2013-May/010972.html\n - Elitegroup GeForce6100PM-M2 (V3.0)\n   http://www.flashrom.org/pipermail/flashrom/2013-July/011177.html\n - GIGABYTE GA-P55A-UD7\n   http://www.flashrom.org/pipermail/flashrom/2013-July/011302.html\n - MSI B75MA-E33 (MS-7808)\n   http://www.flashrom.org/pipermail/flashrom/2013-March/010659.html\n - MSI H77MA-G43 (MS-7756)\n   http://www.flashrom.org/pipermail/flashrom/2013-April/010853.html\n - MSI KA780G (MS-7551)\n   http://paste.flashrom.org/view.php?id\u003d1617\n - SAPPHIRE IPC-E350M1\n   Reported by xvilka on IRC\n - Supermicro X8DTG-D\n   http://www.flashrom.org/pipermail/flashrom/2013-July/011305.html\nNOT OK:\n - ASRock Fatal1ty Z77 Performance\n   http://www.flashrom.org/pipermail/flashrom/2013-January/010467.html\n - ASRock Z68 Extreme4\n   http://www.flashrom.org/pipermail/flashrom/2013-May/010984.html\n - ASUS P8B75-M LE\n   http://www.flashrom.org/pipermail/flashrom/2013-April/010867.html\n - ASUS P8P67-M PRO\n   http://www.flashrom.org/pipermail/flashrom/2013-February/010541.html\n - ASUS P8Z68-V LE\n   http://www.flashrom.org/pipermail/flashrom/2013-February/010582.html\n - Intel DQ77MK\n   http://paste.flashrom.org/view.php?id\u003d1603\n - Supermicro X9DRD-7LN4F\n   http://paste.flashrom.org/view.php?id\u003d1582\n - Supermicro X9SCE-F\n   http://www.flashrom.org/pipermail/flashrom/2013-February/010588.html\n - Supermicro X9SCM-F\n   http://www.flashrom.org/pipermail/flashrom/2013-February/010527.html\n - Tyan S7066\n   http://www.flashrom.org/pipermail/flashrom/2013-March/010630.html\n\nChipsets:\n - Marked Intel B75 as tested\n   http://www.flashrom.org/pipermail/flashrom/2013-March/010659.html\n - Marked Intel H77 as tested\n   http://www.flashrom.org/pipermail/flashrom/2013-March/010607.html\n - Removed 10de:03e2 because it is apparently the MCP61 host bridge.\n   It was reclassified to Host Bridge in the PCI device ID database and there\n   is at least one report suggesting this configuration too:\n   http://www.flashrom.org/pipermail/flashrom/2012-August/009716.html\n - Added MCP89 which hopefully works with the code for previous versions.\n   Thanks to James Laird for submitting this change.\n\nTested flash chips:\n - Atmel AT25DF641(A) to PREW (+PREW)\n   http://www.flashrom.org/pipermail/flashrom/2013-June/011113.html\n - Atmel AT25F512 to PREW (+PREW)\n   http://www.flashrom.org/pipermail/flashrom/2013-April/010904.html\n   Also, change its ID according to Modification of PCN SC040401A:\n   \"There has been a change in the returned value of the Product Identification\n   (RDID) command, the AT25F512A RDID code is 65h compared to 60h from\n   the AT25F512 product.\"\n   It seems to be quite likely that all AT25F512 are fully functional relabeled\n   AT25F1024 chips. There are even some hints in the datasheet:\n   in table 6 they stress that address pin 16 needs to be low under all circum-\n   stances; while continuous reads can wrap around on the AT25F1024 the DS\n   notes \"For the AT25F512, the read command must be terminated when the\n   highest address (00FFFF) is reached.\" OTOH the lock bit semantics are\n   different, but this has not been tested thoroughly\n - Atmel AT25F512A to PREW (+PREW)\n   http://paste.flashrom.org/view.php?id\u003d1569\n - Eon EN25F05 to PREW (+PREW)\n   http://paste.flashrom.org/view.php?id\u003d1571\n - Macronix MX25L12805(D) to PREW (+REW)\n   http://www.flashrom.org/pipermail/flashrom/2013-April/010913.html\n - Spansion S25FL256S......0 and S25FL512S to P/!R!E!W (+P)\n   Tested by Stefan Tauner\n - Micron/Numonyx/ST M25PX80 to PREW (+PREW)\n   Tested by Stefan Tauner\n - Micron/Numonyx/ST N25Q032..3E and N25Q128..3E to PREW (+PREW)\n   Tested by Stefan Tauner\n - Micron/Numonyx/ST N25Q256..3E and N25Q512..3G to P/!R!E!W (+P)\n   Tested by Stefan Tauner\n - SST SST25VF040B to PREW (+PREW)\n   http://paste.flashrom.org/view.php?id\u003d1574\n - SST SST25VF040B.REMS to PREW (+EW)\n   http://paste.flashrom.org/view.php?id\u003d1575\n - ST M25P05-A to PREW (+PREW)\n   http://paste.flashrom.org/view.php?id\u003d1576\n - ST M29W512B to PREW (+W)\n   http://www.flashrom.org/pipermail/flashrom/2013-March/010635.html\n - Winbond W25Q64.W to PREW (+PREW)\n   Tested by the chromiumos guys.\n - Winbond W25Q128.V to PREW (+REW)\n   http://www.flashrom.org/pipermail/flashrom/2013-June/011108.html\n - Winbond W25X20 to PREW (+PREW)\n   http://www.flashrom.org/pipermail/flashrom/2013-May/010990.html\n\nMiscellaneous:\n - Add Lenovo X201 to the laptop whitelist.\n - Add chip IDs for the ESMT F25L..QA family.\n - Add chip IDs for a few Macronix MX25 models.\n - The list of flashchips is not sorted strictly alphabetically and should not be\n   either. Refine the comment explaining the scheme on top of the list.\n - Support -L output of chip sizes with up to 6 decimal places (up to 4 Gb).\n - Use z length modifier in (more) prints for size_t types.\n - Remove chips \u003e16MB again because our current implementation of memory mapping\n   the flash chip violates common rules by mapping a window as large as the chip.\n   This leads to failing mmaps as can be seen here:\n   http://paste.flashrom.org/view.php?id\u003d1695\n - Document spispeed parameter of linux_spi (and fix some leaks).\n - Rephrase the \"multiple chips detected\" message because it was confusing.\n - Skip verification step if the image is equal to the flash contents.\n - Tiny other stuff.\n\nCorresponding to flashrom svn r1702.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n"
    },
    {
      "commit": "6f59b0bc5124f47294e261bb20924f9a8e505d89",
      "tree": "4fb4121d32185587067e5d50723ec879d56b8dbe",
      "parents": [
        "c80c4a35a0d4eb51c142fc53ee4ae6d82f4dc37a"
      ],
      "author": {
        "name": "Nikolay Nikolaev",
        "email": "evrinoma@gmail.com",
        "time": "Fri Jun 28 21:29:51 2013 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Fri Jun 28 21:29:51 2013 +0000"
      },
      "message": "Add support for remaining Numonyx (Micron) N25Q chips\n\nAdd...\n - N25Q128..3E\n - N25Q128..1E\n - N25Q256..1E (defunct due to addressing)\n - N25Q256..3E (defunct due to addressing)\n - N25Q512..1E (defunct due to addressing)\n - N25Q512..3E (defunct due to addressing)\n - N25Q00A..3G (defunct due to addressing)\n\nAlso, refine existing family members.\n\nCorresponding to flashrom svn r1693.\n\nSigned-off-by: Nikolay Nikolaev \u003cevrinoma@gmail.com\u003e\nReviewed-by: Steven Zakulec \u003cspzakulec@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "c80c4a35a0d4eb51c142fc53ee4ae6d82f4dc37a",
      "tree": "51a1339cfa3b916613a092a2a50106c671b7916f",
      "parents": [
        "0ec2f7e7e00d27c9551e7fe7c8f5497d87475be2"
      ],
      "author": {
        "name": "Nikolay Nikolaev",
        "email": "evrinoma@gmail.com",
        "time": "Fri Jun 28 21:29:44 2013 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Fri Jun 28 21:29:44 2013 +0000"
      },
      "message": "Add support for Spansion S25FL...S chips\n\nAdd...\n - S25FL128S\n - S25FL256S uniform version (defunct due to addressing)\n - S25FL512S uniform version (defunct due to addressing)\n\nMerge Intel S33 status register functions with this one\u0027s.\n\nCorresponding to flashrom svn r1692.\n\nSigned-off-by: Nikolay Nikolaev \u003cevrinoma@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "d0e3ea1470eb7e16082a853aca5010d20dc0879b",
      "tree": "f381998972806961af753464911f93de9fd3ee47",
      "parents": [
        "01dac17ec586e0476eaea3410d68d516fd6d6a61"
      ],
      "author": {
        "name": "Nikolay Nikolaev",
        "email": "evrinoma@gmail.com",
        "time": "Fri Jun 28 21:29:08 2013 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Fri Jun 28 21:29:08 2013 +0000"
      },
      "message": "Add support for Eon EN25S series\n\nAdd...\n - EN25S10\n - EN25S20\n - EN25S40\n - EN25S80\n - EN25S16\n - EN25S32\n - EN25S64\n\nCorresponding to flashrom svn r1687.\n\nSigned-off-by: Nikolay Nikolaev \u003cevrinoma@gmail.com\u003e\nReviewed-by: Steven Zakulec \u003cspzakulec@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "b6b00e99aac373176e612c79b4579c9e577bd2ed",
      "tree": "b5193c315ee7ea51071874ed8c30435a4aee7e71",
      "parents": [
        "579f1e0b67a49282684a39f6c08bcf0813bd3c5c"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Fri Jun 28 21:28:43 2013 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Fri Jun 28 21:28:43 2013 +0000"
      },
      "message": "Add support for Nantronics N25 series\n\nAdd...\n - N25S10\n - N25S20\n - N25S40\n - N25S80\n - N25S16\n\nCorresponding to flashrom svn r1683.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n"
    },
    {
      "commit": "278ba6e96766f1d17202642a720f4e4eac007c74",
      "tree": "f0520da2262238adda4fb28a94fda700722c5bf4",
      "parents": [
        "682122bce7714e285d196be09d4c97666458c487"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Fri Jun 28 21:28:27 2013 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Fri Jun 28 21:28:27 2013 +0000"
      },
      "message": "Introduce additional SPI status register helpers\n\n - spi_prettyprint_status_register_default_welwip():\n   It just prettyprints the plain hex value and the welwip bits.\n - spi_prettyprint_status_register_default_bp4():\n   Prints the hex value, welwip, bp0-5 and srwd bits.\n - spi_disable_blockprotect_bp2_srwd(),\n - spi_disable_blockprotect_bp3_srwd() and\n   spi_disable_blockprotect_bp4_srwd():\n   Three new common block unprotection functions for the frequent\n   cases where there is a status register lock bit at bit #7 and some\n   block protection bits at bits #2-#4, #2-#5 and #2-#6 respectively.\n\nCorresponding to flashrom svn r1681.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "cecb2c56d07ac45cde56cadc6416e653b0cfafb7",
      "tree": "81788790601ca10fea904cef17f4694134ecbc3d",
      "parents": [
        "0466c819e248881e03a6ec98db5297565816859b"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Thu Jun 20 22:55:41 2013 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Thu Jun 20 22:55:41 2013 +0000"
      },
      "message": "Fix unlocking function for most Atmel AT2[56]D* chips\n\nI broke unlocking them correctly in r1635 while refactoring (NB: the\ncommit log including the overly selfconfident statement about the\n\"bug in spi_disable_blockprotect_at25df()\").\n\nAffected chips have per sector protection bits and the write protection bits\nin the status register do indicate if none, some or all sectors are protected.\nIt is possible to globally (un)lock all sectors at once but in a way that was\nnot anticipated when refactoring the spi25 unlocking functions into\nspi_disable_blockprotect_generic(). To globally unprotect not only the\nprotection bits (2 and 3) have 0 to be written to them but also bits 4 and 5\nwhich normally would not be touched by spi_disable_blockprotect_generic().\nSome of the chips also support a permanent lockdown with fuses which we\ndo not handle yet.\n\nTo fix this without copying the whole method I introduce another mask\nparameter to spi_disable_blockprotect_generic() namely unprotect_mask.\nSee verbose comments inline for details.\n\nAlso, prettyprint the status register after trying to disable the block\nprotection fails.\n\nCorresponding to flashrom svn r1679.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nTested-by: Chi Zhang \u003czhangchi866@gmail.com\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "f44516121aecbd307a9398fe9bc1ec9ce25bfb09",
      "tree": "87438afed9b3bfa3b4d901c25ccd82df0b982bb4",
      "parents": [
        "3f5e35db4b22d36918adc7ee28b0d77ee50af568"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Fri Apr 19 01:59:15 2013 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Fri Apr 19 01:59:15 2013 +0000"
      },
      "message": "Add support for PMC Pm25LD series\n\nThis patch adds support for\n - Pm25LD256C\n - Pm25LD512(C)\n - Pm25LD010(C)\n - Pm25LD020(C)\n - Pm25LD040(C)\n\nThese seem to be the successors of the Pm25LV series.\nThe main difference seems to be the dual I/O and additional erase opcodes.\nSome support an additional, complex locking register (maybe all of the\nabove, but available datahsheets do not indicate it for all).\n\nThe Pm25LD512C was tested by Chi Zhang:\nhttp://paste.flashrom.org/view.php?id\u003d1579\n\nCorresponding to flashrom svn r1671.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "57794ac1580fc5efee3ba01a0c3e4539bb58d088",
      "tree": "4212a02023a6a8c6dd0b03d234e66471ddb5d634",
      "parents": [
        "54aaa4ae2bb4026ae7acbf3e0aafe8542aaff2a4"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sat Dec 29 15:04:20 2012 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sat Dec 29 15:04:20 2012 +0000"
      },
      "message": "Add support for Atmel\u0027s AT25F series of SPI flash chips\n\nThis adds support for the following chips:\n - AT25F512, AT25F512A, AT25F512B\n - AT25F1024, AT25F1024A\n - AT25F2048\n - AT25F4096\n\nBesides the definitions of the the chips in flashchips.c this includes\n- a dedicated probing method (probe_spi_at25f)\n- pretty printing methods (spi_prettyprint_status_register_at25f*), and\n- unlocking methods (spi_disable_blockprotect_at25f*)\n\nCorresponding to flashrom svn r1637.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "54aaa4ae2bb4026ae7acbf3e0aafe8542aaff2a4",
      "tree": "b394950b3bd52b2490e1da77a1c497516d6bfd06",
      "parents": [
        "9530a02212bd48aca32752250c4e2ec91e24d3b6"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sat Dec 29 15:04:12 2012 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sat Dec 29 15:04:12 2012 +0000"
      },
      "message": "Add support for Intel S33 series flash chips\n\nThis includes:\nBottom boot block:\n* 16Mb/2MB:\n  QB25F160S33B8, QB25F016S33B8, QH25F160S33B8, QH25F016S33B8\n* 32Mb/4MB:\n  QB25F320S33B8, QH25F320S33B8\n* 64Mb/8MB:\n  QB25F640S33B8, QH25F640S33B8\n\nTop boot block:\n* 16Mb/2MB:\n  QB25F160S33T8, QB25F016S33T8, QH25F160S33T8, QH25F016S33T8\n* 32Mb/4MB:\n  QB25F320S33T8, QH25F320S33T8\n* 64Mb/8MB:\n  QB25F640S33T8, QH25F640S33T8\n\nAt least some seem to be marketed by other vendors (too?) but also with\nIntel\u0027s vendor ID.\n\nBesides a 0xC7 chip erase and a 0xD8 uniform 64kB block erase they\nsupport also erasing the top/bottom 8 8kB blocks with opcode 0x40.\nBut since this command fails for all addresses outside those ranges,\nit is not easily implemented with flashrom\u0027s current code base and\nhence left out.\n\nCorresponding to flashrom svn r1636.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "9530a02212bd48aca32752250c4e2ec91e24d3b6",
      "tree": "26d266ad7941e4efd06a21ac44daba46e1281ab4",
      "parents": [
        "6ee37e28365f2a8ea498d03b08def0dcb1cc6494"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sat Dec 29 15:04:05 2012 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sat Dec 29 15:04:05 2012 +0000"
      },
      "message": "Add a generic SPI block unprotect function\n\nThis does not only remove a huge pile of duplicate code, it does\nalso fix a bug in spi_disable_blockprotect_at25df(), which is also\na good example why duplicated code is a bad idea.\n\nCorresponding to flashrom svn r1635.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "6ee37e28365f2a8ea498d03b08def0dcb1cc6494",
      "tree": "3328db4647bba505d32ebc5755c511728cec438e",
      "parents": [
        "2c421199ab37e691a83ad09b542ed43ee5811603"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sat Dec 29 15:03:51 2012 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sat Dec 29 15:03:51 2012 +0000"
      },
      "message": "Improve SPI status register pretty printing\n\n - Move all functions related to SPI status registers to a new file\n   spi25_statusreg.c. This includes the generic as well as the\n   SST-specific functions from spi25.c and the chip-specific functions\n   from a25.c and at25.c.\n - introduce helper functions\n    * spi_prettyprint_status_register_hex()\n    * spi_prettyprint_status_register_bpl()\n    * spi_prettyprint_status_register_plain()\n   Use the latter on every compatible flash chip that has no better printlock\n   function set and get rid of the implicit pretty printing in the SPI probing\n   functions.\n - remove\n    * spi_prettyprint_status_register_common()\n    * spi_prettyprint_status_register_amic_a25lq032() because it can be fully\n      substituted with spi_prettyprint_status_register_amic_a25l032().\n    * spi_prettyprint_status_register() (old switch, no longer needed)\n - promote and export\n    * spi_prettyprint_status_register_amic_a25l05p() as spi_prettyprint_status_register_default_bp1().\n    * spi_prettyprint_status_register_amic_a25l40p() as spi_prettyprint_status_register_default_bp2().\n    * spi_prettyprint_status_register_st_m25p() as spi_prettyprint_status_register_default_bp3().\n - add #define TEST_BAD_REW and use it for a number of Atmel chips which\n   had only TEST_BAD_READ set even though they dont have erasers or a write\n   function set.\n\nCorresponding to flashrom svn r1634.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    }
  ]
}