)]}' { "log": [ { "commit": "610c1aad71bfa118c4f49ac01761f586b8dede69", "tree": "8ad4cfd904cf909526b32b03561ad369f42720d9", "parents": [ "b95fe9b9751746b269a3bbd7021cf731d8553715" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Feb 15 02:56:05 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 15 14:27:20 2026 +0000" }, "message": "spi: Pass master instead of flash to .send_command\n\nIn the SPI-master API, `.send_command` should only forward commands to\nthe SPI bus. All details about the commands and the SPI slave should be\nhandled in the chip driver. Hence, replace the `flashctx` pointer with\none to the `spi_master` to enforce proper separation.\n\nChange-Id: I50934a1294217794b7e23cc98ade7e4279c059a1\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74897\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "39a4f7d5a0d89494a3ed92ffa07e7a69f755cbdc", "tree": "bff14ca76e24ec28e6cee0c7a4401c3e72404bed", "parents": [ "404529d755d07f450babca258dcff5f85a8713d9" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Dec 04 22:40:37 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Feb 24 10:56:47 2025 +0000" }, "message": "sb600spi: Request more `lspci` details\n\nWhen asking the use for `lspci` output, suggest to use `sudo` and\n`-xxx`. The standard registers dumped with `-x` are not very inte-\nresting, and `-xxx` requires root access.\n\nChange-Id: I7a5bc5eb425542d8109ad504cbf77d33e43459b1\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/311\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "9a11cbf21a5078bcdb8db7584c44a9ee17020db4", "tree": "e67a9eadfdb7a71f81df36c7e97180474a8c59df", "parents": [ "aabb3e0ff54e87c0136c91f105e506ed19184cc6" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 13 01:19:07 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:40:04 2024 +0000" }, "message": "Let the flash context directly point to the used master\n\nWe used to have a pointer to a full `registered_master` struct in\nour flash context. Beside the used master, this contained a bit\nmask of supported buses. Oddly convenient, this bit mask invited\nto bypass the chip driver and break the abstraction. It allowed\nto place bus-specific details virtually anywhere in flashprog,\nmaking it harder to find a good place for them.\n\nSo, get rid of the `buses_supported` bit mask by pointing directly\nto the master. Only the chip driver will implicitly know which type\nof master is used.\n\nChange-Id: I9ce13d8df0e7ccc67519d888dd9cb2e2ff8d6682\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72533\n" }, { "commit": "89569d60e3aeeec651496b2e7a2e6064d782ab3b", "tree": "bf0c3951886de60086d32ff6e1a850adad926da6", "parents": [ "929d2e1b17a448d3352dbecb6a620ee0c1e65a58" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 12 23:31:40 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "memory_mapped: Reduce `decode_sizes` to a single `max_rom_decode`\n\nWe used to store the maximum decode size, i.e. the maximum memory-mapped\nrange of the flash chip, per bus type (Parallel, LPC, FWH, SPI). There\nwas no programmer in the tree that really made use of it, though:\n* The chipset drivers usually focus on a single bus type. And even if\n they advertise the whole default set (PAR, LPC, FWH), they only pro-\n vide a maximum decode size for one of them. The latter is probably\n wrong, should really more than one bus type be supported.\n* PCI and external programmers all support only a single bus type, with\n the exception of `serprog` which doesn\u0027t set a maximum decode size.\n\nWhat made the distinction even less useful is that for some chips that\nsupport multiple bus types, i.e. LPC+FWH, we can\u0027t even detect which\ntype it is. The existing code around this also only tried to provide\nthe best possible warning message at the expense of breaking the pro-\ngrammer abstraction.\n\nHence, unify the set of sizes into a single `max_rom_decode` property.\nWe store it inside the `registered_master` struct right away, to avoid\nany more use of globals.\n\nChange-Id: I2aaea18d5b4255eb843a625b016ee74bb145ed85\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72531\n" }, { "commit": "c3b02dce51aad2766512d1939a1b7447c2d526b8", "tree": "58069f464bb8a777ef06e93767813a4c5a042cb0", "parents": [ "a02df33fbf1c196395a61049e60895d4ae0e0a5b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Aug 12 01:13:45 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Sep 18 19:24:39 2023 +0000" }, "message": "Rebrand to flashprog and update URLs\n\nMostly automated `sed` work. As of now, URLs to the old wiki are broken\neither way, so changing them shouldn\u0027t hurt. Other URLs (e.g. to mailing\nlist archives) were hopefully filtered correctly.\n\nChange-Id: I9d43bfd0e675eff2fcbad05f304b9ce9f5006b08\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashrom-stable/+/21\n" }, { "commit": "4d51e07242459f86d00eaf522786695e46ec2511", "tree": "a513666f34cc601d6a9e9bf4f506383dbf69bcb2", "parents": [ "e3c305dfd234503faa23c5491962db8f52d0134c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 17:56:29 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 28 23:42:48 2023 +0000" }, "message": "amd_imc/sb600spi: Move handle_imc() into amd_imc.c\n\nMove handle_imc() to make it easier to share it with other drivers.\n\nChange-Id: I72dff5feda199e1d258c067e230abdf33c451249\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72575\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0cea753aff33b78051febadf8786df83144b5ee7", "tree": "8972ea6cf44e249659ddad7ea3d9aa2dedffc0b6", "parents": [ "ab9f25893f1fa87cbbaf656869e346391eccdb31" ], "author": { "name": "Aarya Chaumal", "email": "aarya.chaumal@gmail.com", "time": "Mon Jul 04 18:21:50 2022 +0530" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 19 13:50:18 2023 +0000" }, "message": "spi: Add function to probe erase command opcode for all spi_master\n\nAdd a field, probe_opcode, to struct spi_master which points to a\nfunction returning a bool by checking if a given command is supported by\nthe programmer in use. This is used for getting a whitelist of commands\nsupported by the programmer, as some programmers like ichspi don\u0027t\nsupport all opcodes.\n\nMost programmers use the default function, which just returns true.\nICHSPI and dummyflasher use their specialized function.\n\nflashrom-stable: Added `.probe_opcode` for `dirtyjtag_spi`, `ich7`.\n\nChange-Id: I6852ef92788221f471a859c879f8aff42558d36d\nSigned-off-by: Aarya Chaumal \u003caarya.chaumal@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/65183\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72539\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "0b587f921aebd36aaa9f69faea0d2601386d7379", "tree": "c13c57f89dd385d3ed1bd76893cf7a251f8eba1a", "parents": [ "7310f19a07d70a16a0e6342ceb538854729282cd" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Fri Sep 09 23:01:05 2022 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "spi: Make \u0027default_spi_write_aai\u0027 the default unless defined\n\nA NULL func pointer is necessary and sufficient for the\ncondition `NULL func pointer \u003d\u003e default_spi_write_aai\u0027 as to not\nneed this explicit specification of \u0027default\u0027.\n\nTherefore drop the explicit need to specify the \u0027default_spi_write_aai\u0027\ncallback function pointer in the spi_master struct. This is a reasonable\ndefault for every other driver in the tree with only a few exceptions.\n\nThis simplifies the code and driver development.\n\nflashrom-stable: Updated `dirtyjtag_spi` which was added earlier.\n\nChange-Id: I7f14aaea0edcf0c08cea0e9cd27d58152707fb2a\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/67479\nOriginal-Reviewed-by: Peter Marheine \u003cpmarheine@chromium.org\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72369\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "19ce50d3746fb1d9e5238bac49cf88ffe654848e", "tree": "90852ac71da4bc563f5bda33dd2954cd990f1d4b", "parents": [ "6c73e27aa68e0e100f6573cd0910f6f54bff271d" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Sat Nov 13 17:59:18 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "pcidev: Move pci_dev_find() from internal to canonical place\n\nAlso rename to `pcidev_find()` in fitting with pcidev.c helpers.\n\nTested: ```sudo ./flashrom -p internal -r /tmp/bios\n\u003csnip\u003e\nFound Programmer flash chip \"Opaque flash chip\" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000.\nReading flash... done.\n```\n\nChange-Id: Ie21f87699481a84398ca4450b3f03548f0528191\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59280\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72310\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3f4d35daf4533650e75fcabb8f1ed9085e1fcf77", "tree": "ae3340f0a563d1d9ed48285cc861e7e90e2343ef", "parents": [ "a6b45c4516e15aeb405028e5095e86259fcd9e34" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Mon Jan 17 15:11:43 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "hwaccess: move mmio functions into hwaccess_physmap\n\nThe mmio_le/be_read/writex functions are used for raw memory access.\nBundle them with the physmap functions.\n\nChange-Id: I313062b078e89630c703038866ac93c651f0f49a\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/61160\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72278\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "74b4aa0b15439a2ab2474889a7abed978439757a", "tree": "a3e6d01052b04bbae7c71af7c1148d3619ba1ab1", "parents": [ "b3287b43dc2fc90913686eb7ca9adfdedac2fdb4" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Dec 14 17:52:30 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "physmap: rename to hwaccess_physmap, create own header\n\nLine up physmap with the other hwaccess related code.\n\nChange-Id: Ieba6f4e94cfc3e668fcb8b3c978de5908aed2592\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60113\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72267\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d96c97c77309f1cf1ff1cbe9fa521a75fc9d5698", "tree": "2ca206a0bb2873472e243eb2138c7f1e0345abf2", "parents": [ "b7c6a66d5167a9cb6d83081f4c84b7a6c0d28046" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Nov 02 21:03:00 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "pci.h: move include into own wrapper\n\nSplit the include of hwaccess and libpci. There is no need to have pci.h\nincluded in hwaccess.\n\nChange-Id: Ibf00356f0ef5cc92e0ec99f8fe5cdda56f47b166\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58883\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72264\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "51264d5def2188624a3354c62722a95e64224645", "tree": "f8b01a56582b453253d7a7b09b26cedd61bbe96f", "parents": [ "121a5b8d63008db1d179ab69fc1c6b39e03d575c" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.de", "time": "Tue Sep 21 10:00:14 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "remove compile guards\n\nThe build system handles the decision when to build a file.\nExtra compile guards for the source files are not necessary.\n\nChange-Id: I76a76e05c7a7dd27637325ab1e9d8946fd5f9076\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/57797\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72260\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5e08e3e829e3f736e18cef7b8f4a8929c9e06257", "tree": "cfe9483275582e2ff2a50628824cf8e842c1feef", "parents": [ "6c33185c81f4aab0d048be7c4b68dca1a91800c2" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue May 11 17:38:14 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "programmer: Smoothen register_spi_master() API\n\nIt was impossible to register a const struct spi_master that would\npoint to dynamically allocated `data`. Fix that so that we won\u0027t\nhave to create more mutable globals.\n\nChange-Id: I0c753b3db050fb87d4bbe2301a7ead854f28456f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54066\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72179\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "ac90af6cdc747bfe3dc38c83c0b7272addf37659", "tree": "ec67fd7c4d01db82b5a1ffd8c8ed36a7229108dd", "parents": [ "bb4f3b06dcfb60a6ab84750c9b149482dc5ee579" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 18 00:22:47 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 13 01:34:15 2023 +0000" }, "message": "Change references to flashrom-stable\n\nAdapt all mentions of the mailing list and also the version print.\n\nChange-Id: Ib4a3271422ee6cf4d0efb8c3fa858b66a22c0a33\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70922\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "980d6b8d712d26711dcd5a71007e4626c7198cd5", "tree": "38e926243e6a10734971066fd1602d373fd04784", "parents": [ "f25447e5724bd8664338b69b12399f101abed76b" ], "author": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Fri Aug 19 02:48:15 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "tree: Retype variable `programmer_may_write` with bool\n\nUse the bool type instead of an integer for the variable\n`programmer_may_write`, since this represents its purpose much better.\n\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nChange-Id: I69958527ae018a92f1c42734a7990d0c532dee0c\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66885\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71483\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "43040f297e68cd4d826d58f57566581ef902d179", "tree": "a8357aba5a8dbfd43f3e7949c865f2682bf5962d", "parents": [ "4203a47a102e2622f404ee6567b240882d584116" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Thu Jun 23 14:38:35 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "tree: indent struct *_master consistently with tabs\n\nUse `\u003ctab\u003e.key\u003ctab\u003e*\u003d \u003cvalue\u003e,`\n\nTEST: `make VERSION\u003d0 MAN_DATE\u003d0` returns the same flashrom binary\nbefore and after the patch\n\nChange-Id: I1c45ea9804ca09e040d7ac98255042f58b01f8ef\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/65363\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71466\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5eca427ae64519b70d1c4ccfb427305ca9974ba0", "tree": "1ca22ef1e0072a76650fdd182206844f8ebddd7d", "parents": [ "1bbc501f79319cc6c8d839bc44fa55e96afab33a" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Sun Apr 12 17:27:53 2020 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:34 2022 +0100" }, "message": "const\u0027ify flashctx to align signatures with cros flashrom\n\nThe ChromiumOS flashrom fork has since const\u0027ify flashctx\nin a few places. This aligns the function signatures to\nmatch with downstream to ease forward porting patches\nout of downstream back into mainline flashrom.\n\nThis patch is minimum viable alignment and so feedback is\nwelcome.\n\nChange-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70933\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "93737bcaf5e9c54501eb411b84c3b32e2dff944a", "tree": "8accecfc9ff20ed5dd1fdab7c51ae0ef9e690a9e", "parents": [ "9355e6faf66653655cef5ab312c00e70582fe595" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Oct 29 18:30:01 2019 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Nov 14 22:42:37 2019 +0000" }, "message": "sb600spi.c: Generalise determin_generation() after Yangtze\n\nDrop dead USE_YANGTZE_HEURISTICS code and add Promontory support.\n\nChange-Id: I5aa7370025f5c1af56c6cb96194b6f3007d0ede7\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36426\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "9355e6faf66653655cef5ab312c00e70582fe595", "tree": "f270bcba5757d3efa66f841d697aa25956a3d485", "parents": [ "c0a27e1f1748650726d81f1c00c1ebd440f3ea38" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Oct 29 18:18:18 2019 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Nov 14 22:42:22 2019 +0000" }, "message": "sb600spi.c: Fold up debug logic into determine_generation()\n\nChange-Id: I6c722e29b321285bf20fb5ee30c912dcdd83411b\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36425\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "c0a27e1f1748650726d81f1c00c1ebd440f3ea38", "tree": "7c7b0f7a03e7deb33ce9df99ee9fff1cc9db78fc", "parents": [ "2d20d6db39547f013b66230f378ceb8e21fa36e3" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Oct 29 17:05:39 2019 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Nov 14 22:41:10 2019 +0000" }, "message": "sb600spi.c: Consolidate smbus dev revision derivation\n\nV.2: Rename \u0027find_smbus_dev()\u0027 -\u003e \u0027find_smbus_dev_rev()\u0027.\n\nChange-Id: I766b29cc1c7d01aa0bcf6cb9ff5ab73fa1995dcd\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36420\nReviewed-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "519be66fc59558971dd653afe69ccaf1a633b492", "tree": "74f0912de156a86d56111f377db080246e5205e9", "parents": [ "ef78de4a21323b8c459337356289218211f2c5ce" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 23 20:03:35 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jul 31 08:26:59 2019 +0000" }, "message": "Fix -Wsign-compare trouble\n\nMostly by changing to `unsigned` types where applicable, sometimes\n`signed` types, and casting as a last resort.\n\nChange-Id: I08895543ffb7a48058bcf91ef6500ca113f2d305\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30409\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\n" }, { "commit": "deeac7e41a311a0806af0e65a2ce5c6673f9cf92", "tree": "2ff1082bf9ed049c2863deff9a6d66b6980b1812", "parents": [ "959aafa53eeae4f22766b9d098e5ca952af8c070" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Apr 22 00:09:42 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 27 10:25:15 2019 +0000" }, "message": "spi: Drop spi_controller type\n\nNot needed anymore. Drop it fast before it encourages anyone to\nviolate layers again!\n\nChange-Id: I8eda93b429e3ebaef79e22aba76be62987e496f4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33651\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "db7482bb72035fab8386226d1720cde09e0c700e", "tree": "8a2114a45c22a44e01d8494f224b38c35b17cb71", "parents": [ "e2cbb12f2209a0ba16bc87e31d544fd7fc47f0e2" ], "author": { "name": "Richard Hughes", "email": "richard@hughsie.com", "time": "Wed Dec 19 12:04:30 2018 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Feb 11 23:50:12 2019 +0000" }, "message": "Fix several -Wno-implicit-fallthrough warnings\n\nGCC is picky about the comment being where the break should go.\n\nChange-Id: I05db2fb34025fefe2c6ddd1274c8e45b7cc5a4b6\nSigned-off-by: Richard Hughes \u003crichard@hughsie.com\u003e\nReviewed-on: https://review.coreboot.org/c/30406\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "e083880279119677e443fc16b4694f8c81bf2c40", "tree": "03413b996779bc4c86ec41590f3e7bcdd97d0ef5", "parents": [ "124ef38f7afc61ad7c713c22aad7c5c7f79bdb9b" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Mon Apr 02 11:14:02 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 24 20:21:41 2018 +0000" }, "message": "Remove address from GPLv2 headers\n\nChange-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/25381\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "7b629bcde47e18d094e496fb8ae537272ead0998", "tree": "3c44a9d573fb61ca483054a845722e051558aefd", "parents": [ "8681df128708a548e64865bb6fd8f6cd957e061d" ], "author": { "name": "Ricardo Ribalda Delgado", "email": "ricardo.ribalda@gmail.com", "time": "Wed Mar 22 14:08:31 2017 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Sep 17 18:03:42 2017 +0000" }, "message": "sb600spi: Add support for Merlin Falcon Chipset\n\nThis patch has been tested on a board similar to AMD Bettong.\n\n00:14.0 SMBus [0c05]: Advanced Micro Devices, Inc. [AMD] FCH SMBus\nController [1022:790b] (rev 4a)\n00:14.3 ISA bridge [0601]: Advanced Micro Devices, Inc. [AMD] FCH LPC\nBridge [1022:790e] (rev 11)\nroot@qt5022-fglrx:~# ./flashrom -p internal -w kk.rom\n\nflashrom v0.9.9-unknown on Linux 4.10.0-qtec-standard (x86_64)\nflashrom is free software, get the source code at\nhttps://flashrom.org\n\nCalibrating delay loop... OK.\ncoreboot table found at 0x9ffd6000.\nFound chipset \"AMD FP4\".\nEnabling flash write... OK.\nFound Micron/Numonyx/ST flash chip \"N25Q128..1E\" (16384 kB, SPI)\nmapped at physical address 0x00000000ff000000.\nReading old flash chip contents... done.\nErasing and writing flash chip... Erase/write done.\nVerifying flash... VERIFIED.\n\nChange-Id: I66a240ebc8382cc7e5156686045aee1a9d03fe6d\nSigned-off-by: Ricardo Ribalda Delgado \u003cricardo.ribalda@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/21429\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "0be072cbe4d05b1e69d1c02291f3a2a544beb2af", "tree": "3c4270b0bdf66cd15fcc6b2525c0ff9aa4a803ab", "parents": [ "fc3ecc2a812235fce1a4cdc7dc3338507150e8c7" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Mar 13 15:16:30 2016 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Mar 13 15:16:30 2016 +0000" }, "message": "Add a bunch of new/tested stuff and various small changes 25\n\nTested mainboards:\nOK:\n - ASRock Fatal1ty 970 Performance and P4i65G\n Reported by anonymous email message ID:\n 932677687262b1300eaf14260999d9262c31@guerrillamail.com\n The latter actually had a tested board enable already.\n\nFlash chips:\n - Eon EN25Q128 to PREW (+PREW)\n Reported by Adrian Graham\n - GigaDevice GD25VQ41B to PREW (+PREW)\n Reported by David Hendricks\n - Winbond W39V040FB to PREW (+EW)\n Reported by fjed on IRC\n\nMiscellaneous:\n - Change PCI IDs of \"MS-6577 (Xenon)\" board enable.\n The previous IDs contained the on-board display adapter which is\n disabled when a dedicated graphics card is installed.\n - Add a note to the README how to overcome the clang warning if only a\n single programmer is enabled.\n - Fix some typo and manpage problems found by lintian\n - r1920 introduced some explicit calls to pkg-config instead of $(PKG_CONFIG).\n This patch corrects that.\n - Make MS-7094 (K8T Neo2-F V2.0) board enable less contestable.\n Previous PCI IDs were board-specific but ot the other of devices\n that could be disabled by the firmware or that vary among\n hardware revions. There are no good alternatives available.\n However, since we always have a DMI decoder available now, we can\n use non-board-specific devices without taking risks. Thanks to\n Uwe Hermann for reporting and testing.\n - Some other small changes to clean up whitespace and fix some warnings\n from Debian\u0027s lintian.\n\nCorresponding to flashrom svn r1951.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "57cdd6ba66219f568917e58c3dc585c7d725ce45", "tree": "40a2a89636f80290353c09b710e5b71a740e8400", "parents": [ "8e6565449be9dbf74dad3b5078f2bdc7c587cb2c" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat Mar 12 19:49:14 2016 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat Mar 12 19:49:14 2016 +0000" }, "message": "sb600spi: rewrite and fix corner case\n\nSpecifying spispeed\u003dreserved as programmer parameter resulted in\nselecting the default SPI speed instead of aborting. Rewrite the logic\nto be more readable.\n\nCorresponding to flashrom svn r1949.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "5c316f954941241ed75a1f00f00bf1bff318488a", "tree": "ce836bcb29d7d9da86ee583a88236b020985ba36", "parents": [ "dc627931848ed6af40be4f7d5bdb8e33d28b8333" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Feb 08 21:57:52 2015 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Feb 08 21:57:52 2015 +0000" }, "message": "Add a bunch of new/tested stuff and various small changes 22\n\nTested mainboards:\nOK:\n - AOpen UK79G-1394 (used in EZ18 barebones)\n Reported by Lawrence Gough\n - ASUS M4N78 SE\n Reported by Dima Veselov\n - ASUS P5LD2-VM\n Mark board enable as tested (reported by Dima Veselov)\n - GIGABYTE GA-970A-UD3P (rev. 2.0)\n Reported by trucmar on IRC\n - GIGABYTE GA-990FXA-UD3 (rev. 4.0)\n Reported by ROKO__ on IRC\n - GIGABYTE GA-H77-DS3H (rev. 1.1)\n Reported by Evgeniy Edigarev\n - GIGABYTE GA-P55-USB3 (rev. 2.0)\n Reported by Måns Thörnqvist\n - MSI MS-7817 (H81M-E33)\n Reported by Igor Kolker\n\nChipsets:\n - Marked Intel Bay Trail (0x0f1c) as tested OK\n Reported by Antonio Ospite\n - Refine Intel IDs\n * Add IDs for Braswell\n * Add IDs for 9 Series PCHs (e.g. H97, Z97)\n * Rename Wellsburg devices slightly\n\nFlash chips:\n - Atmel AT25DF041A to PREW (+PREW)\n Reported by Tai-hwa Liang\n - Atmel AT26DF161 to PREW (+EW)\n Reported by Steve Shenton\n - Atmel AT45DB011D to PREW (+PREW)\n Reported by The Raven\n - Atmel AT45DB642D to PREW (+PREW)\n Reported by Mahesh Mokal\n - Eon EN25F32 to PREW (+PREW)\n Reported by Arman Khodabande\n - Eon EN25F40 to PREW (+REW)\n Reported by Jerrad Pierce\n - Eon EN25QH16 to PREW (+EW)\n Reported by Ben Johnson\n - GigaDevice GD25Q20(B) to PREW (+PREW)\n Reported by Gilles Aurejac\n - Macronix MX25U6435E/F to PR (+PR)\n Reported by Matt Taggart\n - PMC Pm25LV512(A) to PREW (+PREW)\n Reported by The Raven\n - SST SST39VF020 to PREW (+PREW)\n Reported by Urja Rannikko\n - Winbond W25Q40.V to PREW (+EW)\n Reported by Torben Nielsen\n - Add E variants of MX25Lx006 (MX25L2006E, MX25L4006E, MX25L8006E).\n - Add MX25L6465E variant.\n - There was never a MX25L12805 AFAICT.\n - Split MX25L12805 from models with the same ID but an additional 32 kB\n eraser: MX25L12835F/MX25L12845E/MX25L12865E.\n - Add a bunch of ST parallel NOR flash chip IDs.\n\nMiscellaneous:\n - Whitelist ThinkPad X200.\n - Constify master parameter of register_master().\n - Remove FEATURE_BYTEWRITES because it was never used at all.\n - Refine hwseq messages and make them less prominent.\n - Fix the yet unused PRIxCHIPADDR format string thingy.\n - Fix copy\u0026paste error in spi_prettyprint_status_register_bp().\n Spotted by Pablo Cases.\n - Add an additional SMBus controller revision to identify another Yangtze\n model. Thanks to Dan Christensen for reporting this issue.\n - dediprog: add missing include for stdlib.h.\n This fixes (at least) building on FreeBSD and DragonflyBSD with gcc.\n - Remove references to struct pci_filter from programmer.h.\n It is only needed in internal.c where it has a complete type. Having\n it in programmer.h provokes a warning by some old versions of gcc.\n - Tiny other stuff.\n\nCorresponding to flashrom svn r1879.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "6697f71ade7b6428c7be6051c02dbb9768900e04", "tree": "23a2f8596d493396b7d9571ee91888e3f49c49f9", "parents": [ "88b19257cb41c97123d832460c944abc588a8e89" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Aug 06 15:09:15 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Aug 06 15:09:15 2014 +0000" }, "message": "Add a bunch of new/tested stuff and various small changes 21\n\nTested mainboards:\nOK:\n - ASUS F2A85-M\n Reported by various corebooters\n - ASUS M2N-MX SE Plus\n Reported by Antonio\n - ASUS P5LD2\n Reported by François Revol\n - Lenovo ThinkPad T530\n Reported and partially authored by Edward O\u0027Callaghan\n - MSI MS-7502 (Medion MD8833)\n Reported by naq on IRC\n - Shuttle AB61\n Reported by olofolleola4\n - ZOTAC IONITX-F-E\n Reported by Bernardo Kuri\n\nFlash chips:\n - Atmel AT45DB021D to PREW (+PREW)\n Reported by The Raven\n - Atmel AT25F4096 to PREW (+PREW)\n Reported by 공준혁\n - GigaDevice GD25Q16(B) to PREW (+PREW)\n Reported by luxflow@live.com using a GD25Q16BSIG\n - Catalyst CAT28F512\n Mark erase and write as known bad (not implemented)\n\nMiscellaneous:\n - Various spelling corrections by Daniele Forsi.\n - Added and refined a bunch of chips originally investigated by Carl-Daniel.\n - Marked the ARM-USB-OCD-H programmer as tested\n (reported by Ruud Schramp).\n - Tiny other stuff.\n\nCorresponding to flashrom svn r1839.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "a5bcbceb581f27cfc0055369d3dd9cfd1ae00bfa", "tree": "5daecd880a16b7011be28e064fb7550f3e6b7e58", "parents": [ "82b6ec1df30d3fca55547f230c76718d6e613b2a" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat Jul 19 22:03:29 2014 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat Jul 19 22:03:29 2014 +0000" }, "message": "Rename programmer registration functions\n\nRegister_programmer suggests that we register a programmer. However,\nthat function registers a master for a given bus type, and a programmer\nmay support multiple masters (e.g. SPI, FWH). Rename a few other\nfunctions to be more consistent.\n\nCorresponding to flashrom svn r1831.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "82b6ec1df30d3fca55547f230c76718d6e613b2a", "tree": "bf2c2e3b17f8673d2857b0d7021fc34d0c124bef", "parents": [ "0e0a0dc05d8647ec5800ec439b7a8cb0586caa50" ], "author": { "name": "Martin Roth", "email": "martin.roth@se-eng.com", "time": "Tue Jul 15 13:50:58 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Jul 15 13:50:58 2014 +0000" }, "message": "Add support for AMD Bolton chipset\n\nSPI controller on the bolton chipset uses the same 3-bit speed\nsettings as Yangtze, but is otherwise the same as the Hudson chips.\nNote that the Bolton RRG doesn\u0027t specify a speed setting for the bit\nsetting of 0b111, so I\u0027m assuming that it\u0027s the same setting as\nYangtze.\n\nCorresponding to flashrom svn r1830.\n\nSigned-off-by: Martin Roth \u003cmartin.roth@se-eng.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "21071b00e35e0e20861c8b9337675c19c8459983", "tree": "9dd1c7b6bf85ac1d675cd7f6e41876503bb5495d", "parents": [ "31402ee6872ce2880f7fe98dc933e5bc73e8613c" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri May 16 21:39:48 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri May 16 21:39:48 2014 +0000" }, "message": "sbxxx: Add spispeed parameter\n\nAllow to set the SPI clock frequency on AMD chipsets with a programmer\nparameter. If the parameter is given (and matches a possible value), the\nSPI clock is set temporarily. Both registers are restored on programmer\nshutdown.\n\nExample: ./flashrom -p internal:spispeed\u003d\"33 MHz\" -V\n\nPossible values for spispeed are \"16.5 MHz\", \"22 MHz\", \"33 MHz\", \"66 MHz\",\n\"100 MHZ\" and \"800 kHz\" depending on the chipset generation.\n\nCorresponding to flashrom svn r1795.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "31402ee6872ce2880f7fe98dc933e5bc73e8613c", "tree": "e86b4bb62924ef524900d377dd3cc908a53a992e", "parents": [ "d5b2aef69d4f4ab5e2ea69e3244e8e8e9a5221b9" ], "author": { "name": "Wei Hu", "email": "wei@aristanetworks.com", "time": "Fri May 16 21:39:33 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri May 16 21:39:33 2014 +0000" }, "message": "sbxxx: Add support for new AMD SPI controller\n\nThis patch adds support for the \"SPI 100\" SPI engine in Yangtze FCHs\n(found in Kabini and Temash).\n\nTested reading/writing on ASRock IMB-A180 and PC Engines\u0027 APU board.\n\nCorresponding to flashrom svn r1794.\n\nSigned-off-by: Wei Hu \u003cwei@aristanetworks.com\u003e\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "d5b2aef69d4f4ab5e2ea69e3244e8e8e9a5221b9", "tree": "51f4f61e1d20bb1b056bffa2196a21cda71faddd", "parents": [ "7141b986497504727d2510c2d5cd98cb059056ce" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri May 16 21:39:28 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri May 16 21:39:28 2014 +0000" }, "message": "sbxxx: Cleanup\n\n - Move programmer definition to the top.\n - Rewrite array accesses to use indices instead of using pointer arithmetic.\n - Move length check and opcode extraction to a function.\n - Move IMC parameter handling into existing IMC handling function.\n - Split comparing and resetting the FIFO pointer.\n\nCorresponding to flashrom svn r1793.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "a6a0d2000a1197e90faaf8d9e7697c96f1deb934", "tree": "edbcfbcc9921b732f9c69f2d72e20e184ec2b4b4", "parents": [ "949ccc8a7ed2a7ad075103e064ad92483ffa8720" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Sep 15 14:17:39 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Sep 15 14:17:39 2013 +0000" }, "message": "sbxxx: Set SPI clock to 16.5 MHz and disable fast reads\n\nDo not rely on broken firmware to set up the SPI configuration correctly.\nSome boards fail with flashrom because the firmware chose too high speeds\nfor the alternate SPI mode which flashrom uses. Temporarily change the\nclock to the lowest common value of 16.5 MHz.\n\nAlso, disable fast reads just to be safe.\n\nCorresponding to flashrom svn r1750.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "5d3072030ac6ad017a25ff0fa4bc451fa8b65ed8", "tree": "1d4a18ad60037ced5824c9f509dd77997f56054a", "parents": [ "2d8b7ef4a84e4946619fa8e4d1b9fcaa15208440" ], "author": { "name": "Niklas Söderlund", "email": "niso@kth.se", "time": "Sat Sep 14 09:02:27 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Sep 14 09:02:27 2013 +0000" }, "message": "Remove exit call and mayfail parameter from physmap_common()\n\nThe only call path where exit was reached was from physmap functions.\n\nCallers of physmap() et al. which were not prepared to handle\nERROR_PTR return values have been adjusted.\nphysmap_try_ro() has been renamed to physmap_ro() and physmap_common()\nslightly refactored due to the now removed *FAIL parameters.\n\nCorresponding to flashrom svn r1745.\n\nSigned-off-by: Niklas Söderlund \u003cniso@kth.se\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "4442b81fd8ba9236813a22bec77f5920033a7df5", "tree": "52ff0a406da8e94b6045e7a2403967ef24f8b290", "parents": [ "d6c17f6528fd3d3a30f6cf63885c269423777796" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Sep 12 15:48:35 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Sep 12 15:48:35 2013 +0000" }, "message": "sbxxx: Add detection for the remaining AMD chipset families\n\nAlso, correct prettyprinting of the registers of the various families,\nand abort if SpiAccessMacRomEn or SpiHostAccessRomEn prohibit full access.\n\nTested reading/writing on ASRock IMB-A180, and chipset detection on\none of each affected generation by Chris Goodrich from Sage.\n\nCorresponding to flashrom svn r1741.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "7fb5aa049bee3c685835dc24c8184c5897e4a6bd", "tree": "3d193e98d25da24307824ab8d0939f3538ec2e50", "parents": [ "36e9f4b3595c6e8b13f80f85785a91b65ecad62f" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Aug 14 15:48:44 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Aug 14 15:48:44 2013 +0000" }, "message": "Automatically unmap physmap()s\n\nSimilarly to the previous PCI self-clean up patch this one allows to get rid\nof a huge number of programmer shutdown functions and makes introducing\nbugs harder. It adds a new function rphysmap() that takes care of unmapping\nat shutdown. Callers are changed where it makes sense.\n\nCorresponding to flashrom svn r1714.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "463dd6953eed14930ae9819c7194ea1cc3b8ef40", "tree": "9e50a76624538bb25a390e08f7d179b7b1bba998", "parents": [ "d2a7e873f3c4125ce1f40d2a5330105c571658d0" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Aug 08 12:00:19 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Aug 08 12:00:19 2013 +0000" }, "message": "Detect AMD Yangtze (found in Kabini and Tamesh)\n\nThe PCI ID of the LPC bridge doesn\u0027t change between Hudson-2/3/4 and\nYangtze (Kabini/Temash) but the SPI interface does. Bail out in case we\ndetect Yangtze and add infrastructure to distinguish other families too for\nfurther refactorings.\n\nAlso, add ASRock IMB-A180 to the laptop whitelist and refine the IMC\nwarning a bit.\n\nTested on ASRock IMB-A180 with and w/o USE_YANGTZE_HEURISTICS, and\nby Chris Goodrich from Sage on\n - SB600\n - SB700\n - SB800\n - Hudson 3 (A70M)\n - Kabini\n\nCorresponding to flashrom svn r1706.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "70e145989bb9d5214a2c50b79b23c457d12f04a5", "tree": "26b1a82d5a33ea45f5fe0d02cdab4b5f5ab36e7a", "parents": [ "1aa80b0648337cf3dcc50932fb237ee69fd82f82" ], "author": { "name": "Rudolf Marek", "email": "r.marek@assembler.cz", "time": "Thu Jul 25 22:58:56 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Jul 25 22:58:56 2013 +0000" }, "message": "sbxxx: Handle active IMCs in AMD chipsets\n\nDetect and temporarily disable the IMC while accessing the flash.\nDisable writes on default, but allow the user to enforce it.\n\nCorresponding to flashrom svn r1704.\n\nSigned-off-by: Rudolf Marek \u003cr.marek@assembler.cz\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: David Hendricks \u003cdhendrix@google.com\u003e\n" }, { "commit": "0466c819e248881e03a6ec98db5297565816859b", "tree": "ef4b7b69bdbe80c9a3177341811dce516e7bbd74", "parents": [ "b13d4e699249838babfc37a1d77b8ee27f6d72d9" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Jun 16 10:30:08 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Jun 16 10:30:08 2013 +0000" }, "message": "sbxxx: spibar[0] debug print refinements\n\nNewer models support a 66 MHz clock and fast reads.\nWe should probably distinguish the models better (as we do in ichspi)\nand add support for frequency selection etc. For now this has to\nsuffice.\n\nCorresponding to flashrom svn r1678.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "32508eb304428551cff40b291d44823aafec7574", "tree": "0641d77a791290f6842fd60446e87871f6867651", "parents": [ "3834c2d7e5a08e09e580be0dc7f9369c941b2a70" ], "author": { "name": "Patrick Georgi", "email": "patrick.georgi@secunet.com", "time": "Fri Jul 20 20:35:14 2012 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Fri Jul 20 20:35:14 2012 +0000" }, "message": "Hide hwaccess.h from public API\n\nMove hwaccess.h #include from flash.h to individual drivers.\nlibflashrom users need flash.h, but they do not care about hwaccess.h\nand should not see its definitions because they may conflict with\nother hardware access functions and #defines used by the libflashrom\nuser.\n\nCorresponding to flashrom svn r1549.\n\nSigned-off-by: Patrick Georgi \u003cpatrick.georgi@secunet.com\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "7bca126561b80f626dea269d7a6284a7cde0a8ed", "tree": "45c6b31e39846a88d89d157d758134d7b8dc1db1", "parents": [ "3464d05eb41ab4c7a6faba9a1a36bfbeda0de850" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Jun 15 22:28:12 2012 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Fri Jun 15 22:28:12 2012 +0000" }, "message": "Let the programmer driver decide how to do AAI transfers\n\nCurrently spi_aai_write() is implemented without an abstraction\nmechanism for the programmer driver. This adds another function\npointer \u0027write_aai\u0027 to struct spi_programmer, which is set to\ndefault_spi_write_aai (renamed spi_aai_write) for all programmers\nfor now.\n\nA patch which utilises this abstraction in the dediprog driver will\nfollow.\n\nCorresponding to flashrom svn r1543.\n\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "8a3c60cdd0e5632173567923ae1927763e31e857", "tree": "3a5514d022392cf4d8fa368f9f02653da21a93ca", "parents": [ "63fd9026f1e82b67a65072fda862ba7af35839e1" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Dec 18 15:01:24 2011 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Dec 18 15:01:24 2011 +0000" }, "message": "Add struct flashctx * parameter to all functions accessing flash chips\n\nAll programmer access function prototypes except init have been made\nstatic and moved to the respective file.\n\nA few internal functions in flash chip drivers had chipaddr parameters\nwhich are no longer needed.\n\nThe lines touched by flashctx changes have been adjusted to 80 columns\nexcept in header files.\n\nCorresponding to flashrom svn r1474.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\n" }, { "commit": "6e9e2ee2f4411de03bcbf7c2e8cb14c08fec90e4", "tree": "0f2036a03849d5b3e4824e4a4391f7cc45892f7c", "parents": [ "09ebd52e01af15466ef08ce240f6c760e27af79c" ], "author": { "name": "Wang Qing Pei", "email": "wangqingpei@gmail.com", "time": "Fri Aug 26 21:11:41 2011 +0000" }, "committer": { "name": "Uwe Hermann", "email": "uwe@hermann-uwe.de", "time": "Fri Aug 26 21:11:41 2011 +0000" }, "message": "Add AMD Hudson chipset-enable\n\nAMD Hudson has different vendor/device IDs than AMD SBx00, handle\nthat properly.\n\nCorresponding to flashrom svn r1422.\n\nSigned-off-by: Wang Qing Pei \u003cwangqingpei@gmail.com\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n" }, { "commit": "a63c7c449646147efe2bdeb80efeed479dc1d328", "tree": "da1a452c658ecb3120fffe6d084a46a85d5792a4", "parents": [ "082c8b559cd9f3262c9af58ac2f17f2cc8a09d8b" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Aug 16 12:08:22 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Aug 16 12:08:22 2011 +0000" }, "message": "Remove unneeded inclusions of chipdrivers.h\n\nThis is related to the spi split patch as discussed in:\nhttp://www.flashrom.org/pipermail/flashrom/2010-February/thread.html#2364\nthe old commit (r914) log notes:\n\"Some of the spi programmer drivers required chipdrivers.h, needs fixing later: it87spi.c\n ichspi.c sb600spi.c wbsio_spi.c buspirate_spi.c ft2232spi.c bitbang_spi.c dediprog.c\"\n\nthere still remain a few cases where chipdrivers.h is needed:\ndediprog.c (spi_read_chunked and spi_write_chunked)\nit87spi.c (due to spi_write_enable and spi_read_status_register)\nwbsio_spi.c (spi_programmer registration only)\n\nbesides that, there are also non-spi files that do not need it.\nalso, add flash.h to chipdrivers.h because it uses some types of it\nand remove flashchips.h from print.c\n\nCorresponding to flashrom svn r1414.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "b9dbe48b77384e2faf0619161fc5c55afe388ea9", "tree": "8b556f82073e824bc1e9a4cc9547d67b1d902cee", "parents": [ "627975196d0630a137548df631756e656a8139af" ], "author": { "name": "Michael Karcher", "email": "flashrom@mkarcher.dialup.fu-berlin.de", "time": "Wed May 11 17:07:07 2011 +0000" }, "committer": { "name": "Michael Karcher", "email": "flashrom@mkarcher.dialup.fu-berlin.de", "time": "Wed May 11 17:07:07 2011 +0000" }, "message": "Kill central list of SPI programmers\n\nRemove the array spi_programmer, replace it by dynamic registration\ninstead. Also initially start with no busses supported, and switch to\nthe default non-SPI only for the internal programmer.\n\nAlso this patch changes the initialization for the buses_supported variable\nfrom \"everything-except-SPI\" to \"nothing\". All programmers have to set the\nbus type on their own, and this enables register_spi_programmer to just add\nthe SPI both for on-board SPI interfaces (where the internal programmer\nalready detected the other bus types), as well as for external programmers\n(where we have the default \"none\").\n\nCorresponding to flashrom svn r1299.\n\nSigned-off-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "627975196d0630a137548df631756e656a8139af", "tree": "9a01302678ba2ba642040e928b89c8877c080412", "parents": [ "b713d2e35c5336da81f5fbc83393961d1d8aa7bd" ], "author": { "name": "Michael Karcher", "email": "flashrom@mkarcher.dialup.fu-berlin.de", "time": "Wed May 11 17:07:02 2011 +0000" }, "committer": { "name": "Michael Karcher", "email": "flashrom@mkarcher.dialup.fu-berlin.de", "time": "Wed May 11 17:07:02 2011 +0000" }, "message": "Factor out SPI write/read chunking wrappers\n\nCorresponding to flashrom svn r1298.\n\nSigned-off-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "a60faab83ef86bcf2884311db07cf13f445d7f47", "tree": "9de9787987eb6a3374e18835b196b7ac6cb9ad19", "parents": [ "2c3afa34fcfc72abe6b3e0fd034632226fa75522" ], "author": { "name": "Mathias Krause", "email": "mathias.krause@secunet.com", "time": "Mon Jan 17 07:50:42 2011 +0000" }, "committer": { "name": "Mathias Krause", "email": "mathias.krause@secunet.com", "time": "Mon Jan 17 07:50:42 2011 +0000" }, "message": "Convince compilers to put constant data into the .rodata section\n\nThis patch reduces the stack usage by declaring \u0027const\u0027 stack variables\nas \u0027static const\u0027 so they end up in the .rodata section instead of being\ncopied from there to the stack for every invocation of the corresponding\nfunction.\n\nAs a plus we end up in having a smaller binary as the \"copy from .rodata\nto stack\" code isn\u0027t emitted by the compiler any more (roughly -100\nbytes).\n\nCorresponding to flashrom svn r1252.\n\nSigned-off-by: Mathias Krause \u003cmathias.krause@secunet.com\u003e\nAcked-by: Stefan Reinauer \u003cstepan@coreboot.org\u003e\n" }, { "commit": "39446e34c8d14f6a9798dae17ee0152263a31744", "tree": "91cb5ba77510f0118668b48c617fcbb2a4278914", "parents": [ "9ad4255b5e206899351b446dec96b84c989627b6" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Sep 15 12:02:07 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Sep 15 12:02:07 2010 +0000" }, "message": "Detect embedded EC (IMC) in AMD\u0027s SBs\n\nAMD SB700 and later have an integrated microcontroller (IMC) which runs\nfrom shared flash.\n\nThe IMC will happily issue reads while we write, issue writes while we\nread, and generally cause lots of havoc due to the concurrent accesses\nit performs while flashrom is running. A failing or corrupted read can\nbe detected since r1145, and the worst case is that the read aborts and\nthe user has to retry. A failing write is much more serious. It can\nbe detected since r1145, but if the SPI interface locks up, we can\u0027t\ncontinue writing nor can we read the current chip contents.\n\nIf the IMC is inactive, there is no reason to worry. If the IMC is\nactive, flashrom will refuse to erase/write the chip with this patch.\n\nThe correct fix would be to stop the IMC during flashing, but apparently\nthe relevant registers are undocumented, so we take the safe route for\nnow until someone from AMD can give us more info.\n\nCorresponding to flashrom svn r1173.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nTested-by: Matthias Kretz \u003ckretz@kde.org\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n" }, { "commit": "eb0e7fc4f08dcc704565ae07c83878171cc71a44", "tree": "e9eb1f6a1701f8bbe8fdabf6bcfad87870e2547a", "parents": [ "a84b0bd6ad4b5ab7220deb799f30515a9eb0d7fc" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Aug 18 15:12:43 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Aug 18 15:12:43 2010 +0000" }, "message": "Add paranoid checks to sb600spi driver\n\nAdd paranoid checks for correct values in essential registers in the SB600/SB700/... SPI driver. If something else changes the values we\nwrote, we will see severe read/write corruption.\nsb600spi will now abort the access and return an error if it detects\nthis sort of corruption.\n\nNote: This corruption can be caused by a few different events:\n- IPMI/BMC/IMC accesses flash\n- Other software accesses flash\nThe nature of flash access (read/write/ID/...) is irrelevant. Each such\naccess will cause corruption for all other accesses happening at the\nsame time.\n\nThanks to Matthias Kretz for testing this patch.\n\nCorresponding to flashrom svn r1145.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Matthias Kretz \u003ckretz@kde.org\u003e\n" }, { "commit": "5b997c3ed66ddbbb9470f27d4e27ab4c263bc9cf", "tree": "adbaace5de6bb0d97a58143c7e3ae775a15d47ff", "parents": [ "1d3a2fefbc636fb569bd1d018fb97b1b17c08e99" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Tue Jul 27 22:41:39 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Tue Jul 27 22:41:39 2010 +0000" }, "message": "Split off programmer.h from flash.h\n\nProgrammer specific functions are of absolutely no interest to any file\nexcept those dealing with programmer specific actions (special SPI\ncommands and the generic core).\n\nThe new header structure is as follows (and yes, improvements are\npossible):\nflashchips.h flash chip IDs\nchipdrivers.h chip-specific read/write/... functions\nflash.h common header for all stuff that doesn\u0027t fit elsewhere\nhwaccess.h hardware access functions\nprogrammer.h programmer specific functions\ncoreboot_tables.h header from coreboot, internal programmer only\nspi.h SPI command definitions\n\nCorresponding to flashrom svn r1112.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n" }, { "commit": "b05b9e100a9dd1c1c66963e59bffe4b9ea32f8e4", "tree": "81bb78014e4827c1ca38da012d2dfd43099cacc9", "parents": [ "a4448d9aec2c2f6122f3a2141d8ed81032fbb2e6" ], "author": { "name": "Michael Karcher", "email": "flashrom@mkarcher.dialup.fu-berlin.de", "time": "Thu Jul 22 18:04:19 2010 +0000" }, "committer": { "name": "Michael Karcher", "email": "flashrom@mkarcher.dialup.fu-berlin.de", "time": "Thu Jul 22 18:04:19 2010 +0000" }, "message": "Move SB600 SPI initialization to sb600spi.c\n\nCorresponding to flashrom svn r1099.\n\nSigned-off-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "29a1c66a23bc8685f456d548361b735bf36dcf2b", "tree": "963d487fa71ce4b6ad998d89fde9e167ce11e6bb", "parents": [ "ca812d40d461e70a70df6079978e96642775e7b2" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Jul 14 20:21:22 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Jul 14 20:21:22 2010 +0000" }, "message": "Use generic unlocking infrastructure for SPI chips\n\nActually check if the unlock worked instead of just assuming it worked.\n\nCorresponding to flashrom svn r1082.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\n" }, { "commit": "9a795d83fbb8842a271d5e037dc983a57b0419fd", "tree": "a9049f708d0ab7d42d122fecd23855aaa819c5bc", "parents": [ "1748c5701f77ab7164ab3311f37abc356d825ccb" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Jul 14 16:19:05 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Jul 14 16:19:05 2010 +0000" }, "message": "Convert SPI chips to partial write\n\nHowever, wrap the write functions in a compat layer to allow converting\nthe rest of flashrom later. Tested on Intel NM10 by David Hendricks.\n\nCorresponding to flashrom svn r1080.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\n" }, { "commit": "831e8f4abb29f1ff66ebb8ab5ff496050ff677f7", "tree": "8d19ef4871587dcaf0a3a1dec562dd6ef09024b6", "parents": [ "4178760241c3b3dc46a806ee3621a2eb97f4cca5" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun May 30 22:24:40 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun May 30 22:24:40 2010 +0000" }, "message": "Remove unneeded #include statements completely\n\nUnistd.h was only used to get a definition of NULL in all files. Add our\nown NULL #define and remove unistd.h from flash.h\nstdio.h has no place in flash.h, it should be included only in files\nwhich really need it.\nAdd #include statements in individual .c files where needed.\n\nReplace a few printf with msg_* to eliminate the need for stdio.h.\n\nCorresponding to flashrom svn r1021.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n" }, { "commit": "cceafa2ad073fe58b10b6f2317cbd36a63d7ccb5", "tree": "f07a19288da12246cf3da5d886be39915cfc59a5", "parents": [ "8d341b5ae774bdf8249c68944a77b72b7c4be640" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed May 26 01:45:41 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed May 26 01:45:41 2010 +0000" }, "message": "Handle the following architectures in generic flashrom code\n\n- x86/x86_64 (little endian)\n- PowerPC (big endian)\n- MIPS (big+little endian)\n\nNo changes to programmer specific code. This means any drivers with MMIO\naccess will _not_ suddenly start working on big endian systems, but with\nthis patch everything is in place to fix them.\n\nCompilation should work on all architectures listed above for all\ndrivers except nic3com and nicrealtek which require PCI Port IO which is\nx86-only for now.\n\nTo compile without nic3com and nicrealtek, run\nmake distclean\nmake CONFIG_NIC3COM\u003dno CONFIG_NICREALTEK\u003dno\n\nThanks to Misha Manulis for testing early versions of this patch on\nPowerPC (big endian) with the satasii programmer.\nThanks to Segher Boessenkool for design review and for helping out with\ncompiler tricks and pointing out that we need eieio on PowerPC.\nThanks to Vladimir Serbinenko for compile testing on MIPS (little\nendian) and PowerPC (big endian) and for runtime testing on MIPS (little\nendian).\nThanks to David Daney for compile testing on MIPS (big endian).\nThanks to Uwe Hermann for compile and runtime testing on x86_64.\n\nDO NOT RUN flashrom ON NON-X86 AFTER APPLYING THIS PATCH!\nThis patch only provides the infrastructure, but does not convert any\ndrivers, so flashrom will compile, but it won\u0027t do the right thing on\nnon-x86 platforms.\n\nCorresponding to flashrom svn r1013.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Misha Manulis \u003cmisha@manulis.com\u003e\nAcked-by: Vladimir \u0027phcoder/φ-coder\u0027 Serbinenko \u003cphcoder@gmail.com\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\nAcked-by: Segher Boessenkool \u003csegher@kernel.crashing.org\u003e\n" }, { "commit": "5824fbff010076cc0d2a4387c1b2f54644ae5785", "tree": "73c903182e7400386453acfbd7c738b3361849ff", "parents": [ "d175e06ac305274d8e1a8a4658f7f5518c89b801" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Fri May 21 23:09:42 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Fri May 21 23:09:42 2010 +0000" }, "message": "Introduce a generic SPI read function: spi_write_chunked()\n\nEvery SPI programmer driver had its own completely different chip write\nimplementation, and all of them were insufficiently commented. Create\nspi_write_chunked as a copy of spi_read_chunked and convert all SPI\nprogrammers to use it. No functional changes except: - Bus Pirate uses\n12 Byte writes instead of 8 Byte writes - SB600 uses 5 Byte writes\ninstead of 1 Byte writes\n\nCorresponding to flashrom svn r1005.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\nAcked-by: David Hendricks \u003cdhendrix@google.com\u003e\n" }, { "commit": "14ba6682e99273273be74b8e8681d0604b85e9b9", "tree": "cd0212ae1ffe83aaea0a5ca9f5e2be86615c471a", "parents": [ "cfa674fde7ee763844f82e38503cd997a3951197" ], "author": { "name": "Sean Nelson", "email": "audiohacked@gmail.com", "time": "Fri Feb 26 05:48:29 2010 +0000" }, "committer": { "name": "Sean Nelson", "email": "audiohacked@gmail.com", "time": "Fri Feb 26 05:48:29 2010 +0000" }, "message": "Split spi.c into programmer and chip code Remove chipdriver.h include from flash.h\n\nSome of the spi programmer drivers required chipdrivers.h, needs fixing later:\n it87spi.c\n ichspi.c\n sb600spi.c\n wbsio_spi.c\n buspirate_spi.c\n ft2232spi.c\n bitbang_spi.c\n dediprog.c\n\nCorresponding to flashrom svn r914.\n\nSigned-off-by: Sean Nelson \u003caudiohacked@gmail.com\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "643415bfdb160a1277ac490b85c7473ab2473495", "tree": "9fc7b96244f1af373dddbd7055d91cdcac6fd4f2", "parents": [ "08fa2f39f3861463c15e293213e2b16fb694c1ca" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Jan 10 01:59:50 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Jan 10 01:59:50 2010 +0000" }, "message": "Convert all messages in sb600spi.c to the new message infrastructure\n\nCorresponding to flashrom svn r857.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Sean Nelson \u003caudiohacked@gmail.com\u003e\n" }, { "commit": "5609fa752ca1c36d00d915e94d481a9a457c85cf", "tree": "ff145bc4ed987c3c81870ddb6e7ce6a929ca9b47", "parents": [ "a84835a7eadadb715a61d993da6766bdf1b37c5e" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Thu Jan 07 03:32:17 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Thu Jan 07 03:32:17 2010 +0000" }, "message": "Allow one to disable programmer debug messages at compile time\n\nProgrammer debug messages during programmer init/shutdown are useful\nbecause they print hardware settings and desired configuration.\n\nThey help in getting a quick overview of hardware and software state on\nstartup and shutdown.\n\nProgrammer debug messages during flash chip access are mostly a\ndistraction in logs and should only be enabled if someone is having\nproblems which are suspected to stem from a programmer hardware or\nprogrammer software bug. Disable those messages by default, they can be\nreenabled by #define COMM_DEBUG in the affected programmer file.\n\nAn added benefit is a tremendous size reduction in verbose\nprobe/read/write/erase logs because only flash chip driver messages\nremain. In some cases, logs will shrink from 65 MB to 10 kB or less.\n\nThe right(tm) fix would be two different debug levels (DEBUG and SPEW)\nand the ability to differentiate between programmer debug messages and\nflash chip debug messages. Until the design for the message printing\ninfrastructure is finished, this is the best stop-gap measure we can\nget.\n\nCorresponding to flashrom svn r834.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Sean Nelson \u003caudioahcked@gmail.com\u003e\n" }, { "commit": "de75a5ed7f0f1b05e32a97423723db7a0719a2f2", "tree": "e94909e0b3b7bd53dcee2d46ce51d1423d0483f5", "parents": [ "4010712033b988f0be85f790982a12bb4010094b" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Thu Oct 01 13:16:32 2009 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Thu Oct 01 13:16:32 2009 +0000" }, "message": "Introduce proper error checking for SPI programming\n\nCorresponding to flashrom svn r739.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Stefan Reinauer \u003cstepan@coresystems.de\u003e\n" }, { "commit": "ab044b20a2b44097ce65c3fd4f232ee7170303ba", "tree": "4d4e3556312edc4be7fc90d073a2fbb79d86d687", "parents": [ "9e72aa51a7a9ac5f041bacab75fd4be1e2a3356c" ], "author": { "name": "Stefan Reinauer", "email": "stepan@coresystems.de", "time": "Wed Sep 16 08:26:59 2009 +0000" }, "committer": { "name": "Stefan Reinauer", "email": "stefan.reinauer@coreboot.org", "time": "Wed Sep 16 08:26:59 2009 +0000" }, "message": "Fix all remaining issues reported by LLVM/clang\u0027s scan-build\n\nCorresponding to flashrom svn r723.\n\nSigned-off-by: Stefan Reinauer \u003cstepan@coresystems.de\u003e\nAcked-by: Ronald G. Minnich \u003crminnich@gmail.com\u003e\n" }, { "commit": "f38431a5b23e578cff1299b8d69e7d650c060b60", "tree": "293fe367a94034d5b17d622c33e0365ec1a9b871", "parents": [ "c04ee22c7006d6e006086c40651b8761cea0fbfc" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat Sep 05 02:30:58 2009 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat Sep 05 02:30:58 2009 +0000" }, "message": "Store block sizes and corresponding erase functions in struct flashchip\n\nI decided to fill in the info for a\nfew chips to illustrate how this works both for uniform and non-uniform\nsector sizes.\n\nstruct eraseblock{\nint size; /* Eraseblock size */\nint count; /* Number of contiguous blocks with that size */\n};\n\nstruct eraseblock doesn\u0027t correspond with a single erase block, but with\na group of contiguous erase blocks having the same size.\nGiven a (top boot block) flash chip with the following weird, but\nreal-life structure:\n\ntop\n16384\n8192\n8192\n32768\n65536\n65536\n65536\n65536\n65536\n65536\n65536\nbottom\n\nwe get the following encoding:\n{65536,7},{32768,1},{8192,2},{16384,1}\n\nAlthough the number of blocks is bigger than 4, the number of block\ngroups is only 4. If you ever add some flash chips with more than 4\ncontiguous block groups, the definition will not fit into the 4-member\narray anymore and gcc will recognize that and error out. No undetected\noverflow possible. In that case, you simply increase array size a bit.\nFor modern flash chips with uniform erase block size, you only need one\narray member anyway.\n\nOf course data types will need to be changed if you ever get flash chips\nwith more than 2^30 erase blocks, but even with the lowest known erase\ngranularity of 256 bytes, these flash chips will have to have a size of\na quarter Terabyte. I\u0027m pretty confident we won\u0027t see such big EEPROMs\nin the near future (or at least not attached in a way that makes\nflashrom usable). For SPI chips, we even have a guaranteed safety factor\nof 4096 over the maximum SPI chip size (which is 2^24). And if such a\nbig flash chip has uniform erase block size, you could even split it\namong the 4 array members. If you change int count to unsigned int\ncount, the storable size doubles. So with a split and a slight change of\ndata type, the maximum ROM chip size is 2 Terabytes.\n\nSince many chips have multiple block erase functions where the\neraseblock layout depends on the block erase function, this patch\ncouples the block erase functions with their eraseblock layouts.\nstruct block_eraser {\n struct eraseblock{\n unsigned int size; /* Eraseblock size */\n unsigned int count; /* Number of contiguous blocks with that size */\n } eraseblocks[NUM_ERASEREGIONS];\n int (*block_erase) (struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen);\n} block_erasers[NUM_ERASEFUNCTIONS];\n\nCorresponding to flashrom svn r719.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Stefan Reinauer \u003cstepan@coresystems.de\u003e\n" }, { "commit": "116081a224c3b36a4a7d940cfdb1dac1ba35fc75", "tree": "e82fbd5e39ffa638a9f56d93e90f0f520d392a53", "parents": [ "db41c59e3ba625659e397675384b08b4ec967fe6" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Mon Aug 10 02:29:21 2009 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Mon Aug 10 02:29:21 2009 +0000" }, "message": "Replace remaining explicit erases in SPI programmer drivers with auto-erases\n\nSome SPI chip drivers and the generic 1-byte SPI chip write functions\ndidn\u0027t include the automatic erase present in other chip drivers.\n\nSince the majority is definitely auto-erase, change the remaining\nexplicit-erase cases to be auto-erase as well.\n\nCorresponding to flashrom svn r673.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Carlos Arnau Perez \u003ccemede@gmail.com\u003e\n" }, { "commit": "be726817f770572f4d950c7e572c308112a69e3b", "tree": "f6c67448c4b98b1f49e89826f451f51de027b1e5", "parents": [ "5b2f52fa6caab4bda5aaf8b6128eb3044a930c47" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Aug 09 12:44:08 2009 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Aug 09 12:44:08 2009 +0000" }, "message": "Remove unnecessary #include files\n\nSerprog compilation is now controlled by a Makefile variable.\nReplace munmap with physunmap where appropriate.\n\nCorresponding to flashrom svn r671.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Stefan Reinauer \u003cstepan@coresystems.de\u003e\n" }, { "commit": "f8555e24a456551de9ce3d89fc648db9034ef517", "tree": "b2ed02345452c285f0138e2a2777e1dab46ba617", "parents": [ "414bd320ac1346db9539625975644bfa7b30281e" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Thu Jul 23 01:36:08 2009 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Thu Jul 23 01:36:08 2009 +0000" }, "message": "This is a workaround for a bug in SB600 and SB700\n\nIf we only send an opcode and no additional data/address, the SPI\ncontroller will read one byte too few from the chip. Basically, the\nlast byte of the chip response is discarded and will not end up in the\nFIFO. It is unclear if the CS# line is set high too early as well. That\nhardware bug is undocumented as of now, but I\u0027m working with AMD to add\na detailed description of it to the errata.\n\nAdd loads of additional debugging to SB600/SB700 init.\n\nAdd explanatory comments for unintuitive code flow.\n\nThanks go to Uwe for testing quite a few iterations of the patch.\n\nKill the SB600 flash chip status register special case, which was a\nsomewhat misguided workaround for that hardware erratum.\n\nNote for future added features in the SB600 SPI driver: It may be\npossible to read up to 15 bytes of command response with overlapping\nreads due to the ring buffer design of the FIFO if the command can be\nrepeated without ill effects. Same for skipping up to 7 bytes between\ncommand and response.\n\nCorresponding to flashrom svn r661.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Stefan Reinauer \u003cstepan@coresystems.de\u003e\n" }, { "commit": "142e30fcaa1c3a63a1f0baf0b802ef888a0c250b", "tree": "c286d89dadacecee2e68b84ce5606467e9ae33e8", "parents": [ "78e4e127129398454813d1552b516638837c423e" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Tue Jul 14 10:26:56 2009 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Tue Jul 14 10:26:56 2009 +0000" }, "message": "Use a distinct return code for SPI commands with unsupported/invalid length\n\nSome drivers support only a few combinations of read/write length and\nreturn error otherwise. Having a distinct return code for this error\nmeans we can handle it in upper layers.\n\nCorresponding to flashrom svn r653.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Stefan Reinauer \u003cstepan@coresystems.de\u003e\n" }, { "commit": "2f1b36fb35873c599442e1828756c1993524cd5e", "tree": "836e46a0ba0fcd1ce41a52eddcb3437c2d08e2e5", "parents": [ "39fa9b55cd4c049f43124b873b464641fc9f79a9" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Jul 12 12:06:18 2009 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Jul 12 12:06:18 2009 +0000" }, "message": "Convert SPI byte program to use the multicommand infrastructure\n\nTested-by: Jakob Bornecrantz \u003cwallbraker@gmail.com\u003e\n\nCorresponding to flashrom svn r651.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nTested it on Epia-m700 worked okay.\nAcked-by: Jakob Bornecrantz \u003cwallbraker@gmail.com\u003e\n" }, { "commit": "d0478299b1d714a7001f19fb2cafeb257698a2c0", "tree": "4cd9e2881c6f02f26270149770210e6d1aa742cd", "parents": [ "8ef7dce29aead4f17000e2c14b39f0723adc3953" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Fri Jul 10 21:08:55 2009 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Fri Jul 10 21:08:55 2009 +0000" }, "message": "Add SPI multicommand infrastructure\n\nSome SPI opcodes need to be sent in direct succession after each other\nwithout any chip deselect happening in between. A prominent example is\nWREN (Write Enable) directly before PP (Page Program). Intel calls the\nfirst opcode in such a row \"preopcode\".\n\nRight now, we ignore the direct succession requirement completely and it\nworks pretty well because most onboard SPI masters have a timing or\nheuristics which make the problem disappear.\nThe FT2232 SPI flasher is different. Since it is an external flasher,\ntiming is very different to what we can expect from onboard flashers and\nthis leads to failure at slow speeds.\n\nThis patch allows any function to submit multiple SPI commands in a\nstream to any flasher. Support in the individual flashers isn\u0027t\nimplemented yet, so there is one generic function which passes the each\ncommand in the stream one-by-one to the command functions of the\nselected SPI flash driver.\n\nTested-by: Jakob Bornecrantz \u003cwallbraker@gmail.com\u003e\n\nCorresponding to flashrom svn r645.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Jakob Bornecrantz \u003cwallbraker@gmail.com\u003e\n" }, { "commit": "2c7ba8ce706da91e31d53b3c4fdc43d91ce0a2cf", "tree": "14b71fb60b594042acd47637b7e68f9043c901ff", "parents": [ "452b3e37856b2bb984fabc09706a8ca8a954ef6c" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Tue Jun 23 00:47:26 2009 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Tue Jun 23 00:47:26 2009 +0000" }, "message": "SB600 SPI: Kill unused variable\n\nMake a few local functions in sb600spi.c static.\n\nCorresponding to flashrom svn r623.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Luc Verhaegen \u003clibv@skynet.be\u003e\n" }, { "commit": "cbf563cbde925dae6971c7df305493a638de51c6", "tree": "29b0a806979474c3d8dcbc6acfa7022728ca4a15", "parents": [ "30f7cb2f3c570c99b61bd5df72621f44f1bdd0d0" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Tue Jun 16 08:55:44 2009 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Tue Jun 16 08:55:44 2009 +0000" }, "message": "Support reads of arbitrary range\n\nThat means you can tell flashrom to read exactly bytes 12345-56789\n(start 12345, length 44445) and it will not fetch a single byte more.\n\nUwe tested this on one LPC, one SPI, and one parallel flash board.\n\nCorresponding to flashrom svn r596.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n" }, { "commit": "30f7cb2f3c570c99b61bd5df72621f44f1bdd0d0", "tree": "d714754c298d7d247786e19c4b2b4afd6067a795", "parents": [ "084546449983c1d6f147c1a3e381e225887e322c" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Mon Jun 15 17:23:36 2009 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Mon Jun 15 17:23:36 2009 +0000" }, "message": "Flashrom only checks for very few chips if the erase worked\n\nAnd even when it checks if the erase worked, the result of that check is\noften ignored.\n\nConvert all erase functions and actually check return codes\nalmost everywhere.\nCheck inside all erase_* routines if erase worked, not outside.\nerase_sector_jedec and erase_block_jedec have changed prototypes to\nenable erase checking.\n\nUwe successfully tested LPC on an CK804 box and SPI on some SB600 box.\n\nCorresponding to flashrom svn r595.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nSigned-off-by: Urja Rannikko \u003curjaman@gmail.com\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n" }, { "commit": "38a059d6ef1ebb7145a04825fec0ebef1d8a66a7", "tree": "66c9108eda2f0f7129f2ba55b9cb757414d9466a", "parents": [ "8b2f46b878a952a0ea0869624636cb4d6f5fa8c1" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat Jun 13 12:04:03 2009 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat Jun 13 12:04:03 2009 +0000" }, "message": "Every SPI host controller implemented its own way to read flash chips\n\nThis was partly due to a design problem in the abstraction layer.\n\nThere should be exactly two different functions for reading SPI chips:\n- memory mapped reads\n- SPI command reads.\n\nEach of them should be contained in a separate function, optionally\ntaking parameters where needed.\n\nThis patch solves the problems mentioned above, shortens the code and\nmakes the code logic a lot more obvious.\n\nSince open-coding the min() function leads to errors, include it in this\npatch as well.\n\nCorresponding to flashrom svn r589.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Ronald G. Minnich \u003crminnich@gmail.com\u003e\n" }, { "commit": "1dfe0ff1745118406f2ca0d03340dd346cc39770", "tree": "8b0f6db0abbbd38355b6ddf8feadb7b06a4e9bab", "parents": [ "ebd7b8393906876d4b450d8b83a9b748d43c64b4" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun May 31 17:57:34 2009 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun May 31 17:57:34 2009 +0000" }, "message": "Add bus type annotation to struct flashchips\n\nRight now, the annotation only differentiates between SPI and non-SPI.\nAnyone who knows more about a specific flash chip should feel free to\nupdate it.\n\nThe existing flashbus variable was abused to denote the SPI controller\ntype. Use an aptly named variable for that purpose.\n\nOnce this patch is merged, the chipset/programmer init functions can set\nsupported flash chip types and flashrom can automatically select only\nmatching probe/read/erase/write functions. A side benefit of that will\nbe the elimination of the Winbond W29EE011 vs. AMIC A49LF040A conflict.\n\nCorresponding to flashrom svn r556.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n" }, { "commit": "78185dcb3c58552acb652780c4182a77a74f16f0", "tree": "81c15dc84a3217eb3359b300fea38bca68421ed0", "parents": [ "05fab75d73019f430c16ad9a9d3800f8e7e40173" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun May 17 15:49:24 2009 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun May 17 15:49:24 2009 +0000" }, "message": "Use accessor functions for MMIO\n\nSome MMIO accesses used volatile, others didn\u0027t (and risked\nnon-execution of side effects) and even with volatile, some accesses\nlooked dubious.\n\nSince the MMIO accessor functions and the onboard flash accessor\nfunctions are functionally identical (but have different signatures),\nmake the flash accessors wrappers for the MMIO accessors.\n\nFor some of the conversions, I used Coccinelle. Semantic patch follows:\n\n@@ typedef uint8_t; expression a; volatile uint8_t *b; @@ - b[a] + *(b\n+ a) @@ expression a; volatile uint8_t *b; @@ - *(b) |\u003d (a); + *(b) \u003d\n*(b) | (a); @@ expression a; volatile uint8_t *b; @@ - *(b) \u003d (a); +\nmmio_writeb(a, b); @@ volatile uint8_t *b; @@ - *(b) + mmio_readb(b) @@\ntype T; T b; @@ ( mmio_readb | mmio_writeb ) (..., - (T) - (b) + b )\n\nCorresponding to flashrom svn r524.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n\nUwe tested read, write, erase with this patch on a random board to make\nsure nothing breaks.\n\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n" }, { "commit": "2cac6860c3f451a661d8281d25a72dd5db89f4e4", "tree": "7592a765da81385bff5cfe1aa62f215618be948e", "parents": [ "8403ccb49f98d1583736984c92d62735d9d466b5" ], "author": { "name": "Uwe Hermann", "email": "uwe@hermann-uwe.de", "time": "Sat May 16 22:05:42 2009 +0000" }, "committer": { "name": "Uwe Hermann", "email": "uwe@hermann-uwe.de", "time": "Sat May 16 22:05:42 2009 +0000" }, "message": "Drop unused/duplicated #includes and some dead code\n\nBuild-tested on 32bit x86.\n\nCorresponding to flashrom svn r521.\n\nSigned-off-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n" }, { "commit": "96930c39524225cc55a5625e6e45d7519b3f2528", "tree": "40368d966ea3689aa4c8c2b020984671cc45d1d9", "parents": [ "03adbe12691d512c0d9f28caa93cb35e468fd5d3" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat May 09 02:30:21 2009 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat May 09 02:30:21 2009 +0000" }, "message": "Chips like the SST SST25VF080B can only handle single byte writes outside AAI mode\n\nChange SPI architecture to handle 1-byte chunk chip writing differently\nfrom 256-byte chunk chip writing.\n\nAnnotate SPI chip write functions with _256 or _1 suffix denoting the\nnumber of bytes they write at maximum.\n\nThe 1-byte chunk writing is cut-n-pasted to different SPI drivers right\nnow. A later patch can move them to the generic spi_chip_write_1.\n\nCorresponding to flashrom svn r485.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "03adbe12691d512c0d9f28caa93cb35e468fd5d3", "tree": "9bd6460e4a69d0647706ab139184870b32244441", "parents": [ "c3129208648f241c0b6538235cd4e9854ae6539d" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat May 09 02:09:45 2009 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat May 09 02:09:45 2009 +0000" }, "message": "Refine handling of spi_write_enable() failures to fix chip erases on ichspi\n\nUntil the ICH SPI driver can handle preopcodes as standalone opcodes,\nwe should handle such special opcode failure gracefully on ICH and\ncompatible chipsets.\n\nThis fixes chip erase on almost all ICH+VIA SPI masters.\n\nThanks to Ali Nadalizadeh for helping track down this bug!\n\nCorresponding to flashrom svn r484.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "97e8f22b025da9c2f04e25069d335041ab747a11", "tree": "e1d86f96fd2c51a66151082561f565234ecb8bc7", "parents": [ "d42009c4aebda9fc09844b46226a1e7f23c68c7f" ], "author": { "name": "Uwe Hermann", "email": "uwe@hermann-uwe.de", "time": "Mon Apr 13 21:35:49 2009 +0000" }, "committer": { "name": "Uwe Hermann", "email": "uwe@hermann-uwe.de", "time": "Mon Apr 13 21:35:49 2009 +0000" }, "message": "Fix typo\n\nAdd missing copyright year.\n\nCorresponding to flashrom svn r428 and coreboot v2 svn r4107.\n\nSigned-off-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n" }, { "commit": "13f98cefb784f55ac38e7c90be2975c4ee4bdf92", "tree": "4fa61941e7b6df02ea3ea6fdbf2a762c80485edc", "parents": [ "0faf03e6475c6e2b7a695cbe92b3bfc4fe13b5c1" ], "author": { "name": "Jason Wang", "email": "Qingpei.wang@amd.com", "time": "Sat Nov 29 15:07:15 2008 +0000" }, "committer": { "name": "Stefan Reinauer", "email": "stefan.reinauer@coreboot.org", "time": "Sat Nov 29 15:07:15 2008 +0000" }, "message": "Copyright update by Jason Wang for freshly written sb600 code\n\nCorresponding to flashrom svn r354 and coreboot v2 svn r3782.\n\nSigned-off-by: Jason Wang \u003cQingpei.wang@amd.com\u003e\nReviewed-by: Joe, Bao \u003cZheng.Bao@amd.com\u003e\nAcked-by: Stefan Reinauer \u003cstepan@coresystems.de\u003e\n" }, { "commit": "a3f04be761d45aed2f6113eb2a6d08679370f546", "tree": "b1e437eb9e184676bc4ca62472bfb103ca4d2196", "parents": [ "7f30022fb0fb62a484514e50d5b3f15157a5885d" ], "author": { "name": "Jason Wang", "email": "Qingpei.Wang@amd.com", "time": "Fri Nov 28 21:36:51 2008 +0000" }, "committer": { "name": "Uwe Hermann", "email": "uwe@hermann-uwe.de", "time": "Fri Nov 28 21:36:51 2008 +0000" }, "message": "Add support for the AMD/ATI SB600 southbridge SPI functionality\n\nThis has been tested by Uwe Hermann on an RS690/SB600 board.\n\nCorresponding to flashrom svn r351 and coreboot v2 svn r3779.\n\nSigned-off-by: Jason Wang \u003cQingpei.Wang@amd.com\u003e\nReviewed-by: Joe Bao \u003czheng.bao@amd.com\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n" } ] }