)]}' { "log": [ { "commit": "610c1aad71bfa118c4f49ac01761f586b8dede69", "tree": "8ad4cfd904cf909526b32b03561ad369f42720d9", "parents": [ "b95fe9b9751746b269a3bbd7021cf731d8553715" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Feb 15 02:56:05 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 15 14:27:20 2026 +0000" }, "message": "spi: Pass master instead of flash to .send_command\n\nIn the SPI-master API, `.send_command` should only forward commands to\nthe SPI bus. All details about the commands and the SPI slave should be\nhandled in the chip driver. Hence, replace the `flashctx` pointer with\none to the `spi_master` to enforce proper separation.\n\nChange-Id: I50934a1294217794b7e23cc98ade7e4279c059a1\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74897\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "dac4239136fcbfdd29e5f71cfe8d570d5be26494", "tree": "4068869ae91e978984a79e8eab8b0202aa716293", "parents": [ "56d236bda45dfe9069fd29773965aa269506e0a9" ], "author": { "name": "Nicholas Chin", "email": "nic.c3.14@gmail.com", "time": "Tue Jul 30 20:01:59 2024 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Aug 19 10:58:13 2024 +0000" }, "message": "ch347_spi: Add \u0027spimode\u0027 parameter\n\nThis allows the SPI mode (clock polarity and phase) of the CH347 to be\nselected. By default mode 0 is used, as most flash chips are compatible\nwith this mode. I have noticed that the CH347 is able to work at higher\nclock speeds with some chips when set to mode 1, despite the chip not\nofficially having support for this configuration.\n\nChange-Id: I7938519e23e9e014c016f9d7f130d1ac191a09fa\nSigned-off-by: Nicholas Chin \u003cnic.c3.14@gmail.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/244\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "448457ad4bce249d0165d77f23ea18fb4946508c", "tree": "a1de3df939258bdb95852e1d86807fcdbdb8af88", "parents": [ "e39549b56a4a79a7e4fffa987451b8197053e7ea" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 28 00:02:54 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:56:13 2024 +0000" }, "message": "ch347_spi: Add CH347F ID and loop over the entries\n\nTested with CH347T in mode 1 and CH347F.\n\nChange-Id: I2f8246521b359c5cf574b952b32bee603abcc800\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/198\nReviewed-by: Nicholas Chin \u003cnic.c3.14@gmail.com\u003e\n" }, { "commit": "e39549b56a4a79a7e4fffa987451b8197053e7ea", "tree": "afb761d5402a536539d4fb2d881c76704a98444e", "parents": [ "dfd064759b416463244aafea80a5b7120ef8e4e1" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jul 27 23:58:32 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:56:13 2024 +0000" }, "message": "ch347_spi: Search for compatible USB interface\n\nThe newer CH347F version uses a different interface number. Hence,\nlook for the interface with \"vendor specific\" class, which is what\nthe SPI interface uses.\n\nTested with the original CH347T in mode 1 and upcoming CH347F.\n\nChange-Id: I16d66b2562d9d2ec1540949d63752e939540db5d\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/197\nReviewed-by: Nicholas Chin \u003cnic.c3.14@gmail.com\u003e\n" }, { "commit": "9a11cbf21a5078bcdb8db7584c44a9ee17020db4", "tree": "e67a9eadfdb7a71f81df36c7e97180474a8c59df", "parents": [ "aabb3e0ff54e87c0136c91f105e506ed19184cc6" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 13 01:19:07 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:40:04 2024 +0000" }, "message": "Let the flash context directly point to the used master\n\nWe used to have a pointer to a full `registered_master` struct in\nour flash context. Beside the used master, this contained a bit\nmask of supported buses. Oddly convenient, this bit mask invited\nto bypass the chip driver and break the abstraction. It allowed\nto place bus-specific details virtually anywhere in flashprog,\nmaking it harder to find a good place for them.\n\nSo, get rid of the `buses_supported` bit mask by pointing directly\nto the master. Only the chip driver will implicitly know which type\nof master is used.\n\nChange-Id: I9ce13d8df0e7ccc67519d888dd9cb2e2ff8d6682\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72533\n" }, { "commit": "89569d60e3aeeec651496b2e7a2e6064d782ab3b", "tree": "bf0c3951886de60086d32ff6e1a850adad926da6", "parents": [ "929d2e1b17a448d3352dbecb6a620ee0c1e65a58" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 12 23:31:40 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "memory_mapped: Reduce `decode_sizes` to a single `max_rom_decode`\n\nWe used to store the maximum decode size, i.e. the maximum memory-mapped\nrange of the flash chip, per bus type (Parallel, LPC, FWH, SPI). There\nwas no programmer in the tree that really made use of it, though:\n* The chipset drivers usually focus on a single bus type. And even if\n they advertise the whole default set (PAR, LPC, FWH), they only pro-\n vide a maximum decode size for one of them. The latter is probably\n wrong, should really more than one bus type be supported.\n* PCI and external programmers all support only a single bus type, with\n the exception of `serprog` which doesn\u0027t set a maximum decode size.\n\nWhat made the distinction even less useful is that for some chips that\nsupport multiple bus types, i.e. LPC+FWH, we can\u0027t even detect which\ntype it is. The existing code around this also only tried to provide\nthe best possible warning message at the expense of breaking the pro-\ngrammer abstraction.\n\nHence, unify the set of sizes into a single `max_rom_decode` property.\nWe store it inside the `registered_master` struct right away, to avoid\nany more use of globals.\n\nChange-Id: I2aaea18d5b4255eb843a625b016ee74bb145ed85\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72531\n" }, { "commit": "e3a26888e14d16592c2c79d1516828d3d32961a4", "tree": "02d401e60defd27fe7bee194978bac782284cb39", "parents": [ "2b66ad9c4465432e6f2aff2e95f1e7a556bfc3f0" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jan 11 21:45:51 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "Pass programmer context to programmer-\u003einit()\n\nChange-Id: I064eb4e25c3d382e4e5bde802306698fafe5e1d0\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72526\n" }, { "commit": "c32e954c732b8a7eb894f4d835e16b7f7b496193", "tree": "9e3411b1d9e15dc47f9cdbfea66262b8181ac14d", "parents": [ "111c380b2502df035057806fb727a724b18c815f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 21 00:46:37 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Mar 08 23:15:32 2023 +0000" }, "message": "ch347_spi: Add simple `spispeed` parameter\n\nAdd a programmer parameter `spispeed` that accepts a frequency in kHz\nlike it\u0027s done for other drivers. The frequency will be rounded down\nto the closest possible divisor setting.\n\nChange-Id: Ifa05b95f723dba81bdcc7015dcdf557af5f2e0a8\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73153\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nicholas Chin \u003cnic.c3.14@gmail.com\u003e\n" }, { "commit": "197b7c7b03bc2bbfa6a706812fa69897a3eb7cdb", "tree": "bf6b57efe06c818f4dbec5d54466930930fa52c0", "parents": [ "dafd51e22b30b7e13e79567c065e55d30c788fa2" ], "author": { "name": "Nicholas Chin", "email": "nic.c3.14@gmail.com", "time": "Sun Oct 23 13:10:31 2022 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Feb 25 00:42:12 2023 +0000" }, "message": "ch347_spi: Add initial support for the WCH CH347\n\nAdd support for the WCH CH347, a high-speed USB to bus converter\nsupporting multiple protocols interfaces including SPI. Currently only\nmode 1 (vendor defined communication interface) is supported, mode 2\n(USB HID communication interface) support will be added later. The code\nis currently hard coded to use CS1 and a SPI clock of 15 MHz, though\nthere are 2 CS lines and 6 other GPIO lines available, as well as a\nconfigurable clock divisor for up to 60MHz operation. Support for these\nwill be exposed through programmer parameters in later commits.\n\nThis currently uses the synchronous libusb API. Performance seems to be\nalright so far, if it becomes an issue I may switch to the asynchronous\nAPI.\n\nTested with a MX25L1606E flash chip\n\nSigned-off-by: Nicholas Chin \u003cnic.c3.14@gmail.com\u003e\nChange-Id: I31b86c41076cc45d4a416a73fa1131350fb745ba\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73106\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" } ] }