)]}'
{
  "log": [
    {
      "commit": "610c1aad71bfa118c4f49ac01761f586b8dede69",
      "tree": "8ad4cfd904cf909526b32b03561ad369f42720d9",
      "parents": [
        "b95fe9b9751746b269a3bbd7021cf731d8553715"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Wed Feb 15 02:56:05 2023 +0100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Mar 15 14:27:20 2026 +0000"
      },
      "message": "spi: Pass master instead of flash to .send_command\n\nIn the SPI-master API, `.send_command` should only forward commands to\nthe SPI bus. All details about the commands and the SPI slave should be\nhandled in the chip driver. Hence, replace the `flashctx` pointer with\none to the `spi_master` to enforce proper separation.\n\nChange-Id: I50934a1294217794b7e23cc98ade7e4279c059a1\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74897\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n"
    },
    {
      "commit": "9512c9c16c73e46b6190c9c9fd9ea0555a4d7e24",
      "tree": "64dd2e31837a0feb64034f3404d0d68e2fce9178",
      "parents": [
        "06fbccc61ea5cc8410cb795554dffcfdda111139"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.huber@secunet.com",
        "time": "Thu Jan 30 22:38:18 2025 +0100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Feb 23 17:01:45 2025 +0000"
      },
      "message": "Add missing copyright notices to recently created files\n\nAdd copyright notices for new CLI code (2023), the AMD SPI100\ndriver (2023), and new SPI support code for dual/quad i/o and\nQPI (2024). Initially, some code was moved from `flashprog.c`\ninto `spi25_prepare.c` which dates back to 2017 and 2018.\n\nChange-Id: I980382b8950e2aea6880f4b56df23d4eafc6bb3d\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/318\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n"
    },
    {
      "commit": "4661e7c848efb5fc89b5b0f89c8d6b463702ae28",
      "tree": "995fa43c284e204698b53d418575682b3f810d52",
      "parents": [
        "cdcfda2730e20e8e36a658f6c5f341f05580795f"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Apr 28 21:57:45 2023 +0000"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Wed Mar 27 08:32:15 2024 +0000"
      },
      "message": "amd_spi100: Use flashprog_read_chunked() for progress reporting\n\nRead up to 64 KiB in one go to be able to report progress in between.\nOtherwise, we might read the whole flash at once, without being able\nto report progress.\n\nChange-Id: I4d06f6f5d19944fe22298a1ddfb91244fa7c2eb6\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74867\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n"
    },
    {
      "commit": "9a11cbf21a5078bcdb8db7584c44a9ee17020db4",
      "tree": "e67a9eadfdb7a71f81df36c7e97180474a8c59df",
      "parents": [
        "aabb3e0ff54e87c0136c91f105e506ed19184cc6"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Jan 13 01:19:07 2023 +0100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat Mar 09 10:40:04 2024 +0000"
      },
      "message": "Let the flash context directly point to the used master\n\nWe used to have a pointer to a full `registered_master` struct in\nour flash context. Beside the used master, this contained a bit\nmask of supported buses. Oddly convenient, this bit mask invited\nto bypass the chip driver and break the abstraction. It allowed\nto place bus-specific details virtually anywhere in flashprog,\nmaking it harder to find a good place for them.\n\nSo, get rid of the `buses_supported` bit mask by pointing directly\nto the master. Only the chip driver will implicitly know which type\nof master is used.\n\nChange-Id: I9ce13d8df0e7ccc67519d888dd9cb2e2ff8d6682\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72533\n"
    },
    {
      "commit": "89569d60e3aeeec651496b2e7a2e6064d782ab3b",
      "tree": "bf0c3951886de60086d32ff6e1a850adad926da6",
      "parents": [
        "929d2e1b17a448d3352dbecb6a620ee0c1e65a58"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Thu Jan 12 23:31:40 2023 +0100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat Mar 09 10:30:24 2024 +0000"
      },
      "message": "memory_mapped: Reduce `decode_sizes` to a single `max_rom_decode`\n\nWe used to store the maximum decode size, i.e. the maximum memory-mapped\nrange of the flash chip, per bus type (Parallel, LPC, FWH, SPI). There\nwas no programmer in the tree that really made use of it, though:\n* The chipset drivers usually focus on a single bus type. And even if\n  they advertise the whole default set (PAR, LPC, FWH), they only pro-\n  vide a maximum decode size for one of them. The latter is probably\n  wrong, should really more than one bus type be supported.\n* PCI and external programmers all support only a single bus type, with\n  the exception of `serprog` which doesn\u0027t set a maximum decode size.\n\nWhat made the distinction even less useful is that for some chips that\nsupport multiple bus types, i.e. LPC+FWH, we can\u0027t even detect which\ntype it is. The existing code around this also only tried to provide\nthe best possible warning message at the expense of breaking the pro-\ngrammer abstraction.\n\nHence, unify the set of sizes into a single `max_rom_decode` property.\nWe store it inside the `registered_master` struct right away, to avoid\nany more use of globals.\n\nChange-Id: I2aaea18d5b4255eb843a625b016ee74bb145ed85\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72531\n"
    },
    {
      "commit": "c3b02dce51aad2766512d1939a1b7447c2d526b8",
      "tree": "58069f464bb8a777ef06e93767813a4c5a042cb0",
      "parents": [
        "a02df33fbf1c196395a61049e60895d4ae0e0a5b"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat Aug 12 01:13:45 2023 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Mon Sep 18 19:24:39 2023 +0000"
      },
      "message": "Rebrand to flashprog and update URLs\n\nMostly automated `sed` work. As of now, URLs to the old wiki are broken\neither way, so changing them shouldn\u0027t hurt. Other URLs (e.g. to mailing\nlist archives) were hopefully filtered correctly.\n\nChange-Id: I9d43bfd0e675eff2fcbad05f304b9ce9f5006b08\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashrom-stable/+/21\n"
    },
    {
      "commit": "d2472e5a8e3ee6faa85c3c14b5932c5e96c132e8",
      "tree": "9a6abde0488a16df0df6fa6373106eeb259442f8",
      "parents": [
        "f5fcd742a0568aaf50274bc32e1206f99d65a8b8"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Mar 12 00:44:15 2023 +0000"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Tue Mar 14 23:31:10 2023 +0000"
      },
      "message": "amd_spi100: Check IllegalAccess before executing command\n\nThe SPI controller immediately sets the IllegalAccess flag if we\nconfigured an opcode (and optional address) that is not allowed\nin the current configuration.\n\nChange-Id: Icfa5a2823a302857aef0331ce44221747cf5fdd9\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73678\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n"
    },
    {
      "commit": "f5fcd742a0568aaf50274bc32e1206f99d65a8b8",
      "tree": "efdc370c3cc1fcca883364200bc0b6fff5db83ae",
      "parents": [
        "2d614d61c39eefb2796a6edaecb88a0b31650f3c"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat Mar 11 17:11:12 2023 +0000"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Tue Mar 14 23:31:10 2023 +0000"
      },
      "message": "amd_spi100: Revise 4BA support\n\nWith current SoCs, a flash bigger than 16MiB can\u0027t be fully\nmemory mapped. Also, the memory mapping doesn\u0027t necessarily\nshow us the expected window of the flash.\n\nSo, we consider a memory-mapped read only if we know that\nthe SPI controller\n* sends 32-bit addresses, and\n* doesn\u0027t remap any address bits.\n\nMoreover, we disable support for 4BA mode changes, as we\ncurrently don\u0027t reset the chip state and don\u0027t know if the\ncontroller feels in charge of these.\n\nSending native 4BA commands, however, shouldn\u0027t be a problem,\nso enable these.\n\nChange-Id: I899a89067774334fe15b05bf0b7f2baed5068353\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73677\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n"
    },
    {
      "commit": "2d614d61c39eefb2796a6edaecb88a0b31650f3c",
      "tree": "bcb4b67d76b9dcb2a9de7fa1f6fc82d1e7129bc9",
      "parents": [
        "50fb6f19bb8faad483078d3201977c65e2b57d5c"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat Mar 11 01:06:15 2023 +0100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Tue Mar 14 23:31:10 2023 +0000"
      },
      "message": "amd_spi100: Fix memory-mapped reads for partially mapped chips\n\nIf the memory-mapping doesn\u0027t cover exactly the full flash chip,\nwe have to translate the `start` offset by subtracting the offset\nof the mapping inside the chip\u0027s space (`mapped_start`). This\ncalculation should also work if more than the chip\u0027s size is\nmapped. Then this offset would be negative.\n\nWe also use the newly added `mapped_start` for the preceding\ncalculations in the SPI engine fallback case. It keeps its exact\nsemantics, though.\n\nChange-Id: I4881b2420cb80c079052235ad54cedbb6fa3c945\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73671\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Marty E. Plummer \u003chanetzer@startmail.com\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n"
    },
    {
      "commit": "e3c305dfd234503faa23c5491962db8f52d0134c",
      "tree": "b86a019224a05586e18b98eae8ff0c9b51a1c701",
      "parents": [
        "070587892b4af723bf8f1f423d0b26e12e061084"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Jan 29 21:45:56 2023 +0000"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Tue Feb 28 23:42:48 2023 +0000"
      },
      "message": "amd_spi100: Implement memory-mapped reads\n\nQuery the RomRange2 register for the memory range (usually top below 4G)\nand try to map that. Reads outside this range will still be served via\nthe command engine.\n\nChange-Id: I21aa67d550ccda0f55a9cf3ff14545a881624d11\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72583\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "070587892b4af723bf8f1f423d0b26e12e061084",
      "tree": "7217441f5e207ec4750e912079aae5a3b95ffc05",
      "parents": [
        "d81637c3d7c2bf25f1709b6f28a423e074d906f3"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Jan 29 19:56:39 2023 +0000"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Tue Feb 28 23:42:48 2023 +0000"
      },
      "message": "amd_spi100: Use source-aligned read for the FIFO\n\nMakes reading twice as fast (on this Raven Ridge).\n\nChange-Id: I878c7603e514859c48a9c7823f98a391ea921b21\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72582\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "735b186eeffb997a957075d7e610b9700b53cbe1",
      "tree": "1e27f0dc7f2cae492459530df208859221a1d3ca",
      "parents": [
        "197b7c7b03bc2bbfa6a706812fa69897a3eb7cdb"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Jan 29 18:28:45 2023 +0000"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Tue Feb 28 23:42:48 2023 +0000"
      },
      "message": "amd_spi100: Add new driver for AMD SPI100 controllers\n\nStart with a very simple PIO driver. Reads are slow this way, but\nwe can optimize that later. A factor of 2 is possible simply by\naligning the FIFO reads, and another factor of 3 (at least) with\nmemory-mapped reads.\n\nWe override the SPI speed but choose a conservative value to be\non the safe side. Flashrom only supports normal read commands,\nhence we won\u0027t go over 33MHz. Also, if the firmware set a lower\nspeed for normal reads, we use that. We can\u0027t use dual/quad I/O\nwith the SPI command engine, and tests have shown that increasing\nthe SPI speed lifts the read speed only marginally. It seems to\nbe limited by the FIFO reads.\n\nChange-Id: I403d5f103b3ae72f3a91829d562984c54c2e2d00\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72577\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    }
  ]
}